PO54G374A, PO74G374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 10/27/07 54, 74 Series GHz Logic FEATURES: DESCRIPTION: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency is faster than 600MHz . VCC Operates from 1.65V to 3.6V . Propagation delay < 2.4ns max with 15pf load . Low input capacitance: 4pf typical . Latch-Up Performance Exceeds 250 mA Per JESD 17 . ESD Protection Exceeds JESD 22 . 5000-VHuman-BodyModel (A114-A) . 200-VMachineModel (A115-A) . Available in 20pin TSSOP package . Available in 20pin Ceramic Dual Flatpack . Available in 20pin Leadless Ceramic Chip Carrier Potato Semiconductor’s PO74G374A is designed for world top performance using submicron CMOS technology to achieve higher than 600MHz TTL /CMOS output frequency with less than 2.4ns propagation delay. This dual Octal edge triggered D-type flip-flops are designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 2D 2Q 3Q 3D 4D Pin Description INPUTS 8Q 1 4 3 2 1 20 19 18 5 6 17 16 7 8 15 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND LE 5Q 5D OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1D 1Q OE VCC Pin Configuration Logic Block Diagram OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z OE LE 1 11 C1 1D 3 1D 2 1Q To Seven Other Channels 1 Copyright © Potato Semiconductor Corporation PO54G374A, PO74G374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 10/27/07 54, 74 Series GHz Logic Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -55 to 125 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - 5.5 V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = 5.5V - - 5 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -5 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © Potato Semiconductor Corporation PO54G374A, PO74G374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 10/22/07 54, 74 Series GHz Logic Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 30 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Cin Cout Description Test Conditions Typ Input Capacitance Vin = 0V Output Capacitance Vout = 0V 4 6 Unit pF pF Notes: 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Test Conditions (1) M ax - Min Unit 0.5 ns 0.5 ns - ns tsu th Hold time, data after CLK tPLH Propagation Delay CLK to Q CL = 15pF 2.4 t PHL Propagation Delay CLK to Q CL = 15pF 2.4 tPZH or tPZL Output Enable Time CL = 15pF 2.5 ns tPHZ or tPLZ Output Disable Time CL = 15pF 2.5 ns tr/tf Rise/Fall Time 0.8V – 2.0V - ns fmax Input Frequency CL=2pF - 15pF 600 MHz Setup time before CLK 0.8 - ns Notes: 1. See test circuits and waveforms. 2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 500MHz 3 Copyright © Potato Semiconductor Corporation PO54G374A, PO74G374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 10/22/07 54, 74 Series GHz Logic Test Waveforms VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at V LOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VΔ VOL tPHZ VM VOH - VΔ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Test Circuit Vcc Pulse Generator 50Ω D.U.T 50pF to 2pF 4 Copyright © Potato Semiconductor Corporation PO54G374A, PO74G374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 10/22/07 54, 74 Series GHz Logic Packaging Mechanical Drawing: 20 pin TSSOP 20 .169 .177 1 .252 .260 6.4 6.6 .0256 BSC 0.65 4.3 4.5 .047 1.20 Max .007 0.19 .012 0.30 .018 .030 0.45 0.75 .002 0.05 .006 0.15 SEATING PLANE .238 .269 6.1 6.7 .004 0.09 .008 0.20 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical Drawing: 20pin Leadless Ceramic Chip Carrier 5 Copyright © Potato Semiconductor Corporation PO54G374A, PO74G374A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 10/22/07 54, 74 Series GHz Logic Packaging Mechanical Drawing: 20pin Ceramic Dual Flatpack 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 3 2 1 13 12 4 18 5 17 6 16 0.358 (9,09) 7 0.307 (7,80) 15 8 14 0.358 (9,09) 0.342 (8,69) X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX 9 10 11 12 13 Ordering Information Ordering Code PO74G374ATU PO74G374ATR PO54G374ALU PO54G374AFU Package Top-Marking TA 20pin TSSOP Tube Pb-free & Green PO74G374AT -40°C to 85°C 20pin TSSOP Tape and reel Pb-free & Green PO74G374AT -40°C to 85°C Tube Pb-free & Green PO54G374AL -55°C to 125° C Tube Pb-free & Green PO54G374AF -55°C to 125° C 20pin Leadless Ceramic Chip Carrier 20pin Ceramic Dual Flatpack IC Package Information TAPE WIDTH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE Top Left Corner 39 (12”) 3000 64 (20”) 74 N/A N/A N/A N/A N/A 55 N/A N/A N/A N/A N/A 85 TAPE PITCH (mm) PACKAGE CODE PACKAGE TYPE T TSSOP 20 16 8 L LCCC 20 N/A F CFP 20 N/A 6 Copyright © Potato Semiconductor Corporation