PCS2P3805E September 2006 rev 0.3 3.3V CMOS Dual 1-To-5 Clock Driver Functional Description Features • Advanced CMOS Technology The PCS2P3805E is a 3.3V clock driver built using • Guaranteed low skew < 200pS (max) advanced CMOS technology. The device consists of two • Very low propagation delay < 2.5nS (max) banks of drivers, each with a 1:5 fanout and its own output • Very low duty cycle distortion < 270pS (max) enable control. The device has a "heartbeat" monitor for • Very low CMOS power levels diagnostics and PLL driving. The MON output is identical to • Operating frequency up to 166MHz all other outputs and complies with the output specifications • TTL compatible inputs and outputs in this document. The PCS2P3805E offers low capacitance • Inputs can be driven from 3.3V or 5V components inputs. The PCS2P3805E is designed for high speed clock • Two independent output banks with 3-state control distribution where signal quality and skew are critical. The • 1:5 fanout per bank PCS2P3805E also allows single point-to-point transmission • "Heartbeat" monitor output line driving in applications such as address distribution, • VCC = 3.3V ± 0.3V where one signal must be distributed to multiple receivers • Available in SSOP and QSOP Packages with low skew and high signal quality. Block Diagram Pin Diagram OEA INA INB 5 5 OA1 – OA5 OB1 – OB5 OEB VCCA 1 20 VCCB OA1 2 19 OB1 OA2 3 18 OB2 OA3 4 17 OB3 GNDA 5 16 GNDB OA4 6 15 OB4 OA5 7 14 OB5 GNDQ 8 13 MON OEA 9 12 OEB INA 10 11 INB MON PCS2P3805E PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS2P3805E September 2006 rev 0.3 Pin Description Pin # Pin Names 9,12 ¯¯ B OE ¯¯ A, OE 10,11 INA, INB Clock Inputs 2,3,4,6,7 OA1-OA5 Clock Outputs from Bank A 19,18,17,15,14 OB1-OB5 Clock Outputs from Bank B 1 VCCA Power supply for Bank A 20 VCCB Power supply for Bank B 5 GNDA Ground for Bank A 16 GNDB Ground for Bank B 8 GNDQ Ground 13 MON Monitor Output Description 3-State Output Enable Inputs (Active LOW) Function Table1 Inputs Outputs OE ¯¯ A, OE ¯¯ B INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H Note: 1 H = HIGH; L = LOW; Z = High-Impedance Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter1 Conditions Typ Max Unit CIN Input Capacitance VIN= 0V 3 4 pF COUT Output Capacitance VOUT = 0V - 6 pF Note: 1 This parameter is measured at characterization but not tested. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 2 of 11 PCS2P3805E September 2006 rev 0.3 Absolute Maximum Ratings1 Symbol Max Unit Input Power Supply Voltage -0.5 to +4.6 V VI Input Voltage -0.5 to +5.5 V VO Output Voltage -0.5 to VCC+0.5 V TJ Junction Temperature 150 °C TSTG Storage Temperature -65 to +165 °C 2 KV VCC TDV Description Static Discharge Voltage (As per JEDEC STD22- A114-B) Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V Symbol Test Conditions1 Parameter Min Typ2 Max Unit VIH Input HIGH Level 2 - 5.5 V VIL Input LOW Level -0.5 - 0.8 V IIH Input HIGH Current VCC= Max. VI = 5.5V - - ±1 IIL Input LOW Current VCC= Max. VI = GND - - ±1 VO = VCC - - ±1 VO = GND - - ±1 IOZH IOZL VIK High Impedance Output Current (3-State Outputs Pins) VCC= Max. Clamp Diode Voltage VCC= Min., IIN = –18mA µA - -0.7 -1.2 V 3,4 IODH Output HIGH Current VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V -45 -74 -180 mA IODL Output LOW Current VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V3,4 50 90 200 mA -60 -135 -240 mA IOL= 12mA 2.45 3 - IOH= –8mA 5 2.4 3 - VCC - 0.2 - - IOL= 12mA - 0.3 0.4 IOL= 8mA - 0.2 0.4 IOL= 100µA - - 0.2 IOS VOH Short Circuit Current Output HIGH Voltage 3,4 VCC= Max., VO = GND VCC= Min. VIN = VIH or VIL IOH= –100µA VOL Output LOW Voltage VCC= Min. VIN = VIH or VIL V V Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, 25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 3 of 11 PCS2P3805E September 2006 rev 0.3 Power Supply Characteristics Symbol Parameter Test Conditions1 Min Typ2 Max Unit ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max. VIN = GND or VCC - 0.1 30 µA ∆ICC Power Supply Current per Input HIGH VCC = Max. VIN = VCC –0.6V - 45 300 µA VIN = VCC VIN = GND - 80 120 µA/MHz VIN = VCC VIN = GND - 210 240 VIN = VCC –0.6V VIN = GND - 210 240 VIN = VCC VIN = GND - 260 310 VIN = VCC –0.6V VIN= GND - 260 310 ICCD IC VCC= Max. Dynamic Power Supply CL= 15pF 3 Current per Output All Outputs Toggling Total Power Supply 4 Current VCC= Max. CL= 15pF All Outputs Toggling fi = 133MHz VCC= Max. CL= 15pF All Outputs Toggling fi = 166MHz mA Notes: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 4 of 11 PCS2P3805E September 2006 rev 0.3 Switching Characteristics Over Operating Range – PCS2P3805E3,4 Symbol tPLH tPHL Parameter Conditions1,8 Propagation Delay INA to OAn, INB to OBn Min2 Max Unit 0.5 2.5 nS tR Output Rise Time (Measured from 0.7V to 1.7V) - 1 nS tF Output Fall Time (Measured from 1.7V to 0.7V) - 1 nS tSK(O) Same device output pin to pin skew5 - 200 pS tSK(P) Pulse skew6,9 - 270 pS tSK(PP) Part to part skew7 - 550 pS tPZL tPZH Output Enable Time ¯¯ B to OBn ¯¯ A to OAn, OE OE - 5.2 nS tPLZ tPHZ Output Disable Time ¯¯ A to OAn, OE ¯¯ B to OBn OE - 5.2 nS fMAX Input Frequency - 166 MHz CL= 15pF f ≤166MHz Notes: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH , tPHL and tSK(O) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min and Max limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 5. Skew measured between all outputs under identical transitions and load conditions. 6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions. 7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature. 8. Airflow of 1m/s is recommended for frequencies above 133MHz. 9. This parameter is measured using f = 1MHz. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 5 of 11 PCS2P3805E September 2006 rev 0.3 Test Circuits and Waveforms 6V VCC Open GND 500Ω VIN VOUT Pulse Generator D.U.T RL CL RT 500Ω Enable and Disable Time Circuit VCC 3V INPUT tPHL1 tPLH1 VIN VOUT Pulse Generator D.U.T RL RT 1.5V 0V VOH OUTPUT 1 CL tSK(O) 1.5V VOL tSK(O) VOH OUTPUT 2 1.5V VOL tPHL2 tPLH2 CL = 15pF Test Circuit tSK(O) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | Output Skew – tSK(o) Switch Position Test Conditions Test Switch Disable Low Enable Low 6V Disable High Enable High GND Symbol VCC = 3.3V ±0.3V Unit CL 15 pF RT ZOUT of pulse generator Ω RL 33 Ω t R / tF 1 (0V to 3V or 3V to 0V) nS Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 6 of 11 PCS2P3805E September 2006 rev 0.3 Test Circuits and Waveforms ENABLE DISABLE 3V CONTROL INPUT 1.5V OUTPUT NORMALLY SWITCH LOW CLOSED SWITCH OPEN VOH 0.3V VOH Package 1 OUTPUT VOL tPHZ tPZH OUTPUT NORMALLY HIGH tPLZ VOH 1.5V tSK(PP) 1.5V VOL 0.3V VOH tSK(PP) tSK(PP) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | Note: Part-to- Part Skew is for package and speed grade. 3V INPUT 1.5V 0V tPHL 3V INPUT tPHL tPLH VOH 2.0V 0.8V tF 1.5V VOL Part-to- Part Skew Note: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH tR VOH tPHL2 tPLH2 VOL OUTPUT 1.5V VOL Package 2 OUTPUT Enable and Disable Times tPLH 1.5V 0V tPHL1 tPLH1 0V tPZL 3V INPUT 1.5V 1.5V 0V VOH OUTPUT VOL 1.5V tSK(P) = | tPLH - tPLH | VOL Pulse Skew Propagation Delay 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 7 of 11 PCS2P3805E September 2006 rev 0.3 Package Information 20-lead SSOP ( 209 mil ) Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.079 … 2.0 A1 0.002 … 0.05 ….. A2 0.065 0.073 1.65 1.85 D 0.275 0.291 7.00 7.40 c 0.004 0.010 0.09 0.25 E 0.295 0.319 7.50 8.10 E1 0.197 0.220 5.00 5.60 L 0.021 0.037 0.55 0.95 L1 0.050 REF 1.25 REF b 0.009 0.015 0.22 0.38 R1 0.004 …. 0.09 …. a 0° 8° 0° 8° e 0.0197 BASE 0.65 BASE 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 8 of 11 PCS2P3805E September 2006 rev 0.3 20-lead QSOP Symbol Dimensions Inches Millimeters Min Max Min Max A 0.060 0.068 1.52 1.73 A1 0.004 0.008 0.10 0.20 b 0.009 0.012 0.23 0.30 c 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e 0.025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 S 0.056 0.060 1.42 1.52 a 0° 8° 0° 8° 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 9 of 11 PCS2P3805E September 2006 rev 0.3 Ordering Information Part Number Marking Package Type Temperature PCS2P3805EG-20-AR 2P3805EG 20-Pin SSOP, TAPE & REEL, Green Commercial PCS2P3805EG-20-AT 2P3805EG 20-Pin SSOP, TUBE, Green Commercial PCS2P3805EG-20-DR 2P3805EG 20-Pin QSOP, TAPE & REEL, Green Commercial PCS2P3805EG-20-DT 2P3805EG 20-Pin QSOP, TUBE, Green Commercial PCS2I3805EG-20-AR 2I3805EG 20-Pin SSOP, TAPE & REEL, Green Industrial PCS2I3805EG-20-AT 2I3805EG 20-Pin SSOP, TUBE, Green Industrial PCS2I3805EG-20-DR 2I3805EG 20-Pin QSOP, TAPE & REEL, Green Industrial PCS2I3805EG-20-DT 2I3805EG 20-Pin QSOP, TUBE, Green Industrial Device Ordering Information P C S 2 P 3 8 0 5 E G - 2 0 - A T R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 10 of 11 PCS2P3805E September 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P3805E Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 11 of 11