PCS2P3805A September 2006 rev 0.3 3.3V CMOS Buffer Clock Driver Functional Description Features • Advanced CMOS Technology The PCS2P3805A is a 3.3V, non-inverting clock driver built • Guaranteed low skew < 500pS (max.) using advanced CMOS technology. The device consists of • Very low duty cycle distortion < 1.0nS (max) two banks of drivers, each with a 1:5 fanout and its own • Very low CMOS power levels output enable control. The device has a "heartbeat" monitor • TTL compatible inputs and outputs for diagnostics and PLL driving. The MON output is • Inputs can be driven from 3.3V or 5V components identical to all other outputs and complies with the output • Two independent output banks with 3-state control specifications in this document. The PCS2P3805A offers • 1:5 fanout per bank low capacitance inputs. • "Heartbeat" monitor output • VCC = 3.3V ± 0.3V The PCS2P3805A is designed for high speed clock • Available in SSOP, SOIC and QSOP Packages distribution where signal quality and skew are critical. The PCS2P3805A also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Block Diagram OEA INA INB 5 5 OA1 – OA5 OB1 – OB5 OEB MON PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS2P3805A September 2006 rev 0.3 Pin Diagram VCCA 1 20 VCCB OA1 2 19 OB1 OA2 3 18 OB2 OA3 4 17 OB3 GNDA 5 16 GNDB OA4 6 15 OB4 OA5 7 14 OB5 GNDQ 8 13 MON OEA 9 12 OEB INA 10 11 INB PCS2P3805A Pin Description Pin # Pin Names 9,12 ¯¯ B OE ¯¯ A, OE 10,11 INA, INB Clock Inputs 2,3,4,6,7 OA1-OA5 Clock Outputs 19,18,17,15,14 OB1-OB5 Clock Outputs 1 VCCA Power supply for Bank A 20 VCCB Power supply for Bank B 5 GNDA Ground for Bank A 16 GNDB Ground for Bank B 8 GNDQ Ground 13 MON Monitor Output Description 3-State Output Enable Inputs (Active LOW) 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 2 of 12 PCS2P3805A September 2006 rev 0.3 Function Table Inputs Outputs OE ¯¯ A, OE ¯¯ B INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H Note: H = HIGH; L = LOW; Z = High-Impedance Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter1 Conditions Typ Max Unit CIN Input Capacitance VIN= 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF Note: 1 This parameter is measured at characterization but not tested. Absolute Maximum Ratings1 Symbol 2 VTERM VTERM3 4 VTERM Description Max Unit Terminal Voltage with Respect to GND -0.5 to +4.6 V Terminal Voltage with Respect to GND -0.5 to +7 V Terminal Voltage with Respect to GND -0.5 to VCC+0.5 V IOUT DC Output Current -60 to +60 mA TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature 150 °C Ts Max. Soldering Temperature (10 sec) 260 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 2. VCC terminals. 3. Input terminals. 4. Outputs and I/O terminals. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 3 of 12 PCS2P3805A September 2006 rev 0.3 DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V; Industrial: TA = -40 0°C to +85°C, VCC = 3.3V ± 0.3V Symbol VIH Parameter Input HIGH Level (Input pins) Test Conditions1 Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL IIH IIL IOZH IOZL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level Input HIGH Current (Input pins) Min Typ2 Max 2 5.5 2 VCC+ 0.5 -0.5 0.8 VI = 5.5V ±1 Input HIGH Current (I/O pins) VI = VCC ±1 Input LOW Current (Input pins) VI = GND ±1 Input LOW Current (I/O pins) VI = GND ±1 High Impedance Output Current VCC= Max. (3-State Output Pins) VO = VCC ±1 VO = GND ±1 VCC= Max. VCC= Max. VIK Clamp Diode Voltage VCC= Min., IIN = -18mA IODH Output HIGH Current VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V IODL Output LOW Current VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V VOH Output HIGH Voltage VCC= Min. VIN = VIH or VIL IOH= -0.1mA IOH= -8mA VOL Output LOW Voltage IOFF Input Power Off Leakage IOS Short Circuit Current VH Input Hysteresis ICCL ICCH ICCZ Quiescent Power Supply Current 4 µA µA V -36 -60 -110 mA 50 90 200 mA VCC–0.2 2.45 V 3 0.2 0.2 0.4 IOL= 24mA 0.3 0.5 VCC= 0V, VIN = 4.5V 3 V -1.2 IOL= 16mA VCC= Max., VO = GND V -0.7 IOL= 0.1mA VCC= Min. VIN = VIH or VIL Unit -60 -135 ±1 µA -240 mA 150 VCC= Max. VIN = GND or VCC mV 0.1 10 Notes:1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC - 0.6V at rated current. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. V 4 of 12 µA PCS2P3805A September 2006 rev 0.3 Power Supply Characteristics Symbol Parameter Test Conditions1 ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC= Max. VIN = VCC –0.6V ICCD Dynamic Power Supply Current 4 Min 3 VCC= Max. Outputs Open ¯¯ B= GND OE ¯¯ A = OE Per Output Toggling 50% Duty Cycle VIN= VCC VIN= GND VIN= VCC VCC= Max. VIN= GND Outputs Open fO= 25MHz 50% Duty Cycle OE ¯¯ A = OE ¯¯ B= VCC VIN= VCC-0.6V Mon. Output Toggling VIN= GND IC Total Power Supply Current Typ2 Max Unit 10 30 µA 0.035 0.06 mA/ MHz 0.9 1.6 0.9 1.6 6 mA VCC= Max. Outputs Open fO= 50MHz 50% Duty Cycle OEA = OEB= GND Eleven Outputs Toggling VIN= VCC VIN= GND 45 62 VIN= VCC-0.6V VIN= GND 45 62 5 5 Notes: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the IC formula. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 5 of 12 PCS2P3805A September 2006 rev 0.3 Switching Characteristics Over Operating Range – Commercial3,4 Symbol tPLH tPHL tR tF Conditions1 Parameter PCS2P3805A 2 Unit Min Max 1.5 5 nS Output Rise Time (0.8V to 2.0V) 2 nS Output Fall Time (2.0V to 0.8V) 2 nS 0.5 nS 1 nS 1.2 nS Propagation Delay INA to OAn, INB to OBn tSK(O) Output skew: skew between outputs of all banks of same package (inputs tied together) tSK(P) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) tSK(T) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade tPZL tPZH Output Enable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 6 nS tPLZ tPHZ Output Disable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 5 nS CL= 50pF RL= 500Ω Switching Characteristics Over Operating Range – Industrial3,4 Symbol tPLH tPHL tR tF Conditions1 Parameter PCS2P3805A 2 Unit Min Max 1.5 5.2 nS Output Rise Time (0.8V to 2.0V) 2 nS Output Fall Time (2.0V to 0.8V) 2 nS 0.6 nS 1 nS 1.2 nS Propagation Delay INA to OAn, INB to OBn tSK(O) Output skew: skew between outputs of all banks of same package (inputs tied together) tSK(P) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) tSK(T) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade tPZL tPZH Output Enable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 6 nS tPLZ tPHZ Output Disable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 5 nS CL= 50pF RL= 500Ω Note: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 6 of 12 PCS2P3805A September 2006 rev 0.3 Test Circuits and Waveforms Switch Position VCC 6V Test Switch Disable Low Enable Low 6V Disable High Enable High GND GND 500Ω VIN VOUT Pulse Generator D.U.T 50pF RT 500Ω Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs 3V INPUT 1.5V 0V tPHL tPLH 3V INPUT 2.0V OUTPUT 0.8V tR tF 1.5V VOH OUTPUT 1 1.5V VOL VOL tSK(O) tSK(O) VOH OUTPUT 2 Package Delay 3V INPUT tPHL2 tPLH2 tSK(O) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | 1.5V 0V tPHL tPLH tPHL1 tPLH1 VOH Output Skew – tSK(o) VOH OUTPUT 1.5V VOL tSK(P) = | tPLH - tPLH | CONTROL INPUT OUTPUT NORMALLY SWITCH LOW CLOSED SWITCH OPEN tPLZ 3.5V 1.5V tPLH2 VOL tPHL2 tSK(t) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | tPHZ 1.5V 0V tSK(t) Package 2 OUTPUT 3.5V 0.3V tPZH OUTPUT NORMALLY HIGH tSK(t) 1.5V 0V Package Skew – tSK(t) 0.3V VOH 0V 1.5V 0V VOH Package 1 OUTPUT DISABLE 3V tPZL tPHL1 tPLH1 Pulse Skew ENABLE 3V INPUT Note: Pulse Generator for all Pulses:f ≤ 10MHz; tF ≤ 2.5nS; tR ≤ 2.5nS Enable and Disable Times Note: Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 7 of 12 1.5V VOL VOH 1.5V VOL PCS2P3805A September 2006 rev 0.3 Package Information 20-lead SSOP ( 209 mil ) Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.079 … 2.0 A1 0.002 … 0.05 ….. A2 0.065 0.073 1.65 1.85 D 0.275 0.291 7.00 7.40 c 0.004 0.010 0.09 0.25 E 0.295 0.319 7.50 8.10 E1 0.197 0.220 5.00 5.60 L 0.021 0.037 0.55 0.95 L1 0.050 REF 1.25 REF b 0.009 0.015 0.22 0.38 R1 0.004 …. 0.09 …. a 0° 8° 0° 8° e 0.0197 BASE 0.65 BASE 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 8 of 12 PCS2P3805A September 2006 rev 0.3 20-lead QSOP Symbol Dimensions Inches Millimeters Min Max Min Max A 0.060 0.068 1.52 1.73 A1 0.004 0.008 0.10 0.20 b 0.009 0.012 0.23 0.30 c 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e 0.025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 S 0.056 0.060 1.42 1.52 a 0° 8° 0° 8° 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 9 of 12 PCS2P3805A September 2006 rev 0.3 20L SOIC Package (300 mil) Dimensions Symbol Inches Min Max Millimeters Min Max A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 A2 0.088 0.094 2.25 2.40 D 0.496 0.512 12.60 13.00 L 0.016 0.050 0.40 1.27 E1 0.291 0.299 7.40 7.60 R1 0.003 …. 0.08 ….. b 0.013 0.022 0.33 0.56 c 0.009 0.015 0.23 0.38 E 0.394 0.419 10.00 10.65 e a 0.050 BSC 0° 1.27 BSC 8° 0° 8° 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 10 of 12 PCS2P3805A September 2006 rev 0.3 Ordering Information Part Number Marking Package Type Temperature PCS2P3805AG-20-AR 2P3805AG 20-Pin SSOP, TAPE & REEL, Green Commercial PCS2P3805AG-20-AT 2P3805AG 20-Pin SSOP, TUBE, Green Commercial PCS2P3805AG-20-DR 2P3805AG 20-Pin QSOP, TAPE & REEL, Green Commercial PCS2P3805AG-20-DT 2P3805AG 20-Pin QSOP, TUBE, Green Commercial PCS2P3805AG-20-SR 2P3805AG 20-Pin SOIC, TAPE & REEL, Green Commercial PCS2P3805AG-20-ST 2P3805AG 20-Pin SOIC, TUBE, Green Commercial PCS2I3805AG-20-AR 2I3805AG 20-Pin SSOP, TAPE & REEL, Green Industrial PCS2I3805AG-20-AT 2I3805AG 20-Pin SSOP, TUBE, Green Industrial PCS2I3805AG-20-DR 2I3805AG 20-Pin QSOP, TAPE & REEL, Green Industrial PCS2I3805AG-20-DT 2I3805AG 20-Pin QSOP, TUBE, Green Industrial PCS2I3805AG-20-SR 2I3805AG 20-Pin SOIC, TAPE & REEL, Green Industrial PCS2I3805AG-20-ST 2I3805AG 20-Pin SOIC, TUBE, Green Industrial Device Ordering Information P C S 2 P 3 8 0 5 A G - 2 0 - D R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 11 of 12 PCS2P3805A September 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P3805A Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 12 of 12