ASM2P5T9070A November 2006 rev 0.2 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Features The ASM2P5T9070A 2.5V single data rate (SDR) clock • Optimized for 2.5V LVTTL buffer is a single-ended input to ten single-ended outputs • Guaranteed Low Skew < 25pS (max) buffer built on advanced metal CMOS technology. The • Very low duty cycle distortion < 300pS (max) SDR clock buffer fanout from a single input to ten single- • High speed propagation delay < 2nS. (max) ended outputs reduces the loading on the preceding driver • Up to 200MHz operation and provides an efficient clock distribution network. • Very low CMOS power levels The ASM2P5T9070A has two output banks that can be • Hot Insertable and over-voltage tolerant inputs asynchronously enabled/disabled. Multiple power and • 1:10 fanout buffer grounds reduce noise. • 2.5V Supply Voltage • Available in TSSOP Package Applications: ASM2P5T9070A is targeted towards Clock and signal distribution applications. Functional Description Block Diagram GL G1 A G2 OUTPUT CONTROL Q1 OUTPUT CONTROL Q2 OUTPUT CONTROL Q3 OUTPUT CONTROL Q4 OUTPUT CONTROL Q5 OUTPUT CONTROL Q6 OUTPUT CONTROL Q7 OUTPUT CONTROL Q8 OUTPUT CONTROL Q9 OUTPUT CONTROL Q10 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. ASM2P5T9070A November 2006 rev 0.2 Pin Configuration Top View – TSSOP Package 48 GND 2 47 VDD 3 46 VDD GND 4 45 GND GND 5 44 GND G1 6 43 GND VDD 7 42 VDD Q2 8 41 Q3 9 40 Q4 39 GND GL VDD 1 VDD Q1 Pin Description ASM2P5T9070A GND VDD 10 11 38 VDD GND 12 37 Q5 A 13 36 Q6 VDD 14 35 VDD GND 15 34 Q10 16 33 GND Q7 Q9 VDD 17 18 32 Q8 31 VDD G2 19 30 VDD GND 20 29 GND GND 21 28 VDD 22 GND VDD VDD 23 27 24 GND NC 26 25 NC Symbol I/O Type Description A I LVTTL Clock input G1 I LVTTL Gate for outputs Q1 through Q5. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchronously disabled to the level designated by GL1. G2 I LVTTL GL I LVTTL Qn VDD GND O LVTTL PWR PWR Gate for outputs Q6through Q10. When G2 is LOW, these outputs are enabled. When G2 is HIGH, these outputs are asynchronously disabled to the level designated by GL1. Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs Power supply for the device core, inputs, and outputs Power supply return for power NOTE: Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 2 of 9 ASM2P5T9070A November 2006 rev 0.2 Absolute Maximum Ratings1 Symbol VDD Description Power Supply Voltage VI Input Voltage VO Output Voltage TSTG TJ Max Unit -0.5 to +3.6 V -0.5 to +3.6 V -0.5 to VDD +0.5 V -65to +165 °C °C Storage Temperature Junction Temperature 150 Note: 1.These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Capacitance1 (TA = +25°C, F = 1.0MHz) Symbol CIN Parameter Min Typ Input Capacitance Max Unit 6 pF NOTE: 1. This parameter is measured at characterization but not tested. Recommended Operating Range Symbol Description Min Typ Max Unit TA Ambient Operating Temperature -40 +25 +85 °C VDD Internal Power Supply Voltage 2.3 2.5 2.7 V DC Electrical Characteristics Over Operating Range1 Symbol Parameter Test Conditions Min Typ4 Max IIH Input HIGH Current VDD= 2.7V VI = VDD/GND ±5 IIL Input LOW Current VDD= 2.7V VI = GND/VDD ±5 VIK Clamp Diode Voltage VDD= 2.3V, IIN = -18mA VIN DC Input Voltage - 0.7 -0.3 2 VIH DC Input HIGH 1.7 VIL DC Input LOW3 - VOH VOL Output HIGH Voltage Output LOW Voltage IOH= -12mA VDD- 0.4 IOH= -100µA VDD- 0.1 IOL= 12mA IOL= 100µA Notice: The information in this document is subject to change without notice. µA - 1.2 V +3.6 V V 0.7 V V V 0.4 0.1 NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Voltage required to maintain a logic HIGH. 3. Voltage required to maintain a logic LOW. 4. Typical values are at VDD = 2.5V, +25°C ambient. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Unit 3 of 9 V V ASM2P5T9070A November 2006 rev 0.2 Power Supply Characteristics Symbol IDDQ IDDD ITOT Parameter Quiescent VDD Power Supply Current Dynamic VDD Power Supply Current per Output Test Conditions1 Typ Max Unit VDD= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded 1.5 2 mA VDD= Max., VDD= Max., CL= 0pF 150 200 µA/MHz 70 90 100 150 VDD= 2.5V., FREFERENCE CLOCK= 100MHz, CL= 15pF VDD= 2.5V., FREFERENCE CLOCK= 200MHz, CL= 15pF Total Power VDD Supply Current mA NOTE: 1. The termination resistors are excluded from these measurements. Input AC Test Conditions Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VTH Input Timing Measurement Reference Level tR, tF Input Signal Edge Rate2 1 Value Units VDD V 0 V VDD/2 V 2 V/nS NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform. AC Electrical Characteristics Over Operating Range4 Symbol Parameter Min Typ Max Unit Skew Parameters tSK(O) Same Device Output Pin-to-Pin Skew1 25 pS tSK(P) Pulse Skew2 300 pS tSK(PP) Part-to-Part Skew3 300 pS 2 nS Propagation Delay tPLH tPHL Propagation Delay A to Qn tR Output Rise Time (20% to 80%) 350 850 pS tF Output Fall Time (20% to 80%) 350 850 pS fO Frequency Range 200 MHz 3.5 nS 3 nS Output Gate Enable/Disable Delay tPGE Output Gate Enable to Qn tPGD Output Gate Enable to Qn Driven to GL Designated Level NOTES: 1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device. 2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device. 3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels and temperature. 4. Guaranteed by design. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 4 of 9 ASM2P5T9070A November 2006 rev 0.2 AC Timing Waveforms Propagation and Skew Waveforms NOTE: Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse. Gate Disable/Enable Runt Pulse Generation NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 5 of 9 ASM2P5T9070A November 2006 rev 0.2 Test Circuit and Conditions Test Circuit for Input/Output Input/Output Test Conditions Symbol VDD= 2.5V ± 0.2V VTH VDD/ 2 V R1 100 Ω R2 100 Ω CL 15 pF 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. Unit 6 of 9 ASM2P5T9070A November 2006 rev 0.2 Package Information 48-lead TSSOP (6.10 mm Body, JEDEC MO-153-ED) Dimensions Symbol Inches Millimeters Min Max Min Max A .... 0.047 … 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.041 0.8 1.05 b 0.008 BSC 0.20 BSC c 0.004 0.008 0.09 0.20 D 0.488 0.496 12.40 12.60 E1 0.236 0.244 6.00 6.20 E 0.319 BSC 8.10 BSC e 0.020 BSC 0.50 BSC L 0.018 0.030 N α 0.45 0.75 0° 8° 48 0° 8° 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 7 of 9 ASM2P5T9070A November 2006 rev 0.2 Ordering Information Part Number Marking ASM2P5T9070AF-48TT 2P5T9070AF ASM2P5T9070AF-48TR ASM2I5T9070AF-48TT Package Type Operating Range 48 Pin TSSOP, Tube, Pb Free Commercial 2P5T9070AF 48 Pin TSSOP, Tape and Reel, Pb Free Commercial 2I5T9070AF 48 Pin TSSOP, TUBE, Pb Free Industrial ASM2I5T9070AF-48TR 2I5T9070AF 48 Pin TSSOP, Tape and Reel, Pb Free Industrial ASM2P5T9070AG-48TT 2P5T9070AG 48 Pin TSSOP, Tube, Green Commercial ASM2P5T9070AG-48TR 2P5T9070AG 48 Pin TSSOP, Tape and Reel, Green Commercial ASM2I5T9070AG-48TT 2I5T9070AG 48 Pin TSSOP, TUBE, Green Industrial ASM2I5T9070AG-48TR 2I5T9070AG 48 Pin TSSOP, Tape and Reel, Green Industrial Ordering Information A S M 2 P 5 T 9 0 7 0 A F - 4 8 T R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 8 of 9 ASM2P5T9070A November 2006 rev 0.2 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: ASM2P5T9070 Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 9 of 9