PULSECORE PCS2P5T915AG

PCS2P5T915A
September 2006
rev 0.2
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Features
input, the PCS2P5T915A replicates the input to 10
outputs
organised
as
output
pairs
for
differential
•
Very low Output Skew : < 25 pS (max )
signalling.
•
Very low Duty Cycle Distortion : 300 pS (max )
The PCS2P5T915A performs as a translator or converter
•
Low Propagation delays : 2nS (max )
for a differential HSTL, eHSTL, 1.8V/2.5V LVTTL or
•
DC to 250MHz Operating Range
CMOS, LVPECL or single ended 1.8V/2.5V LVTTL or
•
Very low Power Consumption
CMOS inputs to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs
•
Hot insertable
A user interface for configuration/selection is controlled
•
Over-Voltage Tolerant Inputs
via a three level input that can be wired or conditioned
•
Very Low Cycle to cycle Jitter
for the appropriate low-mid-high levels. In addition, the
•
2.5V Supply Voltage
PCS2P5T915A true or complementary outputs may be
•
Isolated Output Power (VDDQ)
asynchronously enabled and/or disabled. Multiple power
•
3 level inputs for selectable interface
pins for power and and returns guarantee the low skews
•
Selectable Inputs : HSTL, eHSTL, 1.8V/2.5V
and high accuracy.
LVTTL or LVPECL
•
Available in Standard 48 pin TSSOP Package
•
Lead Free Option
Applications
• High Accuracy Clock Signal Fan-out and Distribution
• Specialty Synchronous Memory Clock Support
Product Description
The
PCS2P5T915A
• Data Communications
is
a
versatile
user
configurable/selectable 2.5V differential buffer for fanout
and distribution of a high accuracy clock reference
Switches
Routers
Hubs.
source. Accepting either a single ended or a differential
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PCS2P5T915A
September 2006
rev 0.2
PCS2P5T915A Functional Block Diagram
TxS
GL
G(+)
RxS
A
A / VREF
G(-)
Output
Control
Q1
Output
Control
Q1
Output
Control
Q2
Output
Control
Q2
Output
Control
Q3
Output
Control
Q3
Output
Control
Q4
Output
Control
Q4
Output
Control
Q5
Output
Control
Q5
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
2 of 23
PCS2P5T915A
September 2006
rev 0.2
Pin Configuration
GL
1
48
GND
VDD
2
47
VDDQ
VDD
3
46
VDDQ
GND
4
45
GND
GND
5
44
GND
G(+)
6
43
GND
VDDQ
7
42
VDDQ
8
41
Q1
Q1
9
PCS2P5T915A
40
Q2
Q2
39
GND
VDDQ
GND
10
VDDQ
11
38
A/VREF
12
37
Q3
13
36
35
Q3
VDDQ
A
VDDQ
14
GND
15
16
34
GND
33
32
VDDQ
17
18
Q4
Q4
VDDQ
G(-)
19
GND
20
GND
VDD
21
22
30
29
28
27
VDD
23
RxS
24
Q5
Q5
31
26
25
VDDQ
GND
GND
VDDQ
GND
TxS
Absolute Maximum Ratings1
Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met.
3. Not to exceed 3.6V.
Symbol
VDD
VDDQ
VI
VO
Description
Max
Unit
-0.5 to +3.6
V
Output Power Supply
-0.5 to +3.6
V
Input Voltage
-0.5 to +3.6
V
Power Supply Voltage2
2
Output Voltage
3
-0.5 to VDDQ +0.5
V
VREF
Reference Voltage3
-0.5 to +3.6
V
TSTG
Storage Temperature
-65 to +165
°C
TJ
Junction Temperature
150
°C
Capacitance1,2 (TA = +25°C, F = 1.0MHz)
Symbol
Parameter
CIN
Min
Input Capacitance
Typ
Max
3.5
Unit
pF
Notes: 1. This parameter is measured at characterization but not tested.
2. Capacitance applies to all inputs except RxS and TxS.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
3 of 23
PCS2P5T915A
September 2006
rev 0.2
Recommended Operating Range
Symbol
Description
TA
1
VDD
VDDQ1
VT
Ambient Operating Temperature
Internal Power Supply Voltage
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
2.5V LVTTL Output Power Supply Voltage
Min
Typ
Max
Unit
-40
2.4
1.4
1.65
+25
2.5
1.5
1.8
VDD
+85
2.6
1.6
1.95
°C
V
V
V
V
Termination Voltage
VDDQ/ 2
V
Note: 1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
Pin Description
Symbol I/O
Type
Description
1
A
I
Adjustable
A/VREF
I
Adjustable1
G(+)
I
LVTTL
G(-)
I
LVTTL
GL
I
LVTTL5
Qn
Qn
O
Adjustable2
O
Adjustable
RxS
I
3 Level3
TxS
I
3 Level3
5
5
2
VDD
PWR
VDDQ
PWR
GND
PWR
Clock input. A is the "true" side of the differential clock input. If operating in single-ended
mode, A is the clock input.
Complementary clock input. A/VREF is the "complementary" side of A if the input is in
differential mode. If operating in single-ended mode, A/VREF is connected to GND. For
single-ended operation in differential mode, A/VREF should be set to the desired toggle
voltage for A:
2.5V LVTTL
VREF = 1250mV
1.8V LVTTL, eHSTL
VREF = 900mV
HSTL
VREF = 750mV
LVEPECL
, VREF = 1082mV
Gate control for "true", Qn, outputs. When G(+)is LOW, the "true" outputs are enabled.
When G(+)is HIGH, the "true" outputs are asynchronously disabled to the level
designated by GL4.
Gate control for "complementary", Qn, outputs. When G(-)is LOW, the "complementary"
outputs are enabled. When G(-)is HIGH, the "complementary" outputs are
asynchronously disabled to the opposite level as GL4.
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary"
outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs
disable HIGH.
Clock outputs
Complementary clock outputs
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential
(LOW) clock input
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID)
or HSTL (LOW) compatible. Used in conjuction with VDDQ to set the interface levels.
Power supply for the device core and inputs
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, VDDQ should be
connected to VDD.
Power supply return for all power
Notes: 1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize
the possibility of runt pulses or be able to tolerate them in down stream circuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PCS2P5T915A
September 2006
rev 0.2
Input/Output Selection1
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
Output
Input
Output
eHSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
HSTL DIF
2.5V LVTTL
1.8V LVTTL
eHSTL
HSTL
Note: 1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a singleended mode require the A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode,
requiring a VREF. Differential (DIF) inputs are used only in differential mode.
DC Electrical Characteristics Over Operating Range
Symbol
Parameter
Test Conditions
VIHH
VIMM
VILL
I3
Input HIGH Voltage Level1
Input MID Voltage Level1
Input LOW Voltage Level1
3-Level Input DC Current (RxS, TxS)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN= VDD
VIN= VDD/2
VIN= GND
HIGH Level
MID Level
LOW Level
Min
VDD - 0.4
VDD/2 - 0.2
Max
Unit
VDD/2 + 0.2
0.4
V
V
V
200
+50
µA
-50
-200
Note: 1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
5 of 23
PCS2P5T915A
September 2006
rev 0.2
DC Electrical Characteristics Over Operating Range for HSTL1
Symbol
Parameter
Test Conditions
Min
Typ7
Max
Unit
Input Characteristics
IIH
Input HIGH Current9
VDD= 2.6V
VI = VDDQ/GND
±5
IIL
Input LOW Current9
VDD= 2.6V
VI = GND/VDDQ
±5
VIK
Clamp Diode Voltage
VIN
DC Input Voltage
-0.3
VDIF
DC Differential Voltage2,8
DC Common Mode Input
3,8
Voltage
DC Input HIGH4,5,8
0.2
VCM
VIH
VIL
VREF
VDD= 2.4V, IIN= - 18mA
-0.7
680
µA
- 1.2
V
+3.6
V
V
750
900
mV
VREF+ 100
DC Input LOW4,6,8
Single-Ended Reference
Voltage4,8
mV
VREF- 100
750
mV
mV
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOH= -8mA
VDDQ- 0.4
V
IOH= -100µA
VDDQ- 0.1
V
IOL= 8mA
IOL= 100µA
0.4
V
0.1
V
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement"
input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input
interface table should be referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Power Supply Characteristics for HSTL Outputs1
Symbol
Parameter
Test Conditions2
Typ
Max
IDDQ
Quiescent VDD Power
Supply Current
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
Unit
20
30
mA
IDDQQ
Quiescent VDDQ Power
Supply Current
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
0.1
0.3
mA
IDDD
Dynamic VDD Power
Supply Current per
Output
VDD= Max., VDDQ= Max., CL= 0pF
20
30
µA/MHz
IDDDQ
Dynamic VDDQ Power
Supply Current per
Output
VDD= Max., VDDQ= Max., CL= 0pF
30
50
µA/MHz
ITOT
Total Power VDD Supply
Current
VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz,CL= 15pF
VDDQ= 1.5V, FREFERENCE CLOCK= 250MHz, CL= 15pF
20
40
35
50
ITOTQ
Total Power VDDQ Supply
Current
VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz, CL= 15pF
VDDQ= 1.5V, FREFERENCE CLOCK= 250MHz, CL= 15pF
35
60
70
120
mA
mA
Note: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
6 of 23
PCS2P5T915A
September 2006
rev 0.2
Differential Input AC Test Conditions for HSTL
Symbol
Parameter
VDIF
VX
VTHI
tR, tF
Value
Units
1
V
1
Input Signal Swing
Differential Input Signal Crossing Point
2
Input Timing Measurement Reference Level3
750
mV
Crossing Point
V
1
V/nS
4
Input Signal Edge Rate
Notes: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
Compliant devices must meet the VDIF (AC) specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices
must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for eHSTL1
Symbol
Parameter
Test Conditions
Min
Typ7
Max
Unit
±5
µA
Input Characteristics
IIH
Input HIGH Current9
9
IIL
Input LOW Current
VIK
Clamp Diode Voltage
VDD= 2.6V
VI = VDDQ/GND
VDD= 2.6V
VI = GND/VDDQ
±5
VDD= 2.4V, IIN = -18mA
- 0.7
VIN
DC Input Voltage
-0.3
VDIF
DC Differential Voltage2,8
DC Common Mode Input
Voltage3,8
DC Input HIGH4,5,8
0.2
VCM
VIH
VIL
VREF
800
- 1.2
+3.6
V
V
900
1000
VREF+ 100
mV
mV
4,6,8
DC Input LOW
Single-Ended Reference
4,8
Voltage
V
VREF- 100
900
mV
mV
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOH= -8mA
VDDQ- 0.4
V
IOH= -100µA
VDDQ- 0.1
V
IOL= 8mA
IOL= 100µA
0.4
V
0.1
V
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement"
input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input
interface table should be referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
7 of 23
PCS2P5T915A
September 2006
rev 0.2
Power Supply Characteristics for eHSTL Outputs1
Symbol Parameter
Test Conditions2
IDDQ
IDDQQ
IDDD
Quiescent VDD Power
Supply Current
Quiescent VDDQ Power
Supply Current
Dynamic VDD Power Supply
Current per Output
Typ
Max
20
30
mA
0.1
0.3
mA
VDD= Max., VDDQ= Max., CL= 0pF
20
30
µA/MHz
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
Unit
VDD= Max., VDDQ= Max., CL= 0pF
40
60
µA/MHz
ITOT
Dynamic VDDQ Power
Supply
Current per Output
Total Power VDD Supply
Current
VDDQ= 1.8V, FREFERENCE
VDDQ= 1.8V, FREFERENCE
CLOCK=
100MHz, CL= 15pF
CLOCK= 250MHz, CL= 15pF
20
35
40
50
mA
ITOTQ
Total Power VDDQ Supply
Current
VDDQ= 1.8V, FREFERENCE
VDDQ= 1.8V, FREFERENCE
CLOCK=
40
80
80
160
IDDDQ
CLOCK=
100MHz, CL= 15pF
250MHz, CL= 15pF
mA
Notes: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for eHSTL
Symbol
Parameter
VDIF
VX
VTHI
tR, tF
Value
1
Input Signal Swing
1
V
900
mV
Crossing Point
V
1
V/nS
Differential Input Signal Crossing Point2
Input Timing Measurement Reference Level3
Units
4
Input Signal Edge Rate
Notes: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant
devices must meet the VDIF (AC) specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices
must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for LVEPECL1
Symbol
Parameter
Test Conditions
Min
Typ2
Max
Unit
Input Characteristics
IIH
Input HIGH Current6
6
VDD= 2.6V
VI = VDDQ/GND
±5
VDD= 2.6V
VI = GND/VDDQ
±5
µA
IIL
Input LOW Current
VIK
Clamp Diode Voltage
VIN
VIH
DC Input Voltage
DC Common Mode Input
Voltage3,5
Single-Ended Reference
4,5
Voltage
DC Input HIGH
1275
1620
mV
VIL
DC Input LOW
555
875
mV
VCM
VREF
VDD= 2.4V, IIN= -18mA
-0.7
- 0.3
915
1082
- 1.2
V
3.6
V
1248
mV
1082
mV
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, A/VREF is tied to the DC Voltage VREF.
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input
interface table should be referenced.
6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
8 of 23
PCS2P5T915A
September 2006
rev 0.2
Differential Input AC Test Conditions for LVEPECL
Symbol
Parameter
VDIF
VX
VTHI
tR, tF
Value
1
Units
Input Signal Swing
732
mV
Differential Input Signal Crossing Point2
1082
mV
Crossing Point
V
1
V/nS
Input Timing Measurement Reference Level3
4
Input Signal Edge Rate
Notes: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
Compliant devices must meet the VDIF (AC) specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant
devices must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for 2.5V LVTTL1
Symbol
Parameter
Test Conditions
Min
Typ8
Max
Unit
Input Characteristics
IIH
Input HIGH Current10
VDD= 2.6V
VI = VDDQ/GND
±5
IIL
Input LOW Current10
VDD= 2.6V
VI = GND/VDDQ
±5
VIK
VIN
DC Input Voltage
Clamp Diode Voltage
VDD= 2.4V, IIN = -18mA
- 0.7
-0.3
µA
- 1.2
V
+3.6
V
0.7
V
V
2
Single-Ended Inputs
VIH
VIL
DC Input HIGH
1.7
DC Input LOW
Differential Inputs
VDIF
VCM
VIH
VIL
VREF
DC Differential Voltage3,9
DC Common Mode Input
4,9
Voltage
DC Input HIGH5,6,9
0.2
1150
V
1250
1350
mV
VREF+ 100
mV
5,7,9
DC Input LOW
Single-Ended Reference
Voltage5,9
VREF- 100
1250
mV
mV
Output Characteristics
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
IOH= -12mA
VDDQ- 0.4
IOH= -100µA
IOL= 12mA
IOL= 100µA
VDDQ- 0.1
V
0.4
0.1
V
V
V
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the
"complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW
input. The AC differential voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input
interface table should be referenced.
10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
9 of 23
PCS2P5T915A
September 2006
rev 0.2
Power Supply Characteristics for 2.5V LVTTL Outputs1
Symbol Parameter
Test Conditions2
IDDQ
IDDQQ
IDDD
IDDDQ
Quiescent VDD Power
Supply Current
Quiescent VDDQ Power
Supply Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power
Supply Current per Output
Typ
Max
20
30
mA
0.1
0.3
mA
VDD= Max., VDDQ= Max., CL= 0pF
25
40
µA/MHz
VDD= Max., VDDQ= Max., CL= 0pF
45
70
µA/MHz
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
ITOT
Total Power VDD Supply
Current
VDDQ= 2.5V., FREFERENCE CLOCK= 100MHz, CL= 15pF
25
40
VDDQ= 2.5V., FREFERENCE
45
70
ITOTQ
Total Power VDDQ Supply
Current
VDDQ= 2.5V., FREFERENCE CLOCK= 100MHz, CL= 15pF
40
80
VDDQ= 2.5V., FREFERENCE
100
200
CLOCK=
200MHz, CL= 15pF
CLOCK= 200MHz, CL= 15pF
Unit
mA
mA
Notes: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 2.5V LVTTL
Symbol
Parameter
VDIF
VX
Value
Units
VDD
V
VDD/2
V
Input Signal Swing1
Differential Input Signal Crossing Point
2
VTHI
Input Timing Measurement Reference Level
tR, tF
Input Signal Edge Rate4
3
Crossing Point
V
2.5
V/nS
Notes: 1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions.
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
Compliant devices must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-ended Input AC Test Conditions for 2.5V LVTTL
Symbol
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VTHI
tR, tF
Input Timing Measurement Reference Level
1
2
Input Signal Edge Rate
Value
Units
VDD
V
0
V
VDD/2
V
2
V/nS
Notes: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE)
environment.
2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
10 of 23
PCS2P5T915A
September 2006
rev 0.2
DC Electrical Characteristics Over Operating Range for 1.8V LVTTL1
Symbol
Parameter
Test Conditions
Min
Typ8
Max
Unit
Input Characteristics
IIH
Input HIGH Current12
VDD= 2.6V
VI = VDDQ/GND
±5
IIL
Input LOW Current12
VDD= 2.6V
VI = GND/VDDQ
±5
VIK
Clamp Diode Voltage
VDD= 2.4V, IIN= -18mA
VIN
DC Input Voltage
-0.7
- 0.3
µA
- 1.2
V
VDDQ+ 0.3
V
Single-Ended Inputs2
VIH
VIL
1.07311
DC Input HIGH
V
11
DC Input LOW
0.683
V
Differential Inputs
VDIF
VCM
VIH
VIL
VREF
DC Differential Voltage3,9
DC Common Mode Input
Voltage4,9
DC Input HIGH5,6,9
0.2
825
V
900
975
mV
VREF+ 100
mV
5,7,9
DC Input LOW
Single-Ended Reference
5,9
Voltage
VREF- 100
900
mV
mV
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOH= -6mA
VDDQ- 0.4
V
IOH= -100µA
VDDQ- 0.1
V
IOL= 6mA
0.4
V
IOL= 100µA
0.1
V
Notes: 1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement"
input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when
VREF is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee
switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate
tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The
correct input interface table should be referenced.
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD
where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the
specification, the translator was designed to accept the calculated worst case value ( VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a
nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD
where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure
compliance with the specification, the translator was designed to accept the calculated worst case value ( VIL = 0.35 • [1.8 + 0.15V])
rather than reference against a nominal 1.8V supply.
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
11 of 23
PCS2P5T915A
September 2006
rev 0.2
Power Supply Characteristics for 1.8V LVTTL Outputs1
Symbol
IDDQ
IDDQQ
IDDD
IDDDQ
Test Conditions2
Parameter
Quiescent VDD Power
Supply Current
Quiescent VDDQ Power
Supply Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power
Supply Current per Output
Typ
Max
20
30
mA
0.1
0.3
mA
VDD= Max., VDDQ= Max., CL= 0pF
20
40
µA/MHz
VDD= Max., VDDQ= Max., CL= 0pF
55
80
µA/MHz
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
ITOT
Total Power VDD Supply
Current
VDDQ= 1.8V., FREFERENCE
CLOCK=
100MHz, CL= 15pF
25
40
VDDQ= 1.8V., FREFERENCE
CLOCK=
200MHz, CL= 15pF
40
60
ITOTQ
Total Power VDDQ Supply
Current
VDDQ= 1.8V., FREFERENCE
VDDQ= 1.8V., FREFERENCE
CLOCK=
100MHz, CL= 15pF
200MHz, CL= 15pF
50
100
120
240
CLOCK=
Unit
mA
mA
Notes: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 1.8V LVTTL
Symbol
VDIF
VX
VTHI
tR, tF
Parameter
Value
1
Input Signal Swing
Differential Input Signal Crossing Point
VDDI
V
VDDI /2
mV
Crossing Point
V
1.8
V/nS
2
Input Timing Measurement Reference Level
3
Units
4
Input Signal Edge Rate
Notes:1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to
allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under
actual use conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant
devices must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-ended Input AC Test Conditions for 1.8V LVTTL
Symbol
Parameter
1
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VTHI
tR, tF
Input Timing Measurement Reference Level
2
3
Input Signal Edge Rate
Value
Units
VDDI
V
0
V
VDDI/2
mV
2
V/nS
Notes: 1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE)
environment.
3. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
12 of 23
PCS2P5T915A
September 2006
rev 0.2
AC Electrical Characteristics Over Operating Range5
Symbo
l
Parameter
Min
Typ
Max
Unit
Skew Parameters
Single-Ended and Differential
Modes
Single-Ended in Differential
Mode (DSE)
Single-Ended and Differential
Modes
2
tSK(INV)
Inverting Skew
Single-Ended in Differential
Mode (DSE)
Single-Ended and Differential
Modes
tSK(P)
Pulse Skew3
Single-Ended in Differential
Mode (DSE)
Single-Ended and Differential
Modes
4
tSK(PP)
Part-to-Part Skew
Single-Ended in Differential
Mode (DSE)
HSTL and eHSTL Differential True and Complementary
VOX
Output Crossing Voltage Level
Propagation Delay
Propagation Delay A to
2.5V / 1.8V LVTTL Outputs
tPLH
Qn/Qn
tPHL
HSTL / eHSTL Outputs
Output Rise Time
2.5V /1.8V LVTTL Outputs
tR
(20% to 80%)
HSTL / eHSTL Outputs
Output Fall Time
2.5V /1.8V LVTTL Outputs
tF
(20% to 80%)
HSTL / eHSTL Outputs
tSK(O)
fO
25
Same Device Output
1
Pin-to-Pin Skew
pS
25
300
pS
300
300
pS
300
300
pS
300
VDDQ/2 - 200
VDDQ/2
VDDQ/2 + 200
2.5
2
350
1050
350
1350
350
1050
350
1350
Frequency Range (HSTL/eHSTL outputs)
250
Frequency Range (2.5V/1.8V LVTTL outputs)
200
mV
nS
pS
pS
MHz
Output Gate Enable/Disable Delay
tPGE
Output Gate Enable to Qn/Qn
tPGD
Output Gate Enable to Qn/Qn Driven to GL Designated
Level
3.5
nS
3
nS
Notes: 1. Skew measured between all outputs or output pairs under identical input and output interfaces, transitions and load conditions on any one device. For
single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. For differential LVTTL
outputs, the true outputs are compared only with other true outputs and the complementary outputs are compared only with other complementary
outputs. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals.
2. For operating with either 1.8V or 2.5V LVTTL output interfaces with both true and complementary outputs enabled. Inverting skew is the skew between
true and complementary outputs switching in opposite directions under identical input and output interfaces, transitions and load conditions on any one
device.
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any output or output pair under identical input and output interfaces,
transitions and load conditions on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output
voltage passes through VDDQ/2. The measurement applies to both true and complementary signals. For differential HSTL outputs, the measurement
takes place at the crossing point of the true and complementary signals.
4. Skew measured is the magnitude of the difference in propagation times between any outputs or output pairs of two devices, given identical transitions
and load conditions at identical VDD/VDDQ levels and temperature.
5. Guaranteed by design.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
13 of 23
PCS2P5T915A
September 2006
rev 0.2
AC Differential Input Specifications1
Symbol
Parameter
Min
2
tW
Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)
Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL
2
outputs)
Typ
Max
Unit
1.73
nS
2.17
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF
VIH
VIL
AC Differential Voltage3
4,5
AC Input HIGH
400
mV
Vx + 200
mV
4,6
AC Input LOW
Vx - 200
mV
LVEPECL
VDIF
AC Differential Voltage3
4
VIH
AC Input HIGH
VIL
4
400
mV
1275
mV
AC Input LOW
875
mV
Notes: 1. For differential input mode, RxS is tied to GND.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and
the voltage range defined by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the
"complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range.
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
14 of 23
PCS2P5T915A
September 2006
rev 0.2
Differential AC Timing Waveforms
1/fo
tw
tw
VIH
A
VTHI
VIL
VIH
A
VTHI
tPLH
VIL
tPHL
Qn
VOH
VOX
VOL
Qn
tSK(O)
Qm
tSK(O)
VOH
VOX
VOL
Qm
HSTL and eHSTL Output Propagation and Skew Waveforms
1/fo
tw
tw
VIH
A
VTHI
VIL
VIH
A
VTHI
tPLH
tPHL
VIL
Qn
VOH
VTHO
VOL
comp tPLH
comp tPHL
VOH
VTHO
Qn
VOL
tSK(O)
tSK(O)
Qm
tSK(O)
VOH
VTHO
VOL
tSK(O)
VOH
Qm
VTHO
VOL
1.8V or 2.5V LVTTL Output Propagation and Skew Waveforms
Notes: 1. For the HSTL and eHSTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the crossing point of each
Qn and Qn.
2. For 1.8V and 2.5V LVTTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the slower of Qn or Qn
passing through VTHO.
3. Pulse skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
where tPHL and tPLH are measured on the controlled edges of any one output from the rising and falling edges of a single pulse. Note that the tPHL and
tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
15 of 23
PCS2P5T915A
September 2006
rev 0.2
VIH
VTHI
A
VIL
VIH
VTHI
A
VIL
VIH
GL
VTHI
VIL
tPLH
VIH
VTHI
G(+)
VIL
tPGD
tPGE
Qn
VOH
VTHO
VOL
Qn
Differential Gate Disable/Enable Showing Runt Pulse Generation
Notes: 1. The waveforms shown only gate "true" output, Qn.
2. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to
avoid this problem.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
16 of 23
PCS2P5T915A
September 2006
rev 0.2
SDR AC TIMING WAVEFORMS
1/fo
tw
tw
VIH
A
VTHI
VIL
VIH
A
VTHI
tPLH
VIL
tPHL
VOH
VTHO
Qn
VOL
tSK(O)
tSK(O)
VOH
Qm
VTHO
VOL
Propagation and Skew Waveforms
Notes: 1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO.
2. Pulse Skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the
and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
tPHL
17 of 23
PCS2P5T915A
September 2006
rev 0.2
VIH
VTHI
A
VIL
VIH
VTHI
A
VIL
VIH
GL
VTHI
VIL
tPLH
VIH
VTHI
Gx
VIL
tPGD
tPGE
VOH
VTHO
Qn
VOL
SDR Gate Disable/Enable Showing Runt Pulse Generation
Note: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this
problem.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
18 of 23
PCS2P5T915A
September 2006
rev 0.2
Test Circuits and Conditions
VDDI
VIN
3 inch, -50Ω
Transmission Line
R1
VDD
VDDQ
R2
A
D.U.T.
VDDI
Pulse
Generator
VIN
3 inch, -50Ω
Transmission Line
R1
A
R2
Test Circuit for Differential Input1
Differential Input Test Conditions
Symbol
VDD= 2.5V ± 0.1V
Unit
R1
100
Ω
R2
100
Ω
VDDI
VCM*2
V
HSTL: Crossing of A and A
eHSTL: Crossing of A and A
VTHI
LVEPECL: Crossing of A and A
V
1.8V LVTTL: VDDI/2
2.5V LVTTL: VDD/2
Note: 1. This input configuration is used for all input interfaces. For single-ended testing, the VIN input is tied to GND. For testing single-ended in differential input
mode, the VIN is left floating.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
19 of 23
PCS2P5T915A
September 2006
rev 0.2
VDDQ
R1
VDDQ
VDD
VDD
VDDQ
D.U.T.
VDDQ
R2
CL
R1
Qn
Qn
R2
CL
D.U.T.
VDDQ
Qn
R1
CL
R2
Test Circuit for SDR Outputs
Test Circuit for Differential Outputs
SDR Output Test Conditions
Differential Output Test Contions
Symbol
VDD= 2.5V ± 0.1V
VDDQ= Interface
Specified
Unit
CL
R1
R2
15
100
100
pF
Ω
Ω
VTHO
VDDQ/ 2
V
Symbol
CL
R1
R2
VOX
VTHO
VDD= 2.5V ± 0.1V
VDDQ= Interface Specified
15
100
100
HSTL: Crossing of Qn and Qn
eHSTL: Crossing of Qn and Qn
1.8V LVTTL: VDDQ/2
2.5V LVTTL: VDDQ/2
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
Unit
pF
Ω
Ω
V
V
20 of 23
PCS2P5T915A
September 2006
rev 0.2
Package Information
Package (6.10 mm Body, JEDEC MO-153-ED)
Dimensions
Symbol
Inches
Millimeters
Min
Max
Min
Max
A
....
0.047
…
1.20
A1
0.002
0.006
0.05
0.15
A2
0.031
0.041
0.8
1.05
b
0.008 BSC
0.20 BSC
c
0.004
0.008
0.09
0.20
D
0.488
0.496
12.40
12.60
E1
0.236
0.244
6.00
6.20
E
0.319 BSC
8.10 BSC
e
0.020 BSC
0.50 BSC
L
0.018
0.030
N
α
0.45
0.75
0°
8°
48
0°
8°
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
21 of 23
PCS2P5T915A
September 2006
rev 0.2
Ordering Information
Part Number
Marking
Package Type
Temperature
PCS2P5T915AG
2P5T915AG
48 pin TSSOP Package
Commercial
PCS2I5T915AG
2I5T915AG
48 pin TSSOP Package
Industrial
Device Ordering Information
P C S 2 P 5 T 9 1 5 A G - 4 8 - T T
R = Tape & Reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent Nos 5,488,627 and 5,631,920.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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PCS2P5T915A
September 2006
rev 0.2
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Preliminary Information
Part Number: PCS2P5T915A
Document Version: v0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct
this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from
PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale.
The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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