LVDS, 1:4 Clock Buffer Terabuffer™ IDT5T9304 DATA SHEET General Description Features The IDT5T9304 differential clock buffer has a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9304 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. • • • • • • • Guaranteed low skew: 50ps (maximum) • • • • Selectable differential inputs to four LVDS outputs The IDT5T9304 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. Very low duty cycle distortion: 125ps (maximum) Propagation delay: 1.75ns (maximum) Up to 450MHz operation Selectable inputs Hot insertable and over-voltage tolerant inputs 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface 2.5V VDD 0°C to 70°C ambient operating temperature Available in standard (RoHS 5) and lead-free (RoHS 6) packages Applications • Clock distribution Pin Assignment GND PD RESERVED VDD Q1 Q1 Q2 Q2 VDD SEL G GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 A2 A2 GND VDD Q3 Q3 Q4 Q4 VDD GL A1 A1 IDT5T9304 24-Lead TSSOP 4.4mm x 7.8mm x 1.0mm package body G Package Top View IDT5T9304 REVISION A JANUARY 21, 2010 1 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Block Diagram GL G PD A1 A2 Q1 OUTPUT CONTROL Q2 OUTPUT CONTROL Q3 OUTPUT CONTROL Q4 Q1 Q2 1 A1 A2 OUTPUT CONTROL 0 Q3 Q4 SEL IDT5T9304 REVISION A JANUARY 21, 2010 2 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Table 1. Pin Descriptions Number Name Type 1, 12, 22 GND 2 PD Input 3 RESERVED Reserved 4, 9, 16, 21 VDD 5, 7, 18, 20 Q1, Q2, Q4, Q3 6, 8, 17, 19 Description Power Power supply return for all power. LVTTL Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both Qx and Qx outputs will pull to VDD. Set HIGH for normal operation.(3) Reserved pin. Power Power supply for the device core and inputs. Output LVDS Complementary differential clock outputs. Q1, Q2, Q4, Q3 Output LVDS Differential clock outputs. 10 SEL Input LVTTL Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1. 11 G Input LVTTL Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When G is LOW, the differential outputs are active. When G is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). 13, 24 A1, A2 Input Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input. 14, 23 A1, A2 Input Adjustable (1, 4) Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage for A[1:2]: 3.3V LVTTL VREF = 1650mV 2.5V LVTTL VREF = 1250mV 15 GL Input LVTTL Specifies output disable level. If HIGH, Qx outputs disable HIGH and Qx outputs disable LOW. If LOW, Qx outputs disable LOW and Qx outputs disable HIGH. NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V and 2.5V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL (2.5V) and LVPECL (3.3V) levels Differential LVDS levels Differential CML levels 2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting PD. 4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal. Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)) Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 3 Maximum Units pF NOTE: This parameter is measured at characterization but not tested. IDT5T9304 REVISION A JANUARY 21, 2010 3 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Function Tables Table 3A. Gate Control Output Table Control Output Outputs GL G Q[1:4] Q[1:4] 0 0 Toggling Toggling 0 1 LOW HIGH 1 0 Toggling Toggling 1 1 HIGH LOW Table 3B. Input Selection Table Selection SEL pin Inputs 0 A2, A2 1 A1, A1 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Power Supply Voltage, VDD -0.5V to +3.6V Input Voltage, VI -0.5V to +3.6V Output Voltage, VO Not to exceed 3.6V -0.5 to VDD +0.5V Storage Temperature, TSTG -65°C to 150°C Junction Temperature, TJ 150°C Recommended Operating Range Symbol TA VDD Description Ambient Operating Temperature Internal Power Supply Voltage IDT5T9304 REVISION A JANUARY 21, 2010 4 Minimum Typical Maximum Units 0 25 70 °C 2.3 2.5 2.7 V ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol Parameter Test Conditions IDDQ Quiescent VDD Power Supply Current ITOT Total Power VDD Supply Current IPD Total Power Down Supply Current Minimum Typical(2) Maximum Units VDD = Max., All Input Clocks = LOW(2); Output enabled 240 mA VDD = 2.7V; FREFERENCE Clock = 450MHz 250 mA PD = LOW 5 mA NOTE 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions. NOTE 2. The true input is held LOW and the complementary input is held HIGH. Table 4B. LVCMOS/LVTTL DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum IIH Input High Current IIL Input Low Current VIK Clamp Diode Voltage VIN DC Input Voltage -0.3 VIH DC Input High Voltage 1.7 VIL DC Input Low Voltage VTHI DC Input Threshold Crossing Voltage VREF Single-Ended Reference Voltage (3) Typical(2) Maximum Units VDD = 2.7V ±5 µA VDD = 2.7V ±5 µA -1.2 V 3.6 V VDD = 2.3V, IIN = -18mA -0.7 V 0.7 V VDD/2 V 3.3V LVTTL 1.65 V 2.5V LVTTL 1.25 V NOTE 1. See Recommended Operating Range table. NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient. NOTE 3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage. Table 4C. Differential DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol Parameter IIH Input High Current IIL Input Low Current VIK Clamp Diode Voltage VIN DC Input Voltage VDIF VCM DC Differential Voltage Units VDD = 2.7V ±5 µA VDD = 2.7V ±5 µA -1.2 V 3.6 V Minimum VDD = 2.3V, IIN = -18mA -0.7 -0.3 (3) DC Common Mode Input Typical(2) Maximum Test Conditions 0.1 Voltage(4) 0.05 V VDD V NOTE 1. See Recommended Operating Range table. NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient. NOTE 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. NOTE 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. IDT5T9304 REVISION A JANUARY 21, 2010 5 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Table 4D. LVDS DC Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol Parameter Test Conditions VOT(+) Differential Output Voltage for the True Binary State VOT(–) Differential Output Voltage for the False Binary State ∆VOT Change in VOT Between Complementary Output States VOS Output Common Mode Voltage (Offset Voltage) ∆VOS Change in VOS Between Complementary Output States IOS Outputs Short Circuit Current IOSD Differential Outputs Short Circuit Current Typical(2) Maximum Units 247 454 mV 247 454 mV 50 mV 1.375 V 50 mV Minimum 1.125 1.2 VOUT+ and VOUT– = 0V 12 24 mA VOUT+ = VOUT– 6 12 mA NOTE 1. See Recommended Operating Range table. NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient. AC Electrical Characteristics Table 5A. HSTL Differential Input AC Characteristics, VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol VDIF Parameter Input Signal Swing(1) VX Differential Input Signal Crossing DH Duty Cycle VTHI tR / tF Point(2) Input Timing Measurement Reference Input Signal Edge Level(3) Rate(4) Value Units 1 V 750 mV 50 % Crossing Point V 2 V/ns NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. Table 5B. eHSTL AC Differential Input Characteristics, VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol VDIF Parameter Input Signal Swing(1) VX Differential Input Signal Crossing DH Duty Cycle VTHI tR / tF Point(2) Input Timing Measurement Reference Input Signal Edge Level(3) Rate(4) Value Units 1 V 900 mV 50 % Crossing Point V 2 V/ns NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. IDT5T9304 REVISION A JANUARY 21, 2010 6 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol Parameter VDIF Input Signal Swing VX Differential Input Cross Point Voltage(2) DH Duty Cycle VTHI tR / tF Maximum Units 732 mV LVEPECL 1082 mV LVPECL 1880 mV 50 % Crossing Point V 2 V/ns (1) (3) Input Timing Measurement Reference Level (4) Input Signal Edge Rate NOTE 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. Table 5D. LVDS Differential Input AC Characteristics, TA = 0°C to 70°C Symbol VDIF Parameter Input Signal Swing(1) VX Differential Input Cross Point DH Duty Cycle VTHI tR / tF Voltage(2) Input Timing Measurement Reference Input Signal Edge Level(3) Rate(4) Maximum Units 400 mV 1.2 V 50 % Crossing Point V 2 V/ns NOTE 1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. Table 5E. AC Differential Input Characteristics(1), VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol Parameter Minimum Voltage(2) VDIF AC Differential VX Differential Input Cross Point Voltage VCM Common Mode Input Voltage VIN Input Voltage Range(3) Typical Maximum Units 0.1 3.6 V 0.05 VDD V 0.05 VDD V -0.3 3.6 V NOTE 1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been met or exceeded. NOTE 2. VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the “complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state. NOTE 3. VCM specified the maximum allowable range of (VTR + VCP) /2. IDT5T9304 REVISION A JANUARY 21, 2010 7 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Table 5F. AC Characteristics(1,5), VDD = 2.5V±0.2V, TA = 0°C to 70°C Symbol tsk(o) tsk(p) Parameter Test Conditions Same Device Output Pin-to-Pin Skew Pulse Minimum Typical Maximum Units 50 ps 125 ps 300 ps 1.25 1.75 ns 1.25 1.75 ns 450 MHz (2) Skew(3) (4) tsk(pp) Part-to-Part Skew tpLH Propagation Delay, Low-to-High tpHL Propagation Delay, High-to-Low A Crosspoint to Qn, Qn Crosspoint (6) fo Frequency Range tPGE Output Gate Enable Crossing VTHI-to-Qn/Qn Crosspoint 3.5 ns tPGD Output Gate Enable Crossing VTHI-to-Qn/Qn Crosspoint Driven to Designated Level 3.5 ns tPWRDN PD Crossing VTHI-to-Qn = VDD, Qn = VDD 100 µS tPWRUP Output Gate Disable Crossing VTHI to Qn/Qn Driven to Designated Level 100 µS tR / tF Output Rise/Fall Time(6) 600 ps 20% to 80% 125 NOTE. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup. NOTE 2. Skew measured between Crosspoint of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device. NOTE 3. Skew measured is the difference between propagation delay times tpHL and tpLH of any differential output pair under identical input and output interfaces, transitions and load conditions on any one device. NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions at identical VDD levels and temperature. NOTE 5. All parameters are tested with a 50% input duty cycle. NOTE 6. Guaranteed by design but not production tested. IDT5T9304 REVISION A JANUARY 21, 2010 8 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Differential AC Timing Waveforms Output Propagation and Skew Waveforms 1/fo + VDIF VDIF = 0 - VDIF A[1:2] - A[1:2] tPHL tPLH + VDIF VDIF = 0 - VDIF Qn - Qn tSK(O) tSK(O) + VDIF VDIF = 0 - VDIF Qm - Qm NOTE 1: Pulse skew is calculated using the following expression: tsk(p) = |tpHL – tpLH| Note that the tpHL and tpLH shown above ae not valid measurements for this calculation because they are not taken from the same pulse. NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup. Differential Gate Disabled/Endable Showing Runt Pulse Generation + VDIF VDIF = 0 - VDIF A[1:2] - A[1:2] VIH VTHI VIL GL tPLH VIH VTHI VIL G tPGE tPGD + VDIF VDIF = 0 - VDIF Qn - Qn NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the G signal to avoid this problem. IDT5T9304 REVISION A JANUARY 21, 2010 9 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Power Down Timing A1 - A1 +VDIF VDIF=0 -VDIF A2 - A2 +VDIF VDIF=0 -VDIF G VIH VTHI VIL PD VIH VTHI VIL +VDIF VDIF=0 -VDIF Qn - Qn NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting PD. NOTE 2: The Power Down Timing diagram assumes that GL is HIGH. NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is shown when Qn/Qn goes to VDIF = 0. IDT5T9304 REVISION A JANUARY 21, 2010 10 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Test Circuit for Differential Input VIN ~50Ω Transmission Line VDD/2 A D.U.T. Pulse Generator VIN ~50Ω Transmission Line A -VDD/2 Scope 50Ω 50Ω Table 6A. Differential Input Test Conditions Symbol VDD = 2.5V ± 0.2V Unit VTHI Crossing of A and A V IDT5T9304 REVISION A JANUARY 21, 2010 11 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Test Circuit for DC Outputs and Power Down Tests VDD Pulse Generator A Qn RL A D.U.T. VOS VOD RL Qn Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing VDD/2 SCOPE CL Z = 50Ω Pulse Generator A Qn 50Ω A D.U.T. 50Ω Qn Z = 50Ω CL -VDD/2 Table 6B. Differential Input Test Conditions Symbol CL RL VDD = 2.5V ± 0.2V Unit 0(1) pF 8(1,2) pF 50 Ω NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only. NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load. IDT5T9304 REVISION A JANUARY 21, 2010 12 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP Table 7. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT5T9304 REVISION A JANUARY 21, 2010 13 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Ordering Information Table 8. Ordering Information IDT XXXXX Device Type XX Package X Process 0 C to +70 C (Commercial) PG PGG Thin Shrink Small Outline Package TSSOP - Green 5T9304 2.5V LVDS 1:4 Glitchless Clock Buffer Terabuffer II While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT5T9304 REVISION A JANUARY 21, 2010 14 ©2010 Integrated Device Technology, Inc. IDT5T9304 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 2.5V LVDS, 1:4 CLOCK BUFFER TERABUFFER™ Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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