QIMONDA HYB18L256169BF

December 2006
HYB18L256169BF-7.5
HYE18L256169BF-7.5
DRAMs for Mobile Applications
256-Mbit Mobile-RAM
Mobile-RAM
RoHS Compliant Product
Data S heet
Rev. 1.02
Data Sheet,
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
HYB18L256169BF-7.5, HYE18L256169BF-7.5
Revision History: 2006-12, Rev.1.02
Page
Subjects (major changes since last revision)
All
Qimonda update
Previous Version: 2005-05, Rev. 1.01
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
02032006-MP0M-7FQG
2
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
4 banks × 4 Mbit × 16 organization
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Programmable CAS latency: 2, 3
Programmable burst length: 1, 2, 4, 8 or full page
Programmable wrap sequence: sequential or interleaved
Programmable drive strength
Auto refresh and self refresh modes
8192 refresh cycles / 64 ms
Auto precharge
Commercial (0°C to +70°C) and Extended (-25°C to +85°C) operating temperature range
54-ball PG-VFBGA package (11.0 × 8.0 × 1.0 mm)
RoHS Compliant Product1)
Power Saving Features
•
•
•
•
•
Low supply voltages: VDD = 1.70V to 1.95V, VDDQ = 1.70V to 1.95V
Optimized self refresh (IDD6) and standby currents (IDD2/IDD3)
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Power-Down and Deep Power Down modes
Table 1
Performance
Part Number Speed Code
- 7.5
Unit
Speed Grade
133
MHz
CL = 3
5.4
ns
CL = 2
6.0
ns
CL = 3
7.5
ns
CL = 2
9.5
ns
Access Time (tACmax)
Clock Cycle Time (tCKmin)
Table 2
Memory Addressing Scheme
Item
Addresses
Banks
BA0, BA1
Rows
A0 - A12
Columns
A0 - A8
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council
of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated
biphenyls and polybrominated biphenyl ethers.
Data Sheet
3
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Overview
Table 3
Type
Ordering Information
1)
Package
Description
Commercial Temperature Range
HYB18L256169BF-7.5
133 MHz 4 Banks × 4 Mbit × 16 LP-SDRAM
PG-VFBGA-54-8
Extended Temperature Range
HYE18L256169BF-7.5
133 MHz 4 Banks × 4 Mbit × 16 LP-SDRAM
PG-VFBGA-54-8
1) HY[B/E]: Designator for memory products (HYB: standard temp. range); (HYE: extended temp. range)
18L: 1.8V Mobile-RAM
256: 256 MBit density
160: 16 bit interface width
B: die revision
F: green product
-7.5: speed grade(s): min. clock cycle time
1.2
Pin Configuration
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Figure 1
Data Sheet
Standard Ballout 256-Mbit Mobile-RAM
4
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Overview
1.3
Description
The HY[B/E]18L256169BF is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
The HY[B/E]18L256169BF achieves high speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are
burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4,
8 or full page) in a programmed sequence.
The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.
The HY[B/E]18L256169BF is especially designed for mobile applications. It operates from a 1.8V power supply.
Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can
further be reduced by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep PowerDown (DPD) mode.
The HY[B/E]18L256169BF is housed in a 54-ball PG-VFBGA package. It is available in Commercial (0 °C to
70 °C) and Extended (-25 °C to 85 °C) temperature range.
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5
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Overview
1.4
Pin Definition and Description
Table 4
Pin Description
Ball
Type
Detailed Function
CLK
Input
Clock: all inputs are sampled on the positive edge of CLK.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWERDOWN (row active in any bank) or SUSPEND (access in progress). Input buffers,
excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE
are disabled during SELF REFRESH.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple memory banks. CS is considered part of
the command code.
RAS, CAS,
WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
DQ0 - DQ15
I/O
Data Inputs/Output: Bi-directional data bus (16 bit)
LDQM,
UDQM
Input
Input/Output Mask: input mask signal for WRITE cycles and output enable for READ
cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as
an output enable and places the output buffers in High-Z state when HIGH (two clocks
latency).
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE
or PRECHARGE command is being applied. BA0, BA1 also determine which mode
register is to be loaded during a MODE REGISTER SET command (MRS or EMRS).
A0 - A12
Input
Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0
- A8 define the column address during a READ or WRITE command cycle. In addition,
A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle.
During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls
which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged
regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be
precharged. During MODE REGISTER SET commands, the address inputs hold the opcode to be loaded.
VDDQ
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:
VDDQ = 1.70V to 1.95V
VSSQ
VDD
VSS
Supply I/O Ground
N.C.
–
Data Sheet
Supply Power Supply: Power for the core logic and input buffers, VDD = 1.70V to 1.95V
Supply Ground
No Connect
6
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2
Functional Description
The 256-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
2.1
Power On and Initialization
The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational
procedures other than those specified may result in undefined operation.
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Figure 3
Data Sheet
Power-Up Sequence and Mode Register Sets
7
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD
and VDDQ are driven from a single power converter output.
Assert and hold CKE and DQM to a HIGH level.
2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks.
3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period.
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRC
period.
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode
Register, each followed by NOP or DESELECT commands for at least tMRD period; the order in which both
registers are programmed is not important. Programming of the Extended Mode Register may be omitted when
default values (half drive strength, 4 bank refresh) will be used.
Following these steps, the Mobile-RAM is ready for normal operation.
2.2
Register Definition
2.2.1
Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
MR
Mode Register Definition
(BA[1:0] = 00B)
BA1
BA0
A12
A11
A10
A9
A8
A7
0
0
0
0
0
WB
0
0
Field
Bits
Type
Description
WB
9
w
Write Burst Mode
0
Burst Write
1
Single Write
CL
[6:4]
w
CAS Latency
010 2
011 3
A6
A5
CL
A4
A3
BT
A2
A1
A0
BL
Note: All other bit combinations are RESERVED.
BT
3
Data Sheet
w
Burst Type
0
Sequential
1
Interleaved
8
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
000 1
001 2
010 4
011 8
111 full page (Sequential burst type only)
Note: All other bit combinations are RESERVED.
2.2.1.1
Burst Length
READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst
types, and a full-page burst mode is available for the sequential burst type.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary
is reached. The block is uniquely selected by A1-A8 when the burst length is set to two, by A2-A8 when the burst
length is set to four and by A3-A8 when the burst length is set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within the block.
Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not selfterminate; this implies that full-page read or write bursts with Auto Precharge are not legal commands.
Table 5
Burst Definition
Burst Length
Starting Column Address
A2
A1
A0
Sequential
Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
2
4
8
Full Page
Order of Accesses Within a Burst
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
n
n
n
Cn, Cn+1, Cn+2, …
not supported
Notes
1.
2.
3.
4.
For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block.
For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block.
For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block.
For a full page burst, A0-Ai select the starting data element.
Data Sheet
9
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the
block.
2.2.1.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 5.
2.2.1.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock
edge n + m (for details please refer to the READ command description).
2.2.1.4
Write Burst Mode
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.
2.2.1.5
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive
strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified
time before initiating any subsequent operation. Violating either of these requirements result in unspecified
operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
EMR
Extended Mode Register
(BA[1:0] = 10B)
BA1
BA0
A12
A11
A10
A9
A8
A7
1
0
0
0
0
0
0
0
Field
Bits
Type
Description
DS
[6:5]
w
Selectable Drive Strength
00 Full Drive Strength
01 Half Drive Strength (default)
A6
A5
DS
A4
A3
(TCSR)
A2
A1
A0
PASR
Note: All other bit combinations are RESERVED.
TCSR [4:3]
Data Sheet
w
Temperature Compensated Self Refresh
XX Superseded by on-chip temperature sensor (see text)
10
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Field
Bits
PASR [2:0]
Type
Description
w
Partial Array Self Refresh
000 all banks (default)
001 1/2 array (BA1 = 0)
010 1/4 array (BA1 = BA0 = 0)
101 1/8 array (BA1 = BA0 = RA12 = 0)
110 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
Note: All other bit combinations are RESERVED.
2.2.1.6
Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be
restricted to variable portions of the total array. The selection comprises all four banks, two banks, one bank, half
of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a
period defined by tREF (cf. Table 13).
2.2.1.7
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature
Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain
the stored information. This refresh requirement heavily depends on the die temperature: high temperatures
correspond to short refresh periods, and low temperatures correspond to long refresh periods.
The Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die
temperature and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the
TCSR bits in the Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and
power-saving, because
•
•
•
it is fully compatible to all processors that do not support the Extended Mode Register
it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the
lack of an external temperature sensor
it does not require any processor interaction for regular TCSR updates
2.2.1.8
Selectable Drive Strength
The drive strength of the DQ output buffers is selectable via bits A5 and A6 and shall be set load dependent. The
half drive strength is suitable for typical Mobile-RAM applications.
Data Sheet
11
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.3
State Diagram
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Data Sheet
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State Diagram
12
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4
Commands
Table 6
Command Overview
Command
CS RAS CAS WE DQM
Address
Notes
DESELECT
H
X
X
X
X
X
1)
NO OPERATION
L
H
H
H
X
X
1)
ACT
ACTIVE (Select bank and row)
L
L
H
H
X
Bank / Row
2)
RD
READ (Select bank and column and start read burst)
L
H
L
H
L/H
Bank / Col
3)
WR
WRITE (Select bank and column and start write burst)
L
H
L
L
L/H
Bank / Col
3)
BST
BURST TERMINATE or
DEEP POWER DOWN
L
H
H
L
X
X
4)
PRE
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
5)
ARF
AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
L
L
L
H
X
X
6)7)
MRS
MODE REGISTER SET
L
L
L
L
X
Op-Code
8)
–
Data Write / Output Enable
–
–
–
–
L
–
9)
–
Write Mask / Output Disable (High-Z)
–
–
–
–
H
–
9)
NOP
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A12 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non
persistent), A10 LOW disables the Auto Precharge feature.
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
5) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK. Figure 5 shows the basic timing parameters, which apply to all
commands and operations.
T#+
T#(
T#,
#,+
T)3 T)(
)NPUT
6ALID
6ALID
6ALID
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!
!
"
!"!
#3
#
+
%2
!
3#
!
37
%
Figure 5
Data Sheet
Address / Command Inputs Timing Parameters
13
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Table 7
Inputs Timing Parameters
Parameter
Symbol
Clock cycle time
CL = 3
tCK
CL = 2
Clock frequency
CL = 3
fCK
CL = 2
Clock high-level width
Clock low-level width
Address and command input setup time
Address and command input hold time
2.4.1
tCH
tCL
tIS
tIH
- 7.5
Unit
Notes
—
min.
max.
7.5
—
ns
9.5
—
ns
—
133
MHz
—
105
MHz
2.5
—
ns
—
2.5
—
ns
—
1.5
—
ns
—
0.5
—
ns
—
—
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to a Mobile-RAM which is selected (CS
= LOW). This prevents unwanted commands from
being registered during idle states. Operations already
in progress are not affected.
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 6
No Operation Command
2.4.2
DESELECT
The DESELECT function (CS = HIGH) prevents new commands from being executed by the Mobile-RAM. The
Mobile-RAM is effectively deselected. Operations already in progress are not affected.
Data Sheet
14
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.3
MODE REGISTER SET
The Mode Register and Extended Mode Register are
loaded via inputs A0 - A12 (see mode register
descriptions in Chapter 2.2). The MODE REGISTER
SET command can only be issued when all banks are
idle and no bursts are in progress. A subsequent
executable command cannot be issued until tMRD is
met.
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
#ODE
"!
"
!
#ODE
$O
NgT#A
R E
Figure 7
Mode Register Set Command
#,+
#OM
MA
ND
-23
./0
6ALID
T-2$ !DDRE
SS
#ODE
6ALID
$O
NgT#A
RE
#ODE
-OD
E2E
GIS TER%X TEN
DED-OD
E2E
GIS TERSE
LE
CTIO
N
"!
"!
ANDOPCO
DE!
!
Figure 8
Mode Register Definition
Table 8
Timing Parameters for Mode Register Set Command
Parameter
MODE REGISTER SET command period
Data Sheet
Symbol
tMRD
15
- 7.5
min.
max.
2
–
Units
Notes
tCK
–
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.4
ACTIVE
Before any READ or WRITE commands can be issued
to a bank within the Mobile-RAM, a row in that bank
must be “opened” (activated). This is accomplished via
the ACTIVE command and addresses A0 - A12, BA0
and BA1 (see Figure 9), which decode and select both
the bank and the row to be activated. After opening a
row (issuing an ACTIVE command), a READ or WRITE
command may be issued to that row, subject to the tRCD
specification. A subsequent ACTIVE command to a
different row in the same bank can only be issued after
the previous active row has been “closed”
(precharged).
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
"!
"
!
Figure 9
$O
NgT#
AR E
The minimum time interval between successive
ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE
commands to different banks is defined by tRRD.
2!
"!"
AN
K!D
DRES S 2!
2
O
W!
DD
RES S "!
ACTIVE Command
#,+
#OM
MA
ND
!#4
!!
2/7
2/7
#/,
"!"!
"!X
"!Y
"!Y
./0
!#4
./0
T22$ ./0
2$7
2
./0
T2#$ $O
NgT#A
R E
Figure 10
Bank Activate Timings
Table 9
Timing Parameters for ACTIVE Command
Parameter
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
Symbol
tRC
tRCD
tRRD
- 7.5
Units
Notes
min.
max.
67
–
ns
1)
19
–
ns
1)
15
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Data Sheet
16
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.5
READ
Subsequent to programming the mode register with
CAS latency and burst length, READ bursts are
initiated with a READ command, as shown in
Figure 11. Basic timings for the DQs are shown in
Figure 12; they apply to all read operations and
therefore are omitted from all subsequent timing
diagrams.
#,+
#+%
(IG
H #3
The starting column and bank addresses are provided
with the READ command and Auto Precharge is either
enabled or disabled for that burst access. If Auto
Precharge is enabled, the row being accessed starts
precharge at the completion of the burst, provided tRAS
has been satisfied. For the generic READ commands
used in the following illustrations, Auto Precharge is
disabled.
2!3
#!3
7%
! !
#!
%NAB
LE!
0
!
"!
"
!
Figure 11
$ISA
BLE!0
"!"
AN
K!D
DRES S #!
#
O
LUMN
!
DD
RES S
!0!
UTO0
RE
CH
AR GE
"!
$O
NgT#
AR E
!0
READ Command
#,+
T$1:
$1 T!#
T!#
T,:
T/(
$1
$/N
T(:
T/(
$/N
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NgT#A
RE
Figure 12
Data Sheet
Basic READ Timing Parameters for DQs
17
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Table 10
Timing Parameters for READ
Parameter
Symbol
Access time from CLK
CL = 3
CL = 2
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
- 7.5
tAC
tAC
tLZ
tHZ
tOH
tDQZ
tRC
tRCD
tRAS
tRP
Units
Notes
–
min.
max.
–
5.4
ns
–
6.0
ns
1.0
–
ns
3.0
7.0
ns
2.5
–
ns
–
2
tCK
–
–
–
67
–
ns
1)
19
–
ns
1)
45
100k
ns
1)
19
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
#,+
T2#$ T2!3 #OMM
AND
!#4
./0
2%!$
!DD
RESS "A!
2OWX "A!
#OLN
!!0 2OWX $IS!
0
T20
T2#
./0
./0
./0
02%
./0
!#4
"A!
2OWB
0RE
!LL
!0
2OWB
0RE"
ANK!
#,
$1
$/N
$/N
$/N
$/N
"A!#O
LNBANK !C OLU
MNN
!0!UTO0R EC HA
RG
E
$/N$A
TA/UTFROM
COLU
M
NN
$IS !0
$ISA
BLE
!U
TO0REC HAR GE
"URST,ENG
THIN
THECAS ESHOW
N
SU
BSE
QUEN
TELE
ME
NTS OF$A
TA/
UTAREP
ROVID
ED
IN
THEPROGR AMME
DORDER FOLLO
WING
$/
N
Figure 13
Data Sheet
$O
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RE
Single READ Burst (CAS Latency = 2)
18
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
#,+
T2#$ T2!3 #OMM
AND
!#4
./0
./0
2%!
$
!DD
RESS "A!
2OW
X "A!
#OLN !!0 2OW
X $IS !
0
T20
T2#
./0
./0
./0
02%
./0
./0
!#4
"A!
2OW
B 0RE!LL
!0
2OW
B 0RE"
ANK!
#,
$1
$/N
$/N
$/N
$/N
$O
NgT#A
RE
"A!#O
LNBANK !C OLU
MNN
!0!UTO0R ECHA
RGE
$/N$A
TA/UTFROM
COLU
M
NN
$IS !0$IS ABLE
!UTO0REC HARGE
"URST,ENG
THIN
THECAS ESHOW
N
SU
BSE
QUEN
TELE
ME
NTS OF$A
TA/
UTAREP
ROVID
ED
IN
THEPROGR AMME
DORDER FOLLO
WING
$/
N
Figure 14
Single READ Burst (CAS Latency = 3)
Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a
continuous flow of data can be maintained. A READ command can be initiated on any clock cycle following a
previous READ command, and may be performed to the same or a different (active) bank. The first data element
from the new burst follows either the last element of a completed burst (Figure 15) or the last desired data element
of a longer burst which is being truncated (Figure 16). The new READ command should be issued x cycles after
the first READ command, where x equals the number of desired data elements.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
2%!$
./0
./0
./0
./0
"A!
#OLB
#,
$1
$/N
$/N
$/N
$/N
$/B
$/B
$/B
$/N
$/N
$/N
$/N
$/B
$/B
#,
$1
"A!#
OLNB"AN
K!#OLU
MNNB $/N
B$A
TA/UTFROMCOLU
MN
NB
"URST,ENGTHIN
TH
ECASESH
O
WN
SUBSEQ
UENTELE
M
ENTSO
F$A
TA/U
TAREPROVID
E
DIN
THE
PROG
RAMM
EDORDE
RFOLLOW
IN
G$/
N B
Figure 15
Data Sheet
$O
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RE
Consecutive READ Bursts
19
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
#,+
#OM
MA
ND
2%!$
2%!$
2%!$
2%!$
!DDRE
SS
"A!
#OLN
"A!
#OLA
"A!
#OLX "A!
#OLM
./0
./0
./0
./0
./0
#,
$1
$/N
$/A
$/X
$/M
$/M
$/M
$/M
$/N
$/A
$/X
$/M
$/M
$/M
#,
$1
$O
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RE
"A!#O
LNETC "AN
K!#O
LU
MNNETC $/N
ETC $A
TA/U
TFRO
MCOLU
MNNE
TC
"URST,ENGTHIN
TH
ECASESHO
WN
BURS TSARE
TERM
IN
ATED
BYCON
SECUTIV E2%
!
$CO
M
MA
NDS
SUBSE
Q
UENTELE
MENTSO
F$A
TA/U
TAR EPRO
VID
EDIN
THEPR OGRA
MMED
ORDE
RFOLLO
W
IN
G$/
M
Figure 16
Random READ Bursts
Non-consecutive READ bursts are shown in Figure 17.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
./0
2%!$
./0
./0
./0
"A!
#OLB
#,
$1
$/N
$/N
$/N
$/N
$/N
$/N
$/N
$/B
$/B
#,
$1
$/N
$/B
"A!#
OLNB"AN
K!#OLU
MNNB
$/N
B$A
TA/UTFROMCOLU
MN
NB
"URST,ENGTHIN
TH
ECASESHO
WN
SUBSEQ
UENTELE
MEN
TSO
F$A
TA/U
TAREPR OVID
ED
IN
THE
PROG
RAMMED
ORDE
RFOLLOW
IN
G$/
N B
Figure 17
Data Sheet
$O
NgT#A
RE
Non-Consecutive READ Bursts
20
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.5.1
READ Burst Termination
Data from any READ burst may be truncated using the BURST TERMINATE command (see Page 30), provided
that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the
BURST TERMINATE command must be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. This is shown in Figure 18. The
BURST TERMINATE command may be used to terminate a full-page READ which does not self-terminate.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
"34
./0
./0
./0
./0
./0
#,
$1
$/N
$/N
$/N
$/N
$/N
#,
$1
$/N
"A!#
OLN"ANK !#O
LU
MNN
$/N
$A
TA/U
TFRO
MCOLU
MNN
"URST,ENGTHIN
TH
ECASESHO
WN
SUBSEQ
UENTELE
MEN
TSO
F$A
TA/U
TAREPR OVID
ED
IN
THE
PROGRA
MMED
ORDE
RFOLLOW
IN
G$/
N 4HE
BURSTIS TER MIN
ATEDAFTERTHE
RDDATA
ELE
ME
NT
Figure 18
Terminating a READ Burst
2.4.5.2
Clock Suspend Mode for READ Cycles
$O
NgT#A
RE
Clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. As long as
CKE is registered LOW, the following internal clock pulse(s) will be ignored and data on DQ will remain driven, as
shown in Figure 19.
#,+
#+%
INTER NAL
CLO
CK
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
T#3,
$1
$/N
T#3,
$/N
Data Sheet
./0
T#3,
$/N
$/N
$O
NgT#A
RE
"A!#O
LNETC "AN
K!#O
LU
MNNETC $/N
ETC $A
TA/U
TFRO
MCOLU
MNNE
TC
#,
IN
THECASESH
OWN
CLO
CK CYCLE
#LOCK SU
SPEND
LATENCY T#3,IS Figure 19
./0
Clock Suspend Mode for READ Bursts
21
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.5.3
READ - DQM Operation
DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing
parameters as listed in Table 10 also apply to this DQM operation. The read burst in progress is not affected and
will continue as programmed.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
./0
./0
./0
./0
T$1:
$1 $1
$/N
$/N
$/N
$O
NgT#A
RE
"A!#O
LNBA
NK!
COLU
MN
N
$/N
$A
TA/U
TFRO
MCOLU
MNN
#,
IN
THECASESH
OWN
$1-READ
LA
TENCYT$1:IS CLO
CKCYCLE
S
Figure 20
READ Burst - DQM Operation
2.4.5.4
READ to WRITE
A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed
to the same or a different (active) bank. Care must be taken to avoid bus contention on the DQs; therefore it is
recommended that the DQs are held in High-Z state for a minimum of 1 clock cycle. This can be achieved by either
delaying the WRITE command, or suppressing the data-out from the READ by pulling DQM HIGH two clock cycles
prior to the WRITE command, as shown in Figure 21. With the registration of the WRITE command, DQM acts as
a write mask: when asserted HIGH, input data will be masked and no write will be performed.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
./0
72)4%
./0
./0
"A!
#OLB
$1 #,
$1
$/N
$/N
(IG
H:
$)B
$)B
$)B
$/N
(IG
H:
$)B
$)B
$)B
#,
$1
$O
NgT#A
RE
"A!#O
LNBB
ANK!COLU
MN
NB
$/N
$ATA
/UTFR OMC OLU
MNN $
)B$
ATA)NTOCOLU
MNB
$1-IS ASSER TED(
)'
(TOSET$1
STO(IG
H:
STA
TEFORC LO
CKCYC LE
PRIO
RTOTHE72)4%
COMM
AND
Figure 21
Data Sheet
READ to WRITE Timing
22
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.5.5
READ to PRECHARGE
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in Figure 22.
The PRECHARGE command should be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. Following the PRECHARGE
command, a subsequent ACTIVE command to the same bank cannot be issued until tRP is met. Please note that
part of the row precharge time is hidden during the access of the last data elements.
In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same READ burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
#,+
T20
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
!
!0 $IS!0
./0
./0
./0
02%
./0
./0
!#4
"A!
2OWA
"A!
0RE!
LL
!0
0RE"
ANK !
#,
$1
$/N
$/N
$/N
$/N
$O
NgT#A
RE
"A!#
OLNBAN
K!
COLU
MNN "!
!M
2O
WBAN
K!ROWX
$/N
$A
TA/U
TFRO
MCOLU
MNN
"URST,ENGTHIN
TH
ECASE
SHO
WN
#!3LA
TENCY IN
THECAS ESHOW
N
SUBSEQ
UENTELE
MEN
TSO
F$A
TA/U
TAREPR OVID
ED
IN
THE
PROGRA
MMED
ORDE
RFOLLOW
IN
G$/
N
Figure 22
Data Sheet
READ to PRECHARGE Timing
23
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.6
WRITE
WRITE bursts are initiated with a WRITE command, as
shown in Figure 23. Basic timings for the DQs are
shown in Figure 24; they apply to all write operations.
The starting column and bank addresses are provided
with the WRITE command, and Auto Precharge is
either enabled or disabled for that access. If Auto
Precharge is enabled, the row being accessed is
precharged at the completion of the write burst. For the
generic WRITE commands used in the following
illustrations, Auto Precharge is disabled.
#,+
#+%
(IG
H #3
2!3
#!3
7%
! !
#!
%NAB
LE!
0
!
"!"
AN
K!
DD
RES S
#!
#O
LUM
N
!
DD
RESS !0!
UTO0
RE
CHA
RGE
!0
$ISA
BLE!0
"!
"
!
Figure 23
$O
NgT#
AR E
"!
WRITE Command
#,+
T)(
T)3
$1 T)(
T)3
$1
$)N
$)N
$O
NgT#A
RE
Figure 24
Basic WRITE Timing Parameters for DQs
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 25 and Figure 26 show a single WRITE burst for each supported CAS latency setting.
Data Sheet
24
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Table 11
Timing Parameters for WRITE
Parameter
Symbol
- 7.5
DQ input hold time
max.
1.5
—
ns
—
0.8
—
ns
—
0.5
—
ns
—
DQM input hold time
tDQW
tRC
tRCD
tRAS
tWR
tRP
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Notes
min.
tIS
tIH
DQ and DQM input setup time
Units
0
—
tCK
—
67
—
ns
1)
19
—
ns
1)
45
100k
ns
1)
14
—
ns
1)
19
—
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
#,+
T2#$ #OM
MAND
!#4
"A!
!DDRES S 2
OWX
./0
T72
T2!3 72)4%
T20
T2#
./0
./0
./0
./0
02%
./0
"A!
#OLN
!#4
"A!
2OWB
0RE!
LL
!!0
2OWX $IS
!0
!0
2OWB
0RE
"A
NK!
$1
$)N
$)N
$)N
$)N
"A!#O
LNBANK !C OLU
MNN
$)N$
ATA)NTOC OLU
MNN
"URST,ENG
THIN
THECAS ESHOW
N
SU
BSEQUEN
TELEME
NTS OF$A
TA)NAREPROV ID
E
DIN
THE
PROG
RAMM
EDORDE
RFOLLOW
IN
G$)N
Figure 25
Data Sheet
$O
NgT#A
RE
WRITE Burst (CAS Latency = 2)
25
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
#,+
T2#$ #OM
MAND !#4
./0
T72
T2!3 ./0
"A!
!DDRES S 2
OWN
72)4
%
T20
T2#
./0
./0
./0
./0
02%
./0
./0
"A!
#OLN
!#4
"A!
2OWB
0RE!
LL
!!0
2OXW
$IS
!0
$1
$)N
2OW
B
!0
0RE"A
NK !
$)N
$)N
$)N
"A!#O
LNBANK !C OLU
MNN
$)N$
ATA)NTOC O
LU
MNN
"URST,ENG
THIN
THECAS ESHOW
N
SU
BSEQUEN
TELEME
NTS OF$A
TA)NAREPROV ID
E
DIN
THE
PROG
RAMM
EDORDE
RFOLLOW
IN
G$)N
Figure 26
$O
NgT#A
RE
WRITE Burst (CAS Latency = 3)
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge
of clock following the previous WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst (Figure 27) or the last desired data element of a longer burst which is being
truncated (Figure 28). The new WRITE command should be issued x cycles after the first WRITE command,
where x equals the number of desired data elements.
#,+
#OM
MA
ND
!DDRE
SS
$1
./0
72)4%
./0
./0
./0
"A!
#OLN
$)N
72)4%
./0
./0
./0
$)B
$)B
$)B
"A!
#OLB
$)N
$)N
$)N
$)B
"A!#
OLNB"AN
K!#OLU
MNNB $)NB
$A
TA
)NTOCOLU
M
NNB "URST,ENGTHIN
TH
ECA
SESH
O
WN
SUBSEQU
ENTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OG
RAMME
DOR DERFO
LLO
WIN
G$)NB Figure 27
Data Sheet
$O
NgT#A
RE
Consecutive WRITE Bursts
26
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
#,+
#OM
MA
ND
./0
!DDRE
SS
$1
72)4%
72)4%
72)4%
72)4%
"A!
#OLN
"A!
#OLA
"A!
#OLX "A!
#OLM
$)N
$)A
$)X
$)M
./0
./0
./0
$)M
$)M
$)M
"A!#O
LNETC "AN
K!#O
LU
MNNETC $)NETC $A
TA)NTOCO
LU
MNNETC
"URST,ENGTHIN
TH
ECASE
SH
O
WN
BU
RSTSAR ETERM
IN
ATED
BYCO
N
SECUTIVE
72)4%C OMM
AN
DS
SUBSEQUE
NTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OGRA
MME
DOR DERFO
LLO
WIN
G$)M
Figure 28
./0
$O
NgT#A
RE
Random WRITE Bursts
Non-consecutive WRITE bursts are shown in Figure 29.
#,+
#OM
MA
ND
!DDRE
SS
$1
./0
72)4%
./0
./0
./0
"A!
#OLN
$)N
./0
72)4%
./0
./0
$)B
$)B
"A!
#OLB
$)N
$)N
$)N
$)B
"A!#
OLNB"AN
K!#OLU
MNNB $)NB
$A
TA
)NTOCOLU
M
NNB "URST,ENGTHIN
TH
ECA
SESH
O
WN
SUBSEQU
ENTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OG
RAMME
DOR DERFO
LLO
WIN
G$)NB Figure 29
Non-Consecutive WRITE Bursts
2.4.6.1
WRITE Burst Termination
$O
NgT#A
RE
Data from any WRITE burst may be truncated using the BURST TERMINATE command (see Page 30), provided
that Auto Precharge was not activated. The input data provided coincident with the BURST TERMINATE
command will be ignored. This is shown in Figure 30. The BURST TERMINATE command may be used to
terminate a full-page WRITE which does not self-terminate.
Data Sheet
27
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
#,+
#OM
MA
ND
./0
72)4%
./0
./0
$)N
$)N
"34
./0
./0
"A!
#OLN
!DDRE
SS
$1
$)N
$O
NgT#A
RE
"A!#
OLN"ANK !#O
LU
MNN
$)N$A
TA)NTOCO
LU
MN
N
"URST,ENGTHIN
TH
ECA
SE
SHO
WN
SUBSEQUE
NTELE
MENTSOF$A
TA)NAR EWR ITTENIN
THE
PRO
GRAMM
EDORD
ERFOLLO
WIN
G$
)N
4HEBURSTIS TER MIN
ATEDAFTE
RTHE
RDDATA
ELE
MEN
T
Figure 30
Terminating a WRITE Burst
2.4.6.2
Clock Suspend Mode for WRITE Cycles
Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in Figure 31.
#,+
#+%
INTER NAL
CLO
CK
#OM
MA
ND
!DDRE
SS
./0
72)4%
./0
$)N
T#3,
$)N
Data Sheet
T#3,
$)N
$O
NgT#A
RE
"A!#O
LNETC "AN
K!#O
LU
MNNETC $/N
ETC $A
TA/U
TFRO
MCOLU
MNNE
TC
#,
IN
THECASESH
OWN
CLO
CKCYCLE
#LOCK SU
SPEND
LATENCYT#3,IS Figure 31
./0
"A!
#OLN
T#3,
$1
./0
Clock Suspend Mode for WRITE Bursts
28
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.6.3
WRITE - DQM Operation
DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be
performed. The generic timing parameters as listed in Table 11 also apply to this DQM operation. The write burst
in progress is not affected and will continue as programmed.
#,+
#OM
MA
ND
./0
72)4%
./0
./0
./0
$)N
$)N
./0
"A!
#OLN
!DDRE
SS $1 $1
$)N
$O
NgT#A
RE
"A!#
OLN"ANK !#O
LU
MNN
$)N$A
TA)NTOCOLU
MN
N
"URST,ENGTHIN
TH
ECASESHO
WN
SU
BSE
QUE
NTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OGRAM
ME
DOR DERFO
LLO
WIN
G
$)NWITHTH
EFIR STELEM
ENT$)N
BEIN
GMA
SKED
$1-WR ITELATE
NCYIS CLO
CKCYCLE
S
Figure 32
WRITE Burst - DQM Operation
2.4.6.4
WRITE to READ
A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed
to the same or a different (active) bank. With the registration of the READ command, data inputs will be ignored
and no WRITE will be performed, as shown in Figure 33.
#,+
#OM
MA
ND
!DDRE
SS
72)4%
./0
./0
"A!
#OLN
2%!$
./0
./0
./0
./0
"A!
#OLB
#,
$1
$)N
$)N
(IG
H :
$)N
7RITEDATA
AREIGNO
RED
$1
$)N
$)N
$/B
$/B
$/B
$/B
$)B
#,
(IGH
:
$)N
"A!#O
LNBB
ANK!COLU
MN
NB
$O
NgT#A
RE
$)N$A
TA)NTOCOLUMN
N $/
B$ATA
/UTFRO
MCOLU
MN
B
"URST,ENGTHIN
TH
ECASESHO
WN
SUBSEQU
ENTELE
MENTSOF$A
TA)N/
UTAREPR OVID
ED
INTHEPROGRA
MME
DORDER FOLLOWIN
G
$)N$
/
B
$)N
IS IG
N
OREDDUE
TO2
%!
$COMM
AND
.O
$1
-MAS KING
REQUIR EDATTHIS POIN
T
Figure 33
Data Sheet
WRITE to READ Timing
29
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.6.5
WRITE to PRECHARGE
A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in Figure 34.
The PRECHARGE command should be issued tWR after the clock edge at which the last desired data element of
the WRITE burst was registered. Additionally, when truncating a WRITE burst, DQM must be pulled to mask input
data presented during tWR prior to the PRECHARGE command. Following the PRE-CHARGE command, a
subsequent ACTIVE command to the same bank cannot be issued until tRP is met.
In the case of a WRITE being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same WRITE burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
#,+
T72
#OMM
AND
./0
72)4%
!DDR ESS
"A!
#OLN
!
!0 $IS!0
./0
./0
./0
T20
02%
"A!
./0
!#4
"A!
2OWA
0RE!
LL
!0
0RE"
ANK !
$1-
$1
$)N
$)N
$)N
"A!#O
LNBA
NK!
COLU
MN
N
!0!UTO
0R ECHA
RGE
$O
NgT#A
RE
$)N$A
TA)NTOCOLU
MN
N
$IS !0
$
IS ABLE!U
TO0R EC HA
RGE
"URST,ENGTHIN
TH
ECASESHO
WN
SUBSEQUE
NTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OGRAM
ME
DOR DERFO
LLO
WIN
G$)N
DPR IO
RTO
02%
#
(
!
2
'%COMMA
ND
$)N
IS MAS KEDD
UETO$1
-PULLE
D()'(
DURIN
GT72
PERIO
Figure 34
WRITE to PRECHARGE Timing
2.4.7
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ or WRITE bursts (with Auto Precharge
disabled). The most recently registered READ or
WRITE command prior to the BURST TERMINATE
command will be truncated, as shown in Figure 18 and
Figure 30, respectively.
#,+
#+%
(IG
H #3
The BURST TERMINATE command is not allowed for
truncation of READ or WRITE bursts with Auto
Precharge enabled.
2!3
#!3
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 35
Data Sheet
BURST TERMINATE Command
30
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.8
PRECHARGE
The PRECHARGE command is used to deactivate
(close) the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a
subsequent row access a specified time (tRP) after the
PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care”.
#,+
#+%
(IG
H #3
2!3
#!3
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE
command will be treated as a NOP if there is no open
row in that bank, or if the previously open row is already
in the process of precharging.
7%
! !
!!
!LL"
ANK S !
/NE
"A
NK "!
"
!
"!
$O
NgT#A
R E
"!
"
ANK!
DD
RES S
IF!
,
O
THE
RW
ISE
$
O
NgT#
A
RE Figure 36
PRECHARGE Command
2.4.8.1
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or
WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is
non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto
Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, as described for each burst type.
Table 12
Timing Parameters for PRECHARGE
Parameter
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Symbol
tRAS
tWR
tRP
- 7.5
Units
Notes
min.
max.
45
100k
ns
1)
14
–
ns
1)
19
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Data Sheet
31
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.8.2
CONCURRENT AUTO PRECHARGE
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE
command issued to a different bank.
Figure 37 shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered.
Figure 38 shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge)
to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled
HIGH two clock cycles prior to the WRITE to prevent bus contention.
Figure 39 shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The precharge to bank n will begin tWR after the new command to bank m is registered. The last valid
data-in to bank n is one clock cycle prior to the READ to bank m.
Figure 40 shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto
Precharge) to bank m. The precharge to bank n will begin tWR after the WRITE to bank m is registered. The last
valid data-in to bank n is one clock cycle prior to the WRITE to bank m.
#,+
#OM
MA
ND
./0
2$ !0
./0
"ANKN
#OLB
!DDRE
SS
2%!$
./0
./0
./0
"ANKM
#OLX #,
$1
T20
BA
NKN
$/B
$/B
$/X
$/X $/X $O
NgT#A
RE
2$!
02EA
DWITH!UTO0R ECHA
RGE 2%!
$
2EA
DWITHORWITHO
UT!UTO0R ECHA
RGE
#,
AND
"URS T,EN
GTHINTH
ECASE
SHOWN
2EADWITH!
UTO0R EC HAR GETOBAN
KNIS IN
TER RUP
TEDBYSUB
SEQ
UENT2E
ADTOB
ANKM
Figure 37
./0
READ with Auto Precharge Interrupted by READ
#,+
#OM
MA
ND
!DDRE
SS
./0
2$ !0
./0
./0
"ANKN
#OLB
72)4%
./0
./0
./0
"ANKM
#OLX $1 #,
$1
T20
BA
NKN
$/B
$)X $)X
$)X
2$ !0
2E
ADWITH!UTO0R ECHA
RGE 72)4%
7R ITE
WITHORWITH
OUT!UTO0
R ECHARG
E
#,
AND
"URS T,EN
GTHINTH
ECASE
SHOWN
2EADWITH!
UTO0R EC HAR GETOBAN
KNIS IN
TERRUP
TEDBYSUBSEQ
UENT7R ITETOBANK M
Figure 38
Data Sheet
$)X $O
NgT#A
RE
READ with Auto Precharge Interrupted by WRITE
32
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
#,+
#OM
MA
ND
72 !0
!DDRE
SS
"ANKN
#OLB
./0
2%!$
./0
./0
$/B
./0
T20
BA
NKN
$/B
$/X
$/X $/X $/X $O
NgT#A
RE
72 !
07R ITEW
ITH!U
TO0REC HAR GE 2
%!
$2E
A
DWITHOR WITHOU
T!UTO0RE
CHAR GE
#,
AND
"URS T,EN
GTHINTH
ECA
SE
SHOWN
7RITE
WITH!U
TO0R ECH
ARGETOBANKNIS IN
TER RUPTED
BYSU
BSE
QUEN
T2E
AD
TOBANK M
Figure 39
./0
"ANKM
#OLX T72
BA
NKN
#,
$1
./0
WRITE with Auto Precharge Interrupted by READ
#,+
#OM
MA
ND
72 !0
!DDRE
SS
"ANKN
#OLB
./0
72)4%
./0
./0
$)B
./0
$)B
$)X $)X
T20
BA
NKN
$)X
$)X
72 !0
7R ITEWITH!U
TO0REC HARG
E 7
2)4%7R ITEW
ITHORWITHO
UT!U
TO0R EC HARG
E
"URST,ENGTHIN
TH
ECASE
SHO
WN
7RITE
WITH!U
TO0R ECH
ARGETOBANKNIS IN
TER RUPTED
BYSU
BSEQUEN
T7R ITETOBAN
KM
Figure 40
Data Sheet
./0
"ANKM
#OLX T72
BA
NKN
$1
./0
$O
NgT#A
RE
WRITE with Auto Precharge Interrupted by WRITE
33
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.9
AUTO REFRESH and SELF REFRESH
The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways:
by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode.
2.4.9.1
AUTO REFRESH
Auto Refresh is used during normal operation of the
Mobile-RAM. The command is non persistent, so it
must be issued each time a refresh is required. A
minimum row cycle time (tRC) is required between two
AUTO REFRESH commands. The same rule applies to
any access command after the auto refresh operation.
All banks must be precharged prior to the AUTO
REFRESH command.
#,+
#+%
(IG
H #3
2!3
#!3
The refresh addressing is generated by the internal
refresh controller. This makes the address bits “Don’t
Care” during an AUTO REFRESH command. The
Mobile-RAM requires AUTO REFRESH cycles at an
average periodic interval of 7.8 µs (max.). Partial array
mode has no influence on auto refresh mode.
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 41
AUTO REFRESH Command
#,+
T20
#OMM
AND
02%
./0
T2#
!2&
T2#
./0
./0
$1
Data Sheet
./0
!#4
2OWN
0RE!
LL
(IG
H :
$O
NgT#A
RE
"A!2O
WNBA
NK!ROWN
Figure 42
./0
"A!
2OWN
!DD
RESS !!0 !2&
Auto Refresh
34
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.9.2
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the Mobile-RAM, even if the rest of the system
is powered down. When in the self refresh mode, the
Mobile-RAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is LOW. Input
signals except CKE are “Don’t Care” during SELF
REFRESH.
#,+
#+%
#3
2!3
The procedure for exiting SELF REFRESH requires a
stable clock prior to CKE returning HIGH. Once CKE is
HIGH, NOP commands must be issued for tRC because
time is required for a completion of any internal refresh
in progress.
#!3
7%
!!
"!
"
!
If during normal operation burst auto refresh or user
controlled refresh is used, add 8192 auto refresh cycles
just before self refresh entry and just after self refresh
exit.
$O
NgT#A
R E
Figure 43
SELF REFRESH Entry Command
#,+
T20
T2#
T32% 8
T2#
#+%
#OMM
AND
02%
./0
!2&
./0
./0
./0
!2&
./0
!#4
"A!
2OWN
!DD
RESS !!0 2OWN
0RE!LL
$1
(IGH
:
$
ON
gT#A
RE
3ELF2E
FRE
SH
%NTRY #O
MMAN
D
3ELF2E
FRES H
%XIT#O
MM
AND
%XITFROM
3ELF2E
FRESH
!NY#O
MM
AND
!UTO2E
FRESH
2ECOMM
ENDED Figure 44
Self Refresh Entry and Exit
Table 13
Timing Parameters for AUTO REFRESH and SELF REFRESH
Parameter
ACTIVE to ACTIVE command period
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
Symbol
tRC
tRP
tREF
tSREX
- 7.5
Units
Notes
–
ns
1)
19
–
ns
1)
–
64
ms
1)
1
–
tCK
1)
min.
max.
67
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Data Sheet
35
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.10
POWER DOWN
Power-down is entered when CKE is registered LOW
(no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred
to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CLK
and CKE. CKE LOW must be maintained during powerdown.
#,+
#+%
#3
2!3
#!3
Power-down duration is limited by the refresh
requirements of the device (tREF).
7%
!!
"!
"
!
The power-down state is synchronously exited when
CKE is registered HIGH (along with a NOP or
DESELECT command). One clock delay is required for
power down entry and exit.
$O
NgT#A
R E
Figure 45
Power Down Entry Command
#,+
T20
#+%
#OMM
AND
02%
./0
./0
./0
!DD
RESS !!0 $1
6ALID
6ALID
0RE!
LL
6ALID
(IG
H :
0OW
ER $O
WN
%NTR Y
%XITFRO
M
0OWE
R$O
WN
0RECHA
RGE0OWE
R$O
WN
MOD
ESH
OWN
ALLBAN
KSARE
ID
LE
AND
T20
MET
WHE
N0OW
E
R$O
WN
%
NTRY#O
MMA
NDISISS UED
Figure 46
Power Down Entry and Exit
2.4.10.1
DEEP POWER DOWN
!NY
#OMMAN
D
$O
NgT#A
RE
The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current
consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. Figure 35) except
that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this
mode. To enter the deep power down mode all banks must be precharged.
The deep power down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command
sequence as for power-up initialization, including the 200µs initial pause, has to be applied before any other
command may be issued (cf. Figure 3 and Figure 4).
Data Sheet
36
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
2.5
Function Truth Tables
Table 14
Current State Bank n - Command to Bank n
Current State
CS
RAS CAS WE Command / Action
Notes
H
X
X
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
H
NO OPERATION (NOP / continue previous operation)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
L
L
H
AUTO REFRESH
1) to 7)
L
L
L
L
MODE REGISTER SET
1) to 7)
L
L
H
L
PRECHARGE
1) to 6), 8)
L
H
L
H
READ (select column and start READ burst)
1) to 6), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 6), 9)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6), 10)
Read
(AutoPrecharge
Disabled)
L
H
L
H
READ (select column and start new READ burst)
1) to 6), 9)
L
H
L
L
WRITE (select column and start new WRITE burst)
1) to 6), 9)
L
L
H
L
PRECHARGE (truncate READ burst, start precharge)
1) to 6), 10)
L
H
H
L
BURST TERMINATE
1) to 6), 11)
Write
(AutoPrecharge
Disabled)
L
H
L
H
READ (select column and start READ burst)
1) to 6), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 6), 9)
L
L
H
L
PRECHARGE (truncate WRITE burst, start precharge)
1) to 6), 10)
L
H
H
L
BURST TERMINATE
1) to 6), 11)
Any
Idle
Row Active
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was self
refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Write:
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and according to Table 15.
Precharging:
Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank
is in the “idle” state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank
is in the “row active” state.
Read with AP
Enabled:
Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write with AP
Enabled:
Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Data Sheet
37
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
on each positive clock edge during these states.
Refreshing:
Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the
SDRAM is in the “all banks idle” state.
Accessing Mode
Register:
Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once
tMRD is met, the SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all
banks are in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle and no bursts are in progress.
8) Same as NOP command in that state.
9) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and
READs or WRITEs with Auto Precharge disabled.
10) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
11) Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
Table 15
Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS CAS WE Command / Action
Notes
H
X
X
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
H
NO OPERATION (NOP / continue previous operation)
1) to 6)
Idle
X
X
X
X
Any command otherwise allowed to bank n
1) to 6)
Row Activating,
Active, or
Precharging
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 7)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 8)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 7)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 9)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 7), 9)
Any
Read (AutoPrecharge
Disabled)
Write (AutoPrecharge
Disabled)
Read
(with AutoPrecharge)
Write
(with AutoPrecharge)
1) to 6)
PRECHARGE (deactivate row in bank or banks)
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was Self
L
L
H
L
Refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
Data Sheet
38
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
3) Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Write:
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Read with AP
Enabled:
Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write with AP
Enabled:
Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6) All states and sequences not shown are illegal or reserved.
7) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and
READs or WRITEs with Auto Precharge disabled.
8) Requires appropriate DQM masking.
9) Concurrent Auto Precharge: bank n will start precharging when its burst has been interrupted by a READ or WRITE
command to bank m.
Table 16
Truth Table - CKE
CKEn-1
CKEn
Current State
Command
Action
Notes
L
L
Power Down
X
Maintain Power Down
1)2)3)4)
Self Refresh
X
Maintain Self Refresh
1) to 4)
Clock Suspend
X
Maintain Clock Suspend
1) to 4)
Deep Power Down
X
Maintain Deep Power
Down
1) to 4)
Power Down
DESELECT or NOP
Exit Power Down
1) to 4)
Self Refresh
DESELECT or NOP
Exit Self Refresh
1) to 5)
Clock Suspend
X
Exit Clock Suspend
1) to 4)
Deep Power Down
X
Exit Deep Power Down
1) to 4), 6)
All Banks Idle
DESELECT or NOP
Enter Precharge Power
Down
1) to 4)
Bank(s) Active
DESELECT or NOP
Enter Active Power Down
1) to 4)
All Banks Idle
AUTO REFRESH
Enter Self Refresh
1) to 4)
Read / Write burst
(valid)
Enter Clock Suspend
1) to 4)
L
H
H
1)
2)
3)
4)
5)
6)
H
L
H
1) to 4)
see Table 14 and Table 15
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
DESELECT or NOP commands should be issued on any clock edges occurring during tRC period.
Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
Data Sheet
39
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 17
Absolute Maximum Ratings
Parameter
Symbol
Power Supply Voltage
Power Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Operation Case Temperature
Commercial
Power Dissipation
Short Circuit Output Current
Unit
min.
max.
VDD
VDDQ
VIN
VOUT
TC
-0.3
2.7
V
-0.3
2.7
V
-0.3
V
-0.3
VDDQ + 0.3
VDDQ + 0.3
0
+ 70
°C
-25
+85
°C
TSTG
PD
IOUT
-55
+150
°C
–
0.7
W
–
50
mA
Extended
Storage Temperature
Values
V
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Table 18
Pin Capacitances1)2)
Parameter
Symbol
CI1
CI2
CIO
Input capacitance: CLK
Input capacitance: all other input pins
Input/Output capacitance: DQ
Values
Unit
min.
max.
1.5
3.0
pF
1.5
3.0
pF
3.0
5.0
pF
1) These values are not subject to production test but verified by device characterization.
2) Input capacitance is measured according to JEP147 with VDD, VDDQ applied and all other pins (except the pin under test)
floating. DQ’s should be in high impedance state. This may be achieved by pulling CKE to low level.
Data Sheet
40
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
Table 19
Electrical Characteristics1)
Parameter
Power Supply Voltage
Power Supply Voltage for DQ Output Buffer
Input high voltage
Input low voltage
Output high voltage (IOH = -0.1 mA)
Output low voltage (IOL = 0.1 mA)
Input leakage current
Symbol
VDD
VDDQ
VIH
VIL
VOH
VOL
IIL
IOL
Values
Unit
Notes
–
min.
max.
1.70
1.95
V
1.70
1.95
V
–
0.8 × VDDQ
VDDQ + 0.3
V
2)
-0.3
0.3
V
2)
VDDQ - 0.2
–
V
–
–
0.2
V
–
-1.0
1.0
µA
–
Output leakage current
-1.5
1.5
µA
–
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (extended); all voltages referenced to VSS. VSS and VSSQ must be at same
potential.
2) VIH may overshoot to VDD + 0.8 V for pulse width < 4 ns; VIL may undershoot to -0.8 V for pulse width < 4 ns.
Pulse width measured at 50% with amplitude measured between peak voltage and DC reference level.
Data Sheet
41
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
3.2
AC Characteristics
Table 20
AC Characteristics1)2)3)4)
Parameter
Symbol
Clock cycle time
—
ns
9.5
—
ns
—
133
MHz
—
105
MHz
tAC
—
5.4
ns
—
6.0
ns
tCH
tCL
tIS
tIH
2.5
—
ns
—
2.5
—
ns
—
1.5
—
ns
7)
0.5
—
ns
7)
0.8
—
2
—
tCK
—
1.0
–
ns
—
3.0
7.0
ns
—
2.5
—
ns
5)6)
—
2
—
0
—
tCK
tCK
67
—
ns
8)
19
—
ns
8)
15
—
ns
8)
45
100k
ns
8)
14
—
ns
9)
19
—
ns
8)
—
64
ms
—
—
tCK
—
CL = 2
Access time from CLK
CL = 3
CL = 2
Clock high-level width
Clock low-level width
Address, data and command input setup time
Address and command input hold time
Data (DQ) input hold time
tMRD
tLZ
tHZ
tOH
tDQZ
tDQW
tRC
tRCD
tRRD
tRAS
tWR
tRP
tREF
tSREX
MODE REGISTER SET command period
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
1
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (extended); VDD = VDDQ = 1.70V to 1.95V;
2)
3)
4)
5)
—
7.5
fCK
CL = 3
Notes
max.
CL = 2
Clock frequency
Unit
min.
tCK
CL = 3
- 7.5
—
5)6)
—
All parameters assumes proper device initialization.
AC timing tests measured at 0.9 V.
The transition time tT is measured between VIH and VIL; all AC characteristics assume tT = 1 ns.
Specified tAC and tOH parameters are measured with a 30 pF capacitive load only as shown below:
I/O
30 pF
6) If tT(CLK) > 1 ns, a value of (tT/2 - 0.5) ns has to be added to this parameter.
7) If tT > 1 ns, a value of [0.5 x (tT - 1)] ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK ≤ 72 MHz.
With fCK > 72 MHz two clock cycles for tWR are mandatory. Qimonda recommends to use two clock cycles for the write
recovery time in all applications.
Data Sheet
42
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
3.3
Operating Currents
Table 21
Maximum Operating Currents1)
Parameter & Test Conditions
Symbol
Values
Unit Note
- 7.5
Operating current:
one bank:
active / read / precharge, BL = 1, tRC = tRCmin
IDD1
60
mA
2)3)
Precharge power-down standby current:
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax,
inputs changing once every two clock cycles
IDD2P
0.6
mA
2)
Precharge power-down standby current with clock stop:
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD2PS
0.5
mA
–
Precharge non power-down standby current:
all banks idle, CS ≥ VIHmin, CKE ≥ VIHmin,
inputs changing once every two clock cycles
IDD2N
13
mA
2)
Precharge non power-down standby current with clock stop:
all banks idle, CS ≥ VIHmin, CKE ≥ VIHmin, all inputs stable
IDD2NS
1.0
mA
–
Active power-down standby current:
one bank active, CS ≥ VIHmin, CKE ≤ VILmax,
inputs changing once every two clock cycles
IDD3P
1.0
mA
2)
Active power-down standby current with clock stop:
one bank active, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD3PS
0.75
mA
–
Active non power-down standby current:
one bank active, CS ≥ VIHmin, CKE ≥ VIHmin,
inputs changing once every two clock cycles
IDD3N
15
mA
2)
Active non power-down standby current with clock stop:
one bank active, CS ≥ VIHmin, CKE ≥ VIHmin, all inputs stable
IDD3NS
1.5
mA
–
Operating burst read current:
all banks active; continuous burst read,
inputs changing once every two clock cycles
IDD4
45
mA
2)3)
Auto-Refresh current:
tRC = tRCmin, “burst refresh”,
inputs changing once every two clock cycles
IDD5
90
mA
2)
Self Refresh current:
self refresh mode, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD6
see Table 22
mA
–
µA
4)
Deep Power Down current
IDD7
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (extended); VDD = VDDQ = 1.70V to 1.95V;
20
Recommended Operating Conditions unless otherwise noted
2) These values are measured with tCK = 7.5 ns
3) All parameters are measured with no output loads.
4) Value shown as typical.
Data Sheet
43
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
Table 22
Self Refresh Currents1)2)
Parameter & Test Conditions
Max.
Symbol
Temperature
Self Refresh Current:
Self refresh mode,
half array activation
(PASR = 001)
Self Refresh Current:
Self refresh mode,
quarter array activation
(PASR = 010)
Units
typ.
max.
510
600
70 °C
340
–
45 °C
225
–
25 °C
205
–
85 °C
400
470
70 °C
285
–
45 °C
200
–
25 °C
180
–
85 °C
340
400
70 °C
250
–
45 °C
185
–
25 °C
170
–
85 °C
Self Refresh Current:
Self refresh mode,
full array activation
(PASR = 000)
Values
IDD6
µA
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (extended); VDD = VDDQ = 1.70V to 1.95V
2) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component’s actual
temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for
TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85°C. Typ. values are obtained
from device characterization.
Data Sheet
44
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Package OutlinesPG-VFBGA-54-8 (Plastic Green Very Thin Fine Pitch Ball Grid Array Package)
You can find all of our packages, sorts of packing and others in our
Qimonda Internet Page : http://www.qimonda.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
45
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
Data Sheet,
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Table of Contents
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.1.6
2.2.1.7
2.2.1.8
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.5.3
2.4.5.4
2.4.5.5
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.7
2.4.8
2.4.8.1
2.4.8.2
2.4.9
2.4.9.1
2.4.9.2
2.4.10
2.4.10.1
2.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor . . . . . . . . . . . . . . . . . 11
Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Suspend Mode for READ Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
READ - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
WRITE Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock Suspend Mode for WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
WRITE - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DEEP POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
46
3
3
4
5
6
40
40
42
43
Data Sheet,
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
47
Data Sheet,
Edition 2006-12
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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