CYPRESS CY62177EV30LL

CY62177EV30 MoBL®
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Features
Functional Description
■
Thin small outline package (TSOP) I configurable as 2 M × 16
or as 4 M x 8 static RAM (SRAM)
■
Very high speed
❐ 55 ns
■
Wide voltage range
❐ 2.2 V to 3.7 V
■
Ultra low standby power
❐ Typical standby current: 3 A
❐ Maximum standby current: 25 A
■
Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE Features
The CY62177EV30 is a high performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
■
Automatic power down when deselected
■
Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 48-ball TSOP I package
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 10 for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application.
Logic Block Diagram
2M × 16
RAM Array
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
BHE
WE
CE2
CE1
OE
BLE
Power-Down
Circuit
Cypress Semiconductor Corporation
Document Number: 001-09880 Rev. *H
•
198 Champion Court
BHE
BLE
•
CE2
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised June 29, 2011
CY62177EV30 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Document Number: 001-09880 Rev. *H
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagram ............................................................ 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
CY62177EV30 MoBL®
Pin Configuration
Figure 1. 48-pin TSOP I (Forward) (2 M × 16 / 4 M × 8) [1, 2]
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62177EV30LL
Min
Typ[3]
Max
2.2
3.0
3.7
55
Standby ISB2 (A)
f = fMax
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
4.5
5.5
35
45
3
25
Notes
1. DNU Pin# 13 needs to be left floating to ensure proper application.
2. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 2 M × 16 SRAM. The 48-TSOP I package can also be used as a 4 M × 8 SRAM
by tying the BYTE signal to VSS. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-09880 Rev. *H
Page 3 of 15
CY62177EV30 MoBL®
DC input voltage [4, 5] .................... –0.3 V to VCC(max) + 0.3 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch up current...................................................... > 200 mA
Operating Range
Supply voltage to ground
potential ........................................ –0.3 V to VCC(max) + 0.3 V
Device
DC voltage applied to outputs
in High Z state [4, 5] ....................... –0.3 V to VCC(max) + 0.3 V
CY62177EV30LL
Range
Ambient
Temperature
VCC[6]
Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
55 ns
Min
Typ[7]
Max
VCC = 2.20 V
2.0
–
–
Unit
VOH
Output HIGH voltage
IOH = –1.0 mA
VCC = 2.70 V
2.4
–
–
V
VOL
Output LOW voltage
IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
VIH
Input HIGH voltage
VCC = 2.2 V to 2.7 V
VIL
Input LOW voltage
VCC= 2.7 V to 3.7 V
IOH = –0.1 mA
V
–
–
0.4
V
1.8
–
VCC + 0.3 V
V
VCC= 2.7 V to 3.7 V
2.2
–
VCC + 0.3 V
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
–0.3
–
0.7[8]
V
–1
–
+1
A
IIX
Input leakage current
IOZ
Output leakage current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC operating supply
current
f = fMax = 1/tRC
–
35
45
mA
–
4.5
5.5
mA
–
3
25
A
ISB2 [9, 10]
Automatic CE
power down
current—CMOS inputs
GND < VI < VCC
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0,
VCC = 3.7 V
Capacitance
Parameter[11]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
15
pF
15
pF
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V.
9. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 2 M × 16 SRAM. The 48-TSOP I package can also be used as a 4 M × 8 SRAM
by tying the BYTE signal to VSS. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used.
10. Chip enables (CE1 and CE2) and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-09880 Rev. *H
Page 4 of 15
CY62177EV30 MoBL®
Thermal Resistance
Parameter[12]
JA
JC
Description
Thermal resistance
(junction to ambient)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, 2-layer
printed circuit board
TSOPI
44.66
Unit
C/W
12.12
C/W
Thermal resistance
(junction to case)
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
GND
30 pF
R2
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Table 1. AC Test Loads
Parameter
R1
R2
RTH
VTH
2.5 V
16667
15385
8000
1.20
3.3 V
1103
1554
645
1.75
Unit



V
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
Conditions
VCC for data retention
ICCDR
[14]
Data retention current
VCC = 1.5 V, CE1 > VCC – 0.2 V or CE2 < 0.2 V, or
(BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or
VIN < 0.2 V
Min
Typ[13]
Max
Unit
1.5
–
–
V
–
–
17
A
tCDR[12]
Chip deselect to data
retention time
0
–
–
ns
tR[15]
Operation recovery time
55
–
–
ns
Figure 3. Data Retention Waveform [16]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
14. Chip enables (CE1 and CE2) and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
16. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-09880 Rev. *H
Page 5 of 15
CY62177EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter[17]
Description
55 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
ns
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
6
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
OE LOW to LOW
Z[18]
5
–
ns
tHZOE
OE HIGH to High
Z[18, 19]
tLZCE
CE1 LOW and CE2 HIGH to Low Z[18]
tLZOE
Z[18, 19]
–
18
ns
10
–
ns
–
18
ns
tHZCE
CE1 HIGH and CE2 LOW to High
tPU
CE1 LOW and CE2 HIGH to power up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power down
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
55
ns
10
–
ns
–
18
ns
BLE/BHE LOW to Low Z
tLZBE
BLE/BHE HIGH to HIGH Z
tHZBE
Write Cycle
[18]
[18, 19]
[20]
tWC
Write cycle time
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
40
–
ns
tAW
Address setup to write end
40
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
40
–
ns
tBW
BLE/BHE LOW to write end
40
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from Write End
0
–
ns
WE LOW to High
Z[18, 19]
–
20
ns
WE HIGH to Low
Z[18]
10
–
ns
tHZWE
tLZWE
Notes
17. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to
VCC(typ), and output loading of the specified IOL/IOH as shown in Table 1 on page 5.
18. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
20. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
Document Number: 001-09880 Rev. *H
Page 6 of 15
CY62177EV30 MoBL®
Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled)[21, 22]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle 2 (OE Controlled)[22, 23]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
tDBE
tHZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
Notes
21. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
22. WE is HIGH for read cycle.
23. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-09880 Rev. *H
Page 7 of 15
CY62177EV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle 1 (WE Controlled) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 27
tHZOE
Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 27
tHZOE
Notes
24. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
25. Data I/O is high impedance if OE = VIH.
26. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-09880 Rev. *H
Page 8 of 15
CY62177EV30 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle 3 (WE Controlled, OE LOW)[28, 29]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tHD
tSD
DATA I/O
NOTE 29
VALID DATA
tLZWE
tHZWE
Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[28, 29]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 29
tHD
VALID DATA
Notes
28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
29. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-09880 Rev. *H
Page 9 of 15
CY62177EV30 MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
[30]
X
[30]
Mode
Power
X
High Z
Deselect/Power Down
Standby (ISB)
X
X[30]
X[30]
High Z
Deselect/Power Down
Standby (ISB)
X
X
H
H
High Z
Deselect/Power Down
Standby (ISB)
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
High Z (I/O8–I/O15):
Data Out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
L
L
H
Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
Write
Active (ICC)
L
H
L
X
L
H
Data In (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
[30]
X
X
L
X
[30]
L
H
X
X[30]
[30]
X
X
Inputs Outputs
Note
30. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-09880 Rev. *H
Page 10 of 15
CY62177EV30 MoBL®
Ordering Information
Speed
(ns)
55
Ordering Code
CY62177EV30LL-55ZXI
Package
Diagram
51-85183
Package Type
48-pin TSOP I (12 × 18.4 × 1 mm) Pb-free
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 7
7
E V30 LL - 55 Z
X
I
Temperature Grade:
I = Industrial
X = Pb-free
Package Type:
Z = 48-pin TSOP I
Speed Grade: 55 ns
Low Power
Voltage Range: V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus Width = × 16
Density = 32-Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-09880 Rev. *H
Page 11 of 15
CY62177EV30 MoBL®
Package Diagram
Figure 10. 48-pin TSOP I (12 × 18.4 × 1 mm), 51-85183
51-85183 *C
Document Number: 001-09880 Rev. *H
Page 12 of 15
CY62177EV30 MoBL®
Acronyms
Acronym
Description
BHE
byte high enable
BLE
byte low enable
CE
chip enable
CMOS
complementary metal oxide semiconductor
I/O
input/output
I/O
input/output
OE
output enable
SRAM
static random access memory
TSOP
thin small outline package
WE
write enable
Document Conventions
Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
MHz
Mega Hertz
µA
microamperes
mA
milliamperes
ms
milliseconds
ns
nanoseconds

ohms
%
percent
pF
picofarads
ps
picoseconds
V
volts
W
watts
Document Number: 001-09880 Rev. *H
Page 13 of 15
CY62177EV30 MoBL®
Document History Page
Document Title: CY62177EV30 MoBL® 32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Document Number: 001-09880
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
498562
NXR
See ECN
New Datasheet
*A
2544845
VKN/PYRS
07/29/08
Removed 45 ns speed bin
Added 70 ns speed bin
Added 48-Pin TSOPI package
Added footnote# 4 related to TSOPI package
Added footnote# 9 related to ISB2 and ICCDR
Updated Ordering information table
*B
2589750
VKN/PYRS
10/15/08
Changed pin functions of pin# 10 from NC to A20 and pin# 13 from A20 to
DNU in 48-Pin TSOPI package
*C
2668432
VKN/PYRS
03/03/09
Replaced 70 ns speed with 55 ns
Extended the VCC range to 3.7 V
Changed ICC (max) spec from 2.8 mA to 4.5 mA at f = 1 MHz
Changed ICC (max) spec from 30 mA to 45 mA at f = f(max)
Removed ISB1 spec
Changed ISB2 (max) spec from 17 A to 25 A
Modified footnote #10
*D
2779867
VKN
10/06/09
Converted from Preliminary to Final
Changed ICC (max) spec from 4.5 mA to 5.5 mA at f = 1 MHz
Changed ICC (typ) spec from 2.2 mA to 4.5 mA at f = 1 MHz
Changed ICC (typ) spec from 28 mA to 35 mA at f = f(max)
Added VIL spec for TSOP I package and footnote# 10
Changed COUT spec from 10 pF to 15 pF
Included thermal specs
Changed tOHA spec from 10ns to 6ns
*E
2899662
AJU
03/26/10
Removed inactive parts from Ordering Information.
Updated Package Diagram
*F
2927528
VKN
05/04/2010
Included BHE, BLE in footnote #11
Added footnote #25 related to chip enable
Added Contents and Acronyms
Updated links in Sales, Solutions, and Legal Information
*G
3177000
AJU
02/18/2011
Updated Features (Removed FBGA package related information).
Updated Pin Configuration (Removed FBGA package related information).
Corrected NC to DNU in footnote #2
Updated Electrical Characteristics (Included BHE and BLE in ISB2 test
conditions to reflect Byte power down feature).
Updated Thermal Resistance (Removed FBGA package related
information).
Updated Data Retention Characteristics (Included BHE and BLE in ICCDR
test conditions to reflect Byte power down feature).
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Removed FBGA package related information in all instances in the
document.
Updated in new template.
*H
3295175
RAME
06/29/2011
Updated Package Diagram.
Updated Table of Contents.
Removed reference to AN1064 SRAM system guidelines.
Document Number: 001-09880 Rev. *H
Page 14 of 15
CY62177EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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PSoC 1 | PSoC 3 | PSoC 5
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cypress.com/go/USB
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© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-09880 Rev. *H
Revised June 29, 2011
Page 15 of 15
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.