CY62167EV30 MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM 16-Mbit (1M x 16 / 2M x 8) Static RAM Features ■ TSOP I package configurable as 1M × 16 or 2M x 8 SRAM ■ Very high speed: 45 ns ■ Temperature ranges ❐ Industrial: –40°C to +85°C ❐ Automotive-A: –40°C to +85°C ■ Wide voltage range: 2.20 V to 3.60 V ■ Ultra-low standby power ❐ Typical standby current: 1.5 μA ❐ Maximum standby current: 12 μA ■ Ultra-low active power ❐ Typical active current: 2.2 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE Features ■ Automatic power-down when deselected ■ CMOS for optimum speed and power ■ Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I packages Functional Description The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits or 2M words by 8 bits. This device features an advanced circuit design that provides an ultra low active current. Ultra low active current is ideal for providing Logic Block Diagram More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: the device is deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from the I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Design Guidelines. 1M × 16 / 2M x 8 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER Power Down Circuit A11 A12 A13 A14 A15 A16 A17 A18 A19 CE2 CE1 BHE • 198 Champion Court CE2 OE CE1 BLE BLE Cypress Semiconductor Corporation Document #: 38-05446 Rev. *I BYTE BHE WE • San Jose, CA 95134-1709 • 408-943-2600 Revised August 13, 2010 [+] Feedback CY62167EV30 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings............................................................. 4 Operating Range............................................................... 4 Electrical Characteristics................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance.......................................................... 5 Data Retention Characteristics ....................................... 6 Switching Characteristics................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document #: 38-05446 Rev. *I Ordering Information...................................................... Ordering Code Definition........................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 12 12 13 14 15 16 16 16 16 Page 2 of 16 [+] Feedback CY62167EV30 MoBL® Pin Configuration Figure 1. 48-Ball VFBGA (6 x 8 x 1mm) Top View [1, 2] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Figure 2. 48-Pin TSOP I Top View [2, 3] A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 Product Portfolio Power Dissipation Product Range VCC Range (V) Speed (ns) Operating ICC (mA) f = 1 MHz CY62167EV30LL Industrial/Auto-A Min Typ[4] Max 2.2 3.0 3.6 45 f = fmax Standby ISB2 (μA) Typ[4] Max Typ[4] Max Typ[4] Max 2.2 4.0 25 30 1.5 12 Notes 1. Ball H6 for the VFBGA package can be used to upgrade to a 32M density. 2. NC pins are not connected on the die. 3. The BYTE pin in the 48-pin TSOPI package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-pin TSOPI package can also be used as a 2M X 8 SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 38-05446 Rev. *I Page 3 of 16 [+] Feedback CY62167EV30 MoBL® DC input voltage[5, 6]........ –0.3 V to 3.9 V (VCC(max) + 0.3 V Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Static discharge voltage........................................... >2001 V (MIL-STD-883, Method 3015) Storage temperature ................................ –65°C to + 150 °C Latch-up current ...................................................... >200 mA Ambient temperature with power applied .......................................... –55 °C to + 125 °C Operating Range Supply voltage to ground potential ..............................–0.3 V to 3.9 V VCC (max) + 0.3 V Device Range Ambient Temperature VCC[7] DC voltage applied to outputs in High Z state[5, 6] ..............–0.3 V to 3.9 V VCC (max) + 0.3 V CY62167EV30LL Industrial/ Auto-A –40 °C to +85 °C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH voltage VOL Output LOW voltage VIH Input HIGH voltage VIL Input LOW voltage IIX IOZ ICC Input leakage current Output leakage current VCC operating supply current ISB1 Automatic power down current—CMOS inputs ISB2[10] Automatic power down current—CMOS inputs Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 IOH = –0.1 mA IOH = –1.0 mA IOL = 0.1 mA IOL = 2.1 mA For VFBGA package For TSOP I package GND < VI < VCC GND < VO < VCC, Output disabled f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels CE1 > VCC – 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2V, VIN < 0.2 V) f = fmax (address and data only), f = 0 (OE, and WE), VCC = VCC (max) CE1 > VCC – 0.2V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC (max) 45 ns (Industrial/Auto-A) Unit Min Typ[8] Max 2.0 – – V 2.4 – – V – – 0.4 V – – 0.4 V 1.8 – VCC + 0.3 V V 2.2 – VCC + 0.3 V V –0.3 – 0.6 V –0.3 – 0.8 V –0.3 – 0.7[9] V –1 – +1 μA –1 – +1 μA – 25 30 mA – 2.2 4.0 mA – 1.5 12 μA – 1.5 12 μA Capacitance Parameter[11] Description Input capacitance CIN Output capacitance COUT Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 5. VIL(min) = –2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V. This is applicable to TSOP I package only. 10. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05446 Rev. *I Page 4 of 16 [+] Feedback CY62167EV30 MoBL® Thermal Resistance Parameter[12] Description Test Conditions VFBGA (6 x 8 x 1mm) TSOP I Unit ΘJA Thermal resistance Still air, soldered on a 3 × 4.5 inch, (Junction to ambient) two-layer printed circuit board 55 60 °C/W ΘJC Thermal resistance (Junction to case) 16 4.3 °C/W Figure 3. AC Test Loads and Waveforms R1 VCC OUTPUT VCC GND 30 pF INCLUDING JIG AND SCOPE R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 2.2 V to 2.7 V 2.7 V to 3.6 V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Note 12. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05446 Rev. *I Page 5 of 16 [+] Feedback CY62167EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for data retention ICCDR[14] Data retention current 1.5 – – V 48-pin TSOP I – – 8 μA Other packages – – 10 μA – – 10 μA Chip deselect to data retention time 0 – – – Operation recovery time 45 – – ns VCC = 1.5 V to 3.0 V, CE1 > VCC − 0.2 V or Industrial CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC − 0.2 V or VIN < 0.2 V VCC = 1.5 V, CE1 > VCC − 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC − 0.2 V or VIN < 0.2 V tCDR [15] tR[16] Min Typ[13] Max Unit Conditions Industrial Auto-A All packages Figure 4. Data Retention Waveform VCC VCC(min) tCDR DATA RETENTION MODE VDR > 1.5 V VCC(min) tR CE1 or BHE.BLE [17] or CE2 Notes 13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 14. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 15. Tested initially and after any design or process changes that may affect these parameters. 16. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. 17. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05446 Rev. *I Page 6 of 16 [+] Feedback CY62167EV30 MoBL® Switching Characteristics Parameter[18, 19] Description 45 ns (Industrial/Auto-A) Min Max Unit READ CYCLE tRC Read cycle time 45 – ns tAA Address to data valid – 45 ns tOHA Data hold from address change 10 – ns tACE CE1 LOW and CE2 HIGH to data valid – 45 ns tDOE OE LOW to data valid – 22 ns [20] 5 – ns OE LOW to LOW Z tLZOE [20, 21] tHZOE OE HIGH to High Z – 18 ns tLZCE CE1 LOW and CE2 HIGH to Low Z[20] 10 – ns – 18 ns Z[20, 21] tHZCE CE1 HIGH and CE2 LOW to High tPU CE1 LOW and CE2 HIGH to power-up 0 – ns tPD CE1 HIGH and CE2 LOW to power-down – 45 ns tDBE BLE / BHE LOW to data valid – 45 ns Z[20] 10 – ns – 18 ns BLE / BHE LOW to Low tLZBE BLE / BHE HIGH to HIGH tHZBE Z[20, 21] [22] WRITE CYCLE tWC Write cycle time 45 – ns tSCE CE1 LOW and CE2 HIGH to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns tBW BLE / BHE LOW to write end 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 18 ns 10 – ns tHZWE tLZWE [20, 21] WE LOW to High Z [20] WE HIGH to Low Z Notes 18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 5. 19. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 20. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 21. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 22. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. Document #: 38-05446 Rev. *I Page 7 of 16 [+] Feedback CY62167EV30 MoBL® Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled)[23, 24] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE Controlled)[24, 25] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 23. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 24. WE is HIGH for read cycle. 25. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05446 Rev. *I Page 8 of 16 [+] Feedback CY62167EV30 MoBL® Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE Controlled)[26, 27, 28] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA I/O NOTE 29 VALID DATA tHZOE Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled)[26, 28] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE DATA I/O tSD NOTE 29 tHD VALID DATA tHZOE Notes 26. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write 27. Data I/O is high impedance if OE = VIH. 28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 29. During this period the I/Os are in output state. Do not apply input signals. Document #: 38-05446 Rev. *I Page 9 of 16 [+] Feedback CY62167EV30 MoBL® Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE controlled, OE LOW)[30] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA I/O NOTE 31 tHD VALID DATA tLZWE tHZWE Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[30] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 31 tHD VALID DATA Notes 30. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 31. During this period the I/Os are in output state. Do not apply input signals. Document #: 38-05446 Rev. *I Page 10 of 16 [+] Feedback CY62167EV30 MoBL® Truth Table CE1 CE2 WE OE Mode Power H X[32] X X X X High Z Deselect/Power-down Standby (ISB) X[32] BHE BLE Inputs/Outputs L X X X X High Z Deselect/Power-down Standby (ISB) [32] X X H H High Z Deselect/Power-down Standby (ISB) L H H L L L Data Out (I/O0–I/O15) Read Active (ICC) L H H L H L Data Out (I/O0–I/O7); High Z (I/O8–I/O15) Read Active (ICC) L H H L L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H H L H High Z Output disabled Active (ICC) L H H H H L High Z Output disabled Active (ICC) L H H H L L High Z Output disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In (I/O0–I/O7); High Z (I/O8–I/O15) Write Active (ICC) L H L X L H High Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) [32] X X Note 32. The ‘X’ (Don’t care) state for the chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted Document #: 38-05446 Rev. *I Page 11 of 16 [+] Feedback CY62167EV30 MoBL® Ordering Information Speed (ns) 45 Package Diagram Ordering Code Package Type CY62167EV30LL-45BVI 51-85150 48-ball VFBGA (6 × 8 × 1 mm) CY62167EV30LL-45BVXI 51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free) CY62167EV30LL-45ZXI 51-85183 48-pin TSOP I (Pb-free) CY62167EV30LL-45BVXA 51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free) CY62167EV30LL-45ZXA 51-85183 48-pin TSOP I (Pb-free) Operating Range Industrial Automotive-A Ordering Code Definition CY 621 6 7 E V30 LL 45 XXX X Temperature grades: I = Industrial A = Auto-A Package type: BVX: VFBGA (Pb-free) ZSX: TSOP II (Pb-free) Speed grade Low power Voltage range = 3 V typical E = Process Technology 90 nm Bus Width = x16 Density = 16 Mbit 621 = MoBL SRAM family Company ID: CY = Cypress Document #: 38-05446 Rev. *I Page 12 of 16 [+] Feedback CY62167EV30 MoBL® Package Diagrams Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150-*E Document #: 38-05446 Rev. *I Page 13 of 16 [+] Feedback CY62167EV30 MoBL® Figure 12. 48-Pin TSOP I (12 mm × 18.4 mm × 1.0 mm), 51-85183 51-85183-*B Acronyms Acronym Description BHE byte high enable BLE byte low enable CMOS complementary metal oxide semiconductor CE chip enable I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package VFBGA very fine ball grid array WE write enable Document #: 38-05446 Rev. *I Page 14 of 16 [+] Feedback CY62167EV30 MoBL® Document History Page Document Title: CY62167EV30 MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM Document Number: 38-05446 Orig. of Change Submission Date 202600 AJU 01/23/2004 463674 NXR See ECN Converted from Advance Information to Preliminary Removed ‘L’ bin and 35 ns speed bin from product offering Modified Data sheet to include x8 configurability. Changed ball E3 in FBGA pinout from DNU to NC Changed the ISB2(Typ) value from 1.3 μA to 1.5 μA Changed the ICC(Max) value from 40 mA to 25 mA Changed Vcc stabilization time in footnote #9 from 100 µs to 200 µs Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns Changed tLZOE from 3 ns to 5 ns. Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns Changed tSCE, tAW, and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information. Updated the Ordering Information table Rev. ECN No. ** *A Description of Change New Data Sheet *B 469169 NSI See ECN Minor Change: Moved to external web *C 1130323 VKN See ECN Converted from preliminary to final Changed ICC max spec from 2.8 mA to 4.0 mA for f=1MHz Changed ICC typ spec from 22 mA to 25 mA for f=fmax Changed ICC max spec from 25 mA to 30 mA for f=fmax Added VIL spec for TSOP I package and footnote# 9 Added footnote# 10 related to ISB2 and ICCDR Changed ISB1 and ISB2 spec from 8.5 μA to 12 μA Changed ICCDR spec from 8 μA to 10 μA Added footnote# 15 related to AC timing parameters *D 1323984 VKN/AESA See ECN Modified ICCDR spec for TSOP I package Added 48-Ball VFBGA (6 x 7 x 1mm) package Added footnote# 1 related to VFBGA (6 x 7 x 1mm) package Updated Ordering Information table *E 2678799 VKN/PYRS 03/25/2009 Added Automotive-A information *F 2720234 VKN/AESA 06/17/2009 Included -45BVXA part in the Ordering information table *G 2880574 VKN 02/18/2010 Modified ICCDR spec from 8 μA to 10 μA for Auto-A grade. Added Contents. Updated all package diagrams. Updated links in Sales, Solutions, and Legal Information. *H 2934396 VKN 06/03/10 *I 3006301 RAME 08/12/2010 Document #: 38-05446 Rev. *I Added footnote #25 related to chip enable. Updated template. Included BHE and BLE in ISB1, ISB2, and ICCDR test conditions to reflect Byte power down feature. Removed 48-Ball VFBGA (6 x 7 x 1 mm) package related information. Added Acronyms and Ordering code definition. Format updates to match template. Page 15 of 16 [+] Feedback CY62167EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05446 Rev. *I Revised August 13, 2010 Page 16 of 16 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback