SECOS SPWNE555D

SPWNE555D
Single Timer
Elektronische Bauelemente
RoHS Compliant Product
DIP-8
Description
D
The SPWNE555D is a highly stable timer integrated circuit. It
can be operated in Astable mode and Monostable mode. With
monostable operation, the time delay is controlled by one
external and one capacitor. With a stable operation, the frequency
and duty cycle are accurately controlled with two external resistors
and one capacitor.
E
GAUGE PLANE
c
A
Features
SEATING PLANE
Z
SECTION Z - Z
* Timing From uSec to Hours
* Time Delay Generation
* Pulse Generation
* Precistion Timing
e
b
* High Current Driver Capability (=200mA)
Applications
b
Z
L
* Turn Off Time Less Than 2uSec
* Adjustable Duty Cycle
REF.
A
A1
A2
b
b1
b2
b3
c
Millimeter
Min.
Max.
0.381
2.921
0.356
0.356
1.143
0.762
0.203
0.5334
4.953
0.559
0.508
1.778
1.143
0.356
REF.
c1
D
E
E1
e
HE
L
Millimeter
Min.
Max.
0.203
0.279
9.017
10.16
6.096
7.112
7.620
8.255
2.540 BSC
10.92
2.921
3.810
Block Diagram & Pin Configuration
rogrammed by
pacitor CT to ground .Operation 500kHz
nts up to
This is the reference output .It provides charging current for capacitor CT
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01-Jun-2002 Rev. A
Any changing of specification will not be informed individual
Page 1 of 5
SPWNE555D
Elektronische Bauelemente
Single Timer
:
Absolute Maximum Ratings (Ta=25 )
Parameter
Supply Voltage
Output Current
Power Dissipation
Lead Temperature (10sec)
Operating Temperature
Storage Temperature
Symbol
VCC
IO
Pd
Tlead
Topr
Tstg
Electrical Characteristics
Parameter
Supply Voltage
Supply Current (Note 1)
Timing Error(monostable)
Initial Accurary (Note 1)
Drift with Temperature
Drift with Supply Voltage
Timing Error(astable)
Initial Accurary (Note 1)
Drift with Temperature
Drift with Supply Voltage
Control Voltage
Threshold Voltage
Threshold Current (Note 3)
Trigger Voltage
Trigger Current
Reset Voltage
Reset Current
Low Output Voltage
High Output Voltage
Reset Time of Output
Fall Time of Output
Discharge leakage Current
(TA=25
Symbol
VCC
ICC
Value
16
200
600
300
0 ~ 70
-65 ~ 150
Unit
V
mA
mW
V CC=5 ~ 15V)
Test Conditions
VCC=5V, RL=
VCC=15V, RL=
ACCUR RA=1k to 100k
t/ T C=0.1 F
t/ VCC
ACCUR RA=1k to 100k
t/ T C=0.1 F
t/ VCC
VCC=15V
VC
VCC=5V
VCC=15V
VTH
VCC=5V
ITH
VCC=5V
nd resistor set
Vtr
VCC=15V
Itr
Vtr=0
Vrst
Irst
VCC=15V, Isink=10mA
VOL
VCC=15V, Isink=50mA
VCC=5V, Isink=5mA
VCC=15V, Isink=200mA
VOH VCC=15V, Isink=100mA
VCC=5V, Isink=100mA
tR
tF
ILKG
Min
4.5
-
Typ.
3
10
Max.
16
6
15
Unit
V
mA
mA
-
1.0
50
0.1
-
%
ppm/
%/V
2.25
%
ppm/
150
0.3
%/V
9.0
10.0 11.0
V
2.6
3.33
4.0
V
9.2
10.0 10.8
V
3.1
3.33
3.55
this pin (with a 5.0uF capacitor at V
Pin 2)
on time- of the0.1
circuit is0.25
affected by
A the
1.1
1.67
2.2
V
low frequency rolloff and input impedance. The
4.5
5
5.6
V
2.0
A
0.4
0.7
1.0
V
0.1
0.4
mA
0.06 0.25
V
0.3
0.75
0.05 0.35
12.5
V
12.75 13.3
15
2.75
3.3
5
100
nSec
100
nSec
20
100
nA
Note1: Supply current when output is high typically 1mA less at VCC=5V.
Note2: Tested at VCC=5V and VCC=15V.
Note3: This will determine the maximum value of RA+RB for 15V operation, the maximum total is R=20M , and for 5V operation the
maximum total is R=6.7M .
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
Any changing of specification will not be informed individual
Page 2 of 5
SPWNE555D
Elektronische Bauelemente
Single Timer
Characteristics Curve
(UVLO)
VCC = 15 V
ht tp://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
Any changing of specification will not be informed individual
Page 3 of 5
SPWNE555D
Elektronische Bauelemente
vs. Output Power
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
Single Timer
Load
Any changing of specification will not be informed individual
Page 4 of 5
SPWNE555D
Elektronische Bauelemente
Single Timer
Application Circuit
FLIP-FLOP
Application Notes
The application circuit shows astable mode configuration.
Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1
of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of SPWNE555D,
one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is connected to Pin 6. As
soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage
of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at
voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop
circuit is set output high.
That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is
low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is
0.693RB*C1.
In
1
VccVcc
Vcc
3 Vcc
Vcc
Vcc
Vcc- 2 Vcc
Vcc
Vcc
13
=0.693
T1=0.693*(RA+RB)*C1
Thus the total period time T is given by
T2=0.693*RB*C1
T=T1+T2=0.693(RA+2RB)*C1.
Then the frequency of astable mode is given by
f=
1
T
=
1.44
1.44
(RA+2RB)*C1
(RA+2RB)*C1
The duty cycle is given by
D.C. =
T2
T
=
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
RB
RA+2RB
RA+2RB
.
Any changing of specification will not be informed individual
Page 5 of 5