ISSUED DATE :2005/08/10 REVISED DATE :2006/05/15C GSCNE555 SINGLE TIMER Description The GSCNE555 is a highly stable timer integrated circuit. It can be operated in Astable mode and Monostable mode. With monostable operation, the time delay is controlled by one external and one capacitor. With a stable operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor. Features High current driver capability (=200mA) Adjustable duty cycle Timing form Sec to Hours Turn off time less than 2 Sec Applications Precision timing Pulse generation Time delay generation Package Dimensions REF. A B C D E F Millimeter Min. Max. 5.80 4.80 3.80 0° 0.40 0.19 6.20 5.00 4.00 8° 0.90 0.25 REF. M H L J K G Millimeter Min. Max. 0.10 0.25 0.35 0.49 1.35 1.75 0.375 REF. 45° 1.27 TYP. Block Diagram and Simplified Application & Pin Configuration GSCNE555 Page: 1/5 ISSUED DATE :2005/08/10 REVISED DATE :2006/05/15C Absolute Maximum Ratings (Ta=25 ) Parameter Supply Voltage Output Current Power Dissipation Lead Temperature Operating Temperature Storage Temperature Symbol VCC IO Pd Tlead Topr Tstg Electrical Characteristics Parameter Supply Voltage Supply Current (Note 1) Timing Error(monostable) Initial Accurary (Note 1) Drift with Temperature Drift with Supply Voltage Timing Error(astable) Initial Accurary (Note 1) Drift with Temperature Drift with Supply Voltage Control Voltage Threshold Voltage Threshold Current (Note 3) Trigger Voltage Trigger Current Reset Voltage Reset Current Low Output Voltage High Output Voltage Reset Time of Output Fall Time of Output Discharge leakage Current (TA=25 Symbol VCC ICC Value 16 200 440 300 0 ~ 70 -65 ~ 150 Unit V mA mW VCC=5 ~ 15V) Test Conditions VCC=5V, RL= VCC=15V, RL= ACCUR RA=1k to 100k t/ T C=0.1 F t/ VCC ACCUR RA=1k to 100k t/ T C=0.1 F t/ VCC VCC=15V VC VCC=5V VCC=15V VTH VCC=5V ITH VCC=5V Vtr VCC=15V Itr Vtr=0 Vrst Irst VCC=15V, Isink=10mA VOL VCC=15V, Isink=50mA VCC=5V, Isink=5mA VCC=15V, Isource=200mA VOH VCC=15V, Isource=100mA VCC=5V, Isource=100mA tR tF ILKG Min 4.5 - Typ 3 10 Max 16 6 15 - 1.0 50 0.1 - 9.0 2.6 9.2 3.1 1.1 4.5 0.4 12.75 2.75 - 2.25 150 0.3 10.0 3.33 10.0 3.33 0.1 1.67 5 0.7 0.1 0.06 0.3 0.05 12.5 13.3 3.3 100 100 20 11.0 4.0 10.8 3.55 0.25 2.2 5.6 2.0 1.0 0.4 0.25 0.75 0.35 15 5 100 Unit V mA mA % ppm/ %/V % ppm/ %/V V V V V A V V A V mA V V nSec nSec nA Note1: Supply current when output is high typically 1mA less at VCC=5V. Note2: Tested at VCC=5V and VCC=15V. Note3: This will determine the maximum value of RA+RB for 15V operation, the maximum total is R=20M , and for 5V operation the maximum total is R=6.7M . GSCNE555 Page: 2/5 ISSUED DATE :2005/08/10 REVISED DATE :2006/05/15C Characteristics Curve VCC = 15 V GSCNE555 Page: 3/5 ISSUED DATE :2005/08/10 REVISED DATE :2006/05/15C GSCNE555 Page: 4/5 ISSUED DATE :2005/08/10 REVISED DATE :2006/05/15C Application Circuit FLIP-FLOP GSCNE555 Application Notes The application circuit shows astable mode configuration. Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1 of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of GSCNE555, one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is connected to Pin 6. As soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop circuit is set output high. That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is 0.693RB*C1. Vcc- In 1 Vcc 3 =0.693 Vcc- 2 Vcc 13 T1=0.693*(RA+RB)*C1 Thus the total period time T is given by T2=0.693*RB*C1 T=T1+T2=0.693(RA+2RB)*C1 Then the frequency of astable mode is given by f= 1 T = 1.44 (RA+2RB)*C1 The duty cycle is given by D.C. = T2 T = RB RA+2RB Important Notice: All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM. GTM reserves the right to make changes to its products without notice. GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems. GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. Head Office And Factory: Taiwan: No. 17-1 Tatung Rd. Fu Kou Hsin-Chu Industrial Park, Hsin-Chu, Taiwan, R. O. C. TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785 China: (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165 GSCNE555 Page: 5/5