512K x 8 SRAM MODULE SYS8512FKX-70/85/10/12 Issue 5.0: November 1999 Features Description The SYS8512FKX is plastic 4M Static RAM Module housed in a standard 32 pin Dual-In-Line package organised as 512K x 8. The module utilises fast SRAMs housed in TSOP packages, and uses double sided surface mount techniques, buried decoder and dual board construction to achieve a very high density module. The module has Chip Select, Write Enable and Output Enable control inputs; the Output Enable pin allows faster access times than address access during a Read Cycle. • • Low seated height 32 Pin 0.6" Dual-In-Line package with JEDEC compatible pinout. 5 Volt Supply ± 10%. Low Power Dissipation: Average (min cycle) 605mW (maximum). Standby (CMOS) 44mW (maximum). Completely Static Operation. Equal Access and Cycle Times. All Inputs and Outputs Directly TTL Compatible. On-board Supply Decoupling Capacitors. • • • • • • WE OE 128K x 8 SRAM CS 128K x 8 SRAM CS DECODER 128K x 8 SRAM CS A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PACKAGE TOP VIEW AO - A 16 D0 - D7 CS Access Times of 70/85/100/120 ns. Pin Definition Block Diagram 128K x 8 SRAM • 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin Functions A17 CS A18 Address Inputs Data Input/Output Chip Select Input Read/Write Input Output Enable Input Power (+5V) Ground A0 - A18 D0 - D7 CS WE OE VCC GND VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS D7 D6 D5 D4 D3 ISSUE 5.0 November 1999 SYS8512FKX-70/85/10/12 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Symbol min typ max unit Voltage on any pin relative to VSS VT -0.3V - +7 V Power Dissipation PT - 1 - Storage Temperature TSTG -55 - W o +150 C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) Vt can be -3.5V pulse of less than 20ns. Recommended Operating Conditions Parameter Symbol min typ max unit Supply Voltage VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 - Vcc + 0.3 V Input Low Voltage VIL -0.3 - 0.8 Operating Temperature TA TAI 0 -40 ILI1 ILO 0V - VIN - VCC Operating Supply Current I CC Output Voltage C (I) min typ(2) max Unit CS = VIH, VI/O = GND to VCC - - ±8 ±8 µA µA CS = VIL ,II/O = 0mA, VIL - VIN - VCC-2.1V - 16 45 mA I CC1 Min. Cycle, CS = VIL, VIN = VIL/VCC-2.1V - 70 110 mA I CC2 Min. Cycle, CS - 0.2V, VIN = 0.2V/VCC-0.2V - 24 40 mA ISB CS,A17-A18 = VCC-2.1V, VIL - VIN - VCC-2.1V - 5 12 mA CMOS levels ISB1 CS,A17-A18 = VCC-0.2V, 0.2 - VIN - VCC-0.2V - 0.2 8 mA -L Part ISB2 As above - 10 500 µA - - 0.4 V 2.4 - - V TTL levels CMOS levels Standby Supply Current C o 85 Symbol Test Condition I/P Leakage Current A0~A16, OE Output Leakage Current D0~D7 Average Supply Current - 70 TA 0 to 70OC DC Electrical Characteristics (VCC=5V±10%) Parameter - V o TTL levels VOL IOL = 2.1mA VOH IOH = -1.0mA Typical values are at VCC=5.0V,TA=25oC and specified loading. 2 SYS8512FKX-70/85/10/12 ISSUE 5.0 November 1999 Capacitance (VCC=5V±10%,TA=25oC) Parameter Note: Capacitance calculated, not measured. Symbol Input Capacitance (CS, A17, A18) I/P Capacitance (other) I/O Capacitance Test Condition max Unit VIN = 0V VIN = 0V VI/O = 0V 10 40 40 pF pF pF CIN1 CIN2 CI/O Operation Truth Table CS OE WE DATA PINS SUPPLY CURRENT MODE H X X High Impedance ISB1 , ISB2 Standby L L H Data Out ICC1 , ICC2 Read L L L Data In ICC1 , ICC2 Write L H L Data In ICC1 , ICC2 Write Notes : H = VIH : L =VIL : X = VIH or VIL Low Vcc Data Retention Characteristics - L Version Only -L Part Parameter Symbol Test Condition min typ(1) VCC for Data Retention VDR 2.0 - - Data Retention Current CS - VCC-0.2V max VCC = 3.0V, CS = VCC-0.2V I CCDR2 TOP = 0C to 70C - 9 230 µA I CCDR3 TOP = TAI - - 310 µA Data Retention Time t CDR See Retention Waveform 0 - - 0 - - ns Operation Recovery Time tR See Retention Waveform 5 - - 0 - - ms Chip Deselect to Notes (1) Typical figures are measured at 25°C. (2) This parameter is guaranteed not tested. AC Test Conditions Output Load * Input pulse levels: 0V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * VCC=5V±10% 3 ISSUE 5.0 November 1999 SYS8512FKX-70/85/10/12 AC OPERATING CONDITIONS Read Cycle -70 Parameter Symbol min Read Cycle Time t RC 70 Address Access Time tAA Chip Select Access Time -85 max -10 -12 min max min max min max Unit - 85 - 100 - 120 - ns - 70 - 85 - 100 - 120 ns tACS - 70 - 85 - 100 - 120 ns Output Enable to Output Valid tOE - 50 - 55 - 60 - 70 ns Output Hold from Address Change t OH 10 - 10 - 10 - 10 - ns Chip Selection to Output in Low Z tCLZ 10 - 10 - 10 - 10 - ns Output Enable to Output in Low Z tOLZ 5 - 5 - 5 - 5 - ns Chip Deselection to O/P in High Z t CHZ 0 25 0 30 0 35 0 45 ns Output Disable to Output in High Z t OHZ 0 25 0 30 0 35 0 45 ns Notes. (1) tHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels.These parameters are sampled and not 100% tested. Write Cycle -70 Parameter Sym min Write Cycle Time t WC 70 Chip Selection to End of Write t CW Address Valid to End of Write -85 -12 min max min max - 85 - 100 - 120 - ns 60 - 80 - 90 - 100 - ns t AW 60 - 80 - 90 - 100 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width t WP 55 - 65 - 75 - 85 - ns Write Recovery Time t WR 5 - 5 - 10 - 10 - ns Write to Output in High Z tWHZ 0 25 0 30 0 35 0 40 ns Data to Write Time Overlap t DW 30 - 35 - 40 - 45 - ns Data Hold from Write Time t DH 0 - 0 - 0 - 0 - ns 5 - 5 - 5 - 5 - ns Output active from end of write tOW (11) (10) max -10 4 min max Unit SYS8512FKX-70/85/10/12 ISSUE 5.0 November 1999 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE CS t OH t OLZ t ACS Don't care. t OHZ t CLZ Dout Data Valid t CHZ Notes (1) WE is High for Read Cycle. (2) tHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels.These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform tWC Address t WR (4) OE CS t AS (3) t AW t CW (2) (6) Don't Care WE t OHZ (5) t WP (1) tOW High-Z Dout tDW Din High-Z 5 tDH ISSUE 5.0 November 1999 SYS8512FKX-70/85/10/12 Write Cycle No.2 Timing Waveform tWC Address t AS (3) t WR (4) t CW (2) CS t AW tWP (1) WE tOH tWHZ(5) t OW (8) (7) Don't Care High-Z Dout t DW t DH High-Z Din AC Characteristics Notes (1) A write occurs during the overlap (tWP) of a low CS and a low WE. (2) tCW is measured from the earlier of CS or WE going high to the end of write cycle. (3) tAS is measured from the address valid to the beginning of write. (4) tWR is measured from the earliest of CS or WE going high to the end of write. (5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high impedance state. (7) DOUT is in the same phase as written data of this write cycle. (8) DOUT is the read data of next address. (9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be applied to I/O pins. (10) This parameter is sampled and not 100% tested. (11) tWHZ is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested. Data Retention Waveform Vcc DATA RETENTION MODE 4.5V 4.5V t CDR tR 2.2V 2.2V V DR CS CS > Vcc -0.2V 0V 6 SYS8512FKX-70/85/10/12 ISSUE 5.0 November 1999 Package Information 42.50 max. 15.92 max. 15.24 typ. 2.54 typ. min. 3.50 +/-0.50 6.0 max. Dimensions in mm Ordering Information SYS8512FKXLI-10 Speed 70 85 10 12 = 70 ns = 85 ns = 100 ns = 120 ns Temperature Range Blank = Commercial Temperature I = Industrial Temperature Power Consumption Blank = Standard Part L = Low Power Part Package FKX = Plastic 32 pin DIL Organization 8512 = 512K x 8 Memory Type SYS = Static RAM Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose. Our Products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express approval of a company director. 7