128K x 32 SRAM MODULE PUMA 68S4000/A - 020/025/35/45 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel.+44 (0191) 2930500 Fax.+44 (0191) 2590997 Description The PUMA68S4000/A is a 4Mbit CMOS High Speed Static RAM organised as 128K x 32 in a JEDEC 68 pin surface mount PLCC, available with access times of 20, 25, 35, and 45ns. The output width is user configurable as 8 , 16 or 32 bits using four Chip Selects (CS1~4). The device features multiple ground pins for maximum noise immunity and TTL compatible inputs and outputs. The PUMA 68S4000/A offers a dramatic space saving advantage over four standard 128Kx8 devices. Issue 4.5 : April 2001 Features • Fast Access Times of 20 ,25, 35 and 45 ns. • JEDEC 68 'J' leaded plastic surface mount Substrate • Industrial or Military Grade. • Upgradeable footprint. • User Configurable as 8 / 16 / 32 bit wide output. • Operating Power Low Power Standby (32-BIT) (TTL) 4.00 W (Max) 1.43 W (Max) • Fully Static operation. • Multiple ground pins for maximum noise immunity. 128Kx8 SRAM 128Kx8 SRAM 128Kx8 SRAM CS1 CS2 CS3 CS4 D0-7 D8-15 D16-23 D24-31 128Kx8 SRAM VCC 2 A9 3 A10 4 WE A6 5 CS4 6 CS3 GND 7 8 A4 9 A5 A0-A16 OE WE A2 (PUMA 68 S4000A page 2) A3 (PUMA 68 S4000A page 2) A1 Pin Definition NC A0 Block Diagram A7 A8 • Single 5V±10% Power supply. 1 68 67 66 65 64 63 62 61 D0 10 60 D16 D1 11 59 D17 D2 12 58 D18 D3 13 57 D19 D4 14 56 D20 D5 15 55 D21 D6 16 54 D22 D7 17 53 D23 GND 18 52 GND D8 D9 19 FROM 51 D24 20 50 D25 D10 ABOVE 21 49 D11 22 48 D26 D27 PUMA 68S4000 VIEW D12 23 47 D28 D13 24 46 D29 D14 25 45 D30 D15 26 44 D31 Address Inputs Data Input/Output Chip Select Write Enable Output Enable No Connect Power (+5V) Ground NC NC GND NC NC NC NC CS2 OE CS1 A15 A16 A14 A13 A12 Pin Functions A11 VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A0 - A16 D0 - D31 CS1~4 WE1~4 OE NC VCC GND Package Details Plastic 68 J-Leaded JEDEC PLCC PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 PUMA 68 S4000A Pinout and Block Diagram. A0 ~A16 /OE /WE4 /WE3 /WE2 /WE1 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM /CS1 /CS2 /CS3 /CS4 NC A0 A1 A2 A3 A4 A5 /CS3 GND /CS4 /WE1 A6 A7 A8 A9 A10 VCC D0~7 D8~15 D16~23 D24~31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 16 17 PUMA 68S4000A VIEW 18 19 20 21 55 54 53 52 FROM ABOVE 51 50 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC A11 A12 A13 A14 A15 A16 /CS1 /OE /CS2 NC /WE2 /WE3 /WE4 NC GND NC D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 D12 D13 D14 D15 2 D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Symbol (2) T Voltage on any pin relative to VSS Power Dissipation Storage Temperature V PT TSTG Min Typ Max Unit -0.3 -65 - 7.0 4.0 150 V W o C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature (Commercial) (Industrial) (Military) Symbol Min Typ Max VCC VIH VIL TA TAI TAM 4.5 2.2 -0.3 0 -40 -55 5.0 - 5.5 VCC+0.3 0.8 70 85 125 Unit V V V o C o C (Suffix I) o C (Suffix M) DC Electrical Characteristics (VCC=5V±10%, TA = -55oC to +125oC) Parameter Symbol Test Condition Input Leakage Current Output Leakage Current ILI1 ILO VIN=0V to VCC VI/O=0V to VCC Min Typ max Unit -20 -40 - 20 40 µA µA Operating Supply Current(2) 32 bit ICC32 16 bit ICC16 8 bit ICC8 CS(1)=VIL, II/O=0mA, f=fmax As above. As above. - - 840 540 400 mA mA mA Standby Supply Current (TTL) ISB CS(1)=VIH, f=fmax, VIN=VILor VIH - - 260 mA Output Voltage Low Output Voltage High VOL VOH 2.4 - 0.4 - V V IOL = 8.0mA,VCC=Min IOH = -4.0mA,VCC=Min Notes: (1) CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) At f=fmax address and data inputs are cycling at max frequency. 3 PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 Capacitance (VCC=5V±10%,TA=25oC) Note: Capacitance calculated, not measured. Parameter Symbol Input Capacitance Address,OE,WE Output Capacitance 8-bit mode (worst case) Test Condition CIN1 CI/O min typ max Unit - - 34 42 pF pF VIN =0V VI/O=0V AC Test Conditions Output Load 166Ω I/O Pin * Input pulse levels: 0V to 3.0V 1.76V * Input rise and fall times: 3ns 30pF * Input and Output timing reference levels: 1.5V * Output load: see diagram * VCC=5V±10% Operation Truth Table CS1 CS2 CS3 CS4 L H H H L H L L H H H L H L X H H L H H L H L H L H H L H L X H H H L H H L L H H L H H L L X H H H H L H L L H H H L H L L X H OE WE X X X X X X X L L L L L L L H X L L L L L L L H H H H H H H H X SUPPLY CURRENT ICC8 ICC8 ICC8 ICC8 ICC16 ICC16 ICC32 ICC8 ICC8 ICC8 ICC8 ICC16 ICC16 ICC32 ICC32/ICC16/ICC8 ISB,ISB1 Notes : H = VIH : L =VIL : X = VIH or VIL 4 MODE Write D0~7 Write D8~15 Write D16~23 Write D24~31 Write D0~15 Write D16~31 Write D0~31 Read D0~7 Read D8~15 Read D16~23 Read D24~31 Read D0~15 Read D16~31 Read D0~31 D0~31 High-Z D0~31 Standby PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 AC OPERATING CONDITIONS Read Cycle -020 Parameter -025 -35 -45 Symbol min max min max min max min max Unit Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z tRC tAA tACS tOE tOH tCLZ tOLZ Chip Deselection to O/P in High Z Output Disable to Output in High Z tCHZ tOHZ 20 3 3 0 0 0 20 20 10 9 8 25 3 3 0 0 0 25 25 12 10 10 35 3 3 0 0 0 35 35 15 12 12 45 3 3 0 0 0 45 45 17 15 15 ns ns ns ns ns ns ns ns ns Write Cycle -020 Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output active from end of write Symbol tWC tCW tAW tAS tWP tWR tWHZ tDW tDH tOW -025 -35 -45 min max min max min max min max Unit 20 15 15 0 12 0 0 10 0 3 10 - 25 20 20 0 15 0 0 12 0 3 12 - 35 25 25 0 17 0 0 15 0 3 15 - 45 35 35 0 20 0 0 15 0 3 15 - ns ns ns ns ns ns ns ns ns ns 5 PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OH t OLZ CS1~4 t ACS Don’t care. t OHZ (3) t CLZ (4,5) Dout Data Valid t CHZ (3,4,5) AC Read Characteristics Notes (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module and from module to module. (5) These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform(1,4) tWC Address t WR(7) OE t AS(6) t AW t CW CS1~4 Don’t Care WE t OHZ(3,9) t OW t WP(2) High-Z Dout t DW Din High-Z t DH Data Valid 6 (8) PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 Write Cycle No.2 Timing Waveform (1,5) tWC Address t AS(6) t WR(7) t CW CS1~4 t AW t WP(2) WE tOH t WHZ(3,9) t OW High-Z Dout t DW Din (8) (4) Don’t Care t DH High-Z Data Valid AC Write Characteristics Notes (1) All write cycle timing is referenced from the last valid address to the first transition address. (2) All writes occur during the overlap of CS1~4 and WE low. (3) If OE, CS1~4, and WE are in the Read mode during this period, the I/O pins are low impedance state. Inputs of opposite phase to the output must not be applied because bus contention can occur. (4) Dout is the Read data of the new address. (5) OE is continuously low. (6) Address is valid prior to or coincident with CS1~4 and WE low, too avoid inadvertant writes. (7) CS1~4 or WE must be high during address transitions. (8) When CS1~4 are low : I/O pins are in the output state. Input signals of opposite phase leading to the output should not be applied. (9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. 7 PUMA 68S4000/A - 020/025/35/45 Package Information ISSUE 4.5 : April 2001 Dimensions in mm(inches) Plastic 68 Pin JEDEC Surface mount PLCC 25.27 (0.995) sq. 5.08 (0.200) max 25.02 (0.985) sq. 0.10 (0.004) 23.11 (0.910) 0.46 (0.018) typ. 24.13 (0.950) 1.27 (0.050) typ. 0.90 (0.035) typ. Ordering Information PUMA 68S4000/AM - 020 Speed 020 025 35 45 = = = = 20ns 25ns 35ns 45ns Temperature range Blank I M = = = Commercial Temperature Industrial Temperature Military Temperature /WE Option Blank A = = Single/WE /WE1~4 S4000 = 128K x 32 SRAM configurable as 256K x 16 and 512K x 8 PUMA 68 = 68 pin "J" Leaded PLCC Memory Organisation Package Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 8 PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 Visual Inspection Standard All devices inspected to ANSI/J-STD-001B Class 2 standard Moisture Sensitivity Devices are moisture sensitive. Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH). After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220OC) must be : A : Mounted within 72 Hours at factory conditions of <30OC/60% RH OR B : Stored at <20% RH If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking as specified below. If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers OR B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers. Packaging Standard Devices packaged in dry nitrogen, JED-STD-020. Packaged in trays as standard. Tape and reel available for shipment quantities exceeding 200pcs upon request. Soldering Recomendations IR/Convection - Ramp Rate Temp. exceeding 183OC Peak Temperature Time within 5OC of peak Ramp down 6OC/sec max. 150 secs. max. 225OC 20 secs max. 6OC/sec max. Vapour Phase - Ramp up rate Peak Temperature Time within 5OC of peak Ramp down 6OC/sec max. 215 - 219OC 60 secs max. 6OC/sec max. The above conditions must not be exceeded. Note : The above recommendations are based on standard industry practice. Failure to comply with the above recommendations invalidates product warranty. 9