Revised January 2005 MM74HCT14 Hex Inverting Schmitt Trigger General Description Features The MM74HCT14 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability to drive 10 LS-TTL loads. ■ Typical propagation delay: 13 ns The 74HCT logic family is functionally and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. ■ Wide power supply range: 2–6V ■ Low quiescent current: 10 µA maximum ■ Low input current: 1 µA maximum ■ Fanout of 10 LS-TTL loads ■ Typical hysteresis voltage: 0.9V at VCC = 4.5V ■ TTL, LS pin-out and input threshold compatible Ordering Codes: Order Number Package Package Description Number MM74HCT14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HCT14MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HCT14SJ M14D MM74HCT14MTC MM74HCT14N MTC14 N14A Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Schematic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 2005 Fairchild Semiconductor Corporation DS500059 www.fairchildsemi.com MM74HCT14 Hex Inverting Schmitt Trigger September 1983 MM74HCT14 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Supply Voltage (VCC) −0.5 to +7.0V DC Input Voltage (VIN) −1.5 to VCC + 1.5V DC Output Voltage (VOUT) −0.5 to VCC + 0.5V Clamp Diode Current (IIK, IOK) ± 20 mA DC Output Current, per pin (IOUT) ± 25 mA Min Max Units 2 6 V 0 VCC V −40 +85 °C DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) ± 50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. −65°C to +150°C Note 2: Unless otherwise specified all voltages are referenced to ground. Lead Temperature (TL) 260°C (Soldering 10 seconds) DC Electrical Characteristics (Note 3) Symbol VT+ Parameter Positive Going VCC Conditions Minimum Threshold Voltage Maximum VT− Negative Going Minimum Threshold Voltage Maximum VH Hysteresis Voltage Minimum Maximum V OH VOL IIN TA = −40 to 85°C Guaranteed Limits Units 4.5V 1.5 1.2 1.2 V 5.5V 1.7 1.4 1.4 V V 4.5V 1.5 1.9 1.9 5.5V 1.7 2.1 2.1 V 4.5V 0.9 0.5 0.5 V 5.5V 1.0 0.6 0.6 V 4.5V 0.9 1.2 1.2 V 5.5V 1.0 1.4 1.4 V 4.5V 0.6 0.4 0.4 V 5.5V 0.7 0.4 0.4 V 4.5V 0.6 1.4 1.4 V 5.5V 0.7 1.5 1.5 V Minimum HIGH Level VIN = VIL Output Voltage |IOUT| = 20 µA VCC VCC− 0.1 VCC − 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 4.2 3.98 3.84 V |IOUT| = 4.8 mA, VCC = 5.5V 5.2 4.98 4.98 V Maximum LOW Level VIN = VIH Voltage |IOUT| = 20 µA Maximum Input Current 0 0.1 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 0.2 0.26 0.33 V |IOUT| = 4.8 mA, VCC = 5.5V 0.2 0.26 0.33 V ±0.1 ±1.0 µA 5.5V 1.0 10 µA 5.5V 2.4 2.4 mA VIN = VCC or GND VIH or VIL ICC TA = 25°C Typ Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA VIN=2.4V or 0.5V (Note 3) Note 3: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH Parameter Conditions Maximum Propagation Delay Typ Guaranteed Limit Units 10 18 ns AC Electrical Characteristics VCC= 5V ± 10%, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter tPHL, tPLH Maximum Propagation Delay tTLH, tTHL Maximum Output Rise and Fall Time CPD Power Dissipation Conditions TA = 25° TA = −40 to 85°C Typ 9 (per gate) Guaranteed Limits Units 20 25 ns 15 19 ns 25 pF Capacitance (Note 4) CIN Maximum Input Capacitance 5 10 10 pF Note 4: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f+ICC. Typical Performance Characteristics Input Threshold, VT+, VT−, vs Power Supply Voltage Propagation Delay vs Power Supply Typical Applications Low Power Oscillator Note: The equations assume t1+t2>>tpd0 +tpd1 3 www.fairchildsemi.com MM74HCT14 AC Electrical Characteristics MM74HCT14 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 MM74HCT14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HCT14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 MM74HCT14 Hex Inverting Schmitt Trigger Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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