Revised February 1999 MM74HC138 3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features ■ Typical propagation delay: 20 ns ■ Wide power supply range: 2V–6V ■ Low quiescent current: 80 µA maximum (74HC Series) ■ Low input current: 1 µA maximum ■ Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HC138M MM74HC138SJ MM74HC138MTC MM74HC138N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for DIP, SOIC, SOP and TSSOP © 1999 Fairchild Semiconductor Corporation DS005120.prf www.fairchildsemi.com MM74HC138 3-to-8 Line Decoder September 1983 MM74HC138 Truth Table Inputs Outputs Enable Select G1 G2 (Note 1) C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X H H H H H H H H L X X X X H H H H H H H H H L L L L L H H H H H H H H L L L H H L H H H H H H H L L H L H H L H H H H H H L L H H H H H L H H H H H L H L L H H H H L H H H H L H L H H H H H H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L H = HIGH Level, L = LOW Level, X = don’t care Note 1: G2 = G2A+G2B Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions − 0.5 to + 7.0V Supply Voltage (VCC ) DC Input Voltage (VIN) − 1.5 to VCC + 1.5V DC Output Voltage (VOUT) − 0.5 to VCC + 0.5V Clamp Diode Current (IIK, IOK) ± 20 mA DC Output Current, per pin (IOUT) ± 25 mA DC VCC or GND Current, per pin Storage Temperature Range (TSTG) 600 mW 500 mW (Note 5) Symbol Conditions VIH VIL VOH Parameter 0 VCC V −40 +85 °C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 3: Unless otherwise specified all voltages are referenced to ground. 260°C DC Electrical Characteristics V DC Input or Output Voltage Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units Input Rise or Fall Times − 65°C to + 150°C S.O. Package only 6 (VIN, VOUT) Power Dissipation (PD) (Note 4) Max 2 Operating Temperature Range (TA) ± 50 mA (ICC) Min Supply Voltage (VCC) Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. VCC TA = 25°C Typ TA = −40 to 85°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 V 6.0V 4.2 4.2 V Maximum LOW Level 2.0V 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 V 6.0V 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage | IOUT | ≤ 20 µA 2.0V 2.0 1.9 1.9 V 4.5V 4.5 4.4 4.4 V 6.0V 6.0 5.9 5.9 V VIN = VIH or VIL VOL |IOUT | ≤ 4.0 mA 4.5V 4.2 3.98 3.84 V | IOUT | ≤ 5.2 mA 6.0V 5.7 5.48 5.34 V Maximum LOW Level VIN = VIH or VIL Output Voltage | IOUT | ≤ 20 µA 2.0V 0 0.1 0.1 V 4.5V 0 0.1 0.1 V 6.0V 0 0.1 0.1 V | IOUT | ≤ 4.0 mA 4.5V 0.2 0.26 0.33 V | IOUT | ≤ 5.2 mA 6.0V 0.2 0.26 0.33 V VIN = VCC or GND 6.0V ±0.1 ±1.0 µA Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 µA Supply Current IOUT = 0 µA VIN = VIH or VIL IIN Maximum Input Current ICC Note 5: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC138 Absolute Maximum Ratings(Note 2) (Note 3) MM74HC138 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPLH Parameter Conditions Guaranteed Typ Maximum Propagation Limit Units 18 25 ns 28 35 ns 18 25 ns 23 30 ns 18 25 ns Delay, Binary Select to any Output tPHL Maximum Propagation Delay, Binary Select to any Output tPHL, tPLH Maximum Propagation Delay, G1 to any Output tPHL Maximum Propagation Delay G2A or G2B to Output tPLH Maximum Propagation Delay G2A or G2B to Output AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPLH tPHL tPHL, tPLH tPHL tPLH tTLH, tTHL CIN Parameter VCC Conditions TA= 25°C Typ TA= −40 to 85°C Units Guaranteed Limits Maximum Propagation 2.0V 75 150 189 ns Delay Binary Select to 4.5V 15 30 38 ns any Output LOW-to-HIGH 6.0V 13 26 32 ns Maximum Propagation 2.0V 100 200 252 ns Delay Binary Select to any 4.5V 20 40 50 ns Output HIGH-to-LOW 6.0V 17 34 43 ns Maximum Propagation 2.0V 75 150 189 ns Delay G1 to any 4.5V 15 30 38 ns Output 6.0V 13 26 32 ns Maximum Propagation 2.0V 82 175 221 ns Delay G2A or G2B to 4.5V 28 35 44 ns Output 6.0V 22 30 37 ns Maximum Propagation 2.0V 75 150 189 ns Delay G2A or G2B to 4.5V 15 30 38 ns Output 6.0V 13 26 32 ns Output Rise and 2.0V 30 75 95 ns Fall Time 4.5V 8 15 19 ns 6.0V 7 13 16 ns 3 10 10 pF Maximum Input Capacitance CPD Power Dissipation (Note 6) 75 Capacitance Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC. www.fairchildsemi.com 4 pF MM74HC138 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com MM74HC138 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC138 3-to-8 Line Decoder Physical Dimensions inches (millimeters) unless otherwise noted (Continued)