Revised May 2005 MM74HC14 Hex Inverting Schmitt Trigger General Description Features The MM74HC14 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability to drive 10 LS-TTL loads. The 74HC logic family is functionally and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. ■ Typical propagation delay: 13 ns ■ Wide power supply range: 2–6V ■ Low quiescent current: 20 PA maximum (74HC Series) ■ Low input current: 1 PA maximum ■ Fanout of 10 LS-TTL loads ■ Typical hysteresis voltage: 0.9V at VCC 4.5V Ordering Code: Order Number Package Package Description Number MM74HC14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC14MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC14SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC14MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC14N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC14N_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 2005 Fairchild Semiconductor Corporation DS005105 www.fairchildsemi.com MM74HC14 Hex Inverting Schmitt Trigger September 1983 MM74HC14 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r25 mA Supply Voltage (VCC) DC Input Voltage (VIN ) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V 55 125 qC (VIN, VOUT) Operating Temperature Range (TA) DC VCC or GND Current, per pin r50 mA 65qC to 150qC (ICC) Storage Temperature Range (TSTG) Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. Lead Temperature (TL) 260 qC (Soldering 10 seconds) DC Electrical Characteristics Symbol VT Parameter Positive Going Conditions Minimum Threshold Voltage Maximum VT Negative Going Minimum Threshold Voltage Maximum VH Hysteresis Voltage Minimum Maximum VOH Minimum HIGH Level VIN Output Voltage |IOUT | VIN VOL ICC 20 PA TA VCC 25qC Typ TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units 2.0V 1.2 1.0 1.0 1.0 V 4.5V 2.7 2.0 2.0 2.0 V 6.0V 3.2 3.0 3.0 3.0 V 2.0V 1.2 1.5 1.5 1.5 V 4.5V 2.7 3.15 3.15 3.15 V 6.0V 3.2 4.2 4.2 4.2 V 2.0V 0.7 0.3 0.3 0.3 V 4.5V 1.8 0.9 0.9 0.9 V 6.0V 2.2 1.2 1.2 1.2 V 2.0V 0.7 1.0 1.0 1.0 V 4.5V 1.8 2.2 2.2 2.2 V 6.0V 2.2 3.0 3.0 3.0 V 2.0V 0.5 0.2 0.2 0.2 V 4.5V 0.9 0.4 0.4 0.4 V 6.0V 1.0 0.5 0.5 0.5 V 2.0V 0.5 1.0 1.0 1.0 V 4.5V 0.9 1.4 1.4 1.4 V 6.0V 1.0 1.5 1.5 1.5 V 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V V VIL |IOUT | 4.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT | 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V 2.0V 0 0.1 0.1 0.1 V Maximum LOW Level VIN Output Voltage |IOUT | VIN IIN VIL (Note 4) VIH 20 PA 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V VIH |IOUT | 4.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT | 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V Maximum Input Current VIN VCC or GND 6.0V r0.1 r1.0 r1.0 PA Maximum Quiescent VIN VCC or GND 6.0V 2.0 20 40 PA Supply Current IOUT 0 PA Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 MM74HC14 AC Electrical Characteristics VCC 5V, TA 25qC, CL Symbol tPHL, tPLH 15 pF, tr tf 6 ns Parameter Conditions Maximum Propagation Delay Typ Guaranteed Limit Units 12 22 ns AC Electrical Characteristics VCC 2.0V to 6.0V, CL Symbol 50 pF, tr Parameter tf 6 ns (unless otherwise specified) Conditions tPHL, tPLH Maximum Propagation Delay tTLH, tTHL Maximum Output Rise and Fall Time VCC Power Dissipation 25qC TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units 2.0V 60 125 156 188 ns 4.5V 13 25 31 38 ns 6.0V 11 21 26 32 ns 2.0V 30 75 95 110 ns 4.5V 8 15 19 22 ns 7 13 16 19 6.0V CPD TA Typ (per gate) 27 ns pF Capacitance (Note 5) CIN Maximum Input Capacitance Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f ICC. 5 10 10 10 pF CPD VCC2 f ICC VCC, and the no load dynamic current consumption, Typical Performance Characteristics Input Threshold, VT, VT, vs Power Supply Voltage Propagation Delay vs Power Supply 3 www.fairchildsemi.com MM74HC14 Typical Applications Low Power Oscillator Note: The equations assume t1 t2 !! tpd0 tpd1 www.fairchildsemi.com 4 MM74HC14 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com MM74HC14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 MM74HC14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com MM74HC14 Hex Inverting Schmitt Trigger Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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