SS6383A(G) 2A DDR Termination Regulator FEATURES DESCRIPTION Source and sink current capability of 2A The SS6383A linear regulator is designed to provide 2A source and sink current while regulating an output voltage to within 20mV. Low output voltage offset, ±20mV High accuracy output voltage at full-load VOUT adjustable by external resistors The SS6383A converts voltage supplies ranging from 1.6V to 6V into an output voltage that is set by two external voltage-divider resistors. It provides an excellent voltage source for active termination schemes for high-speed transmission lines such as those seen in highspeed memory buses. Low external component count Current limit protection Thermal protection SO-8 and TO-252-5 packages APPLICATIONS Mother Boards Graphic Cards DDR Termination Voltage Supply - supports DDR1 (1.25VTT), DDR2 (0.9VTT), and meets JEDEC SSTL-2 and SSTL-3 term. specifications The built-in current-limiting in source and sink mode, together with thermal shutdown, provides maximum protection to the SS6383A against fault conditions. TYPICAL APPLICATION CIRCUIT 1 VIN=2.5V + CIN 470µF VOUT 2 3 VCNTL=3.3V VIN + GND VCNTL VREF SS6383ACE5 CCNTL 47µF 5 4 VOUT R1 100K COUT 220µF R2 C1 100K 100pF + EN SSM7002EN This device is available with Pb-free lead finish (second-level interconnect) as SS6383AGxx 11/07/2004 Rev.2.01 www.SiliconStandard.com 1 of 7 SS6383A(G) ORDERING INFORMATION PIN CONFIGURATION SS6383AXXX XX TO-252-5 Packing TR: Tape and reel Package type CE5: TO-252-5, commercial GE5: TO-252-5, Pb-free, commercial CS: SO-8, commercial GS: SO-8, Pb-free, commercial Example: SS6383AGE5TR in TO-252-5 package, Pb-free lead finish, shipped on tape and reel TOP VIEW 1: VIN 2: GND 3. VCNTL 4. VREF 5: VOUT 1234 5 SO-8 TOP VIEW VIN 1 8 VCNTL GND 2 7 VCNTL VREF 3 6 VCNTL VOUT 4 5 VCNTL ABSOLUTE MAXIMUM RATINGS Supply Voltage -0.4V to 7V Operating Temperature Range -40°C~85°C -65°C ~150°C Storage Temperature Range 260°C Lead Temperature (Solder, 10sec) Thermal Resistance θJC TO-252 SO-8 12.5°C /W 40°C /W Thermal Resistance θJA TO-252 100°C /W (Assumes no ambient airflow, no heatsink) SO-8 160°C /W Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 11/07/2004 Rev.2.01 www.SiliconStandard.com 2 of 7 SS6383A(G) TEST CIRCUIT 1 2.5V VIN VOUT 2 3 3.3V 5 VOUT + GND VREF 4 1.25V COUT 10µF VCNTL SS6383ACE5 ELECTRICAL CHARACTERISTICS (VCNTL=3.3V, VIN=2.5V, VREF=0.5VIN, COUT=10µF, TA=25°C, unless otherwise specified) PARAMETER Input Voltage (DDR1/2) TEST CONDITIONS Keep VCNTL≥VIN during SYMBOL MIN. TYP. VIN 1.6 2.5/1.8 power on and off sequences VCNTL Output Voltage IOUT = 0mA VOUT Output Voltage Offset IOUT = 0mA VOS Load Regulation (DDR1/2) IOUT =0.1mA ~ +2A IOUT =0.1mA ~ -2A Quiescent Current VREF<0.2V, VOUT = OFF Operating Current of VCNTL No load VREF Bias Current UNIT V 3.0 3.3 6 VREF -20 V 20 mV 10 20 10 20 IQ 8 30 µA ICNTL 3 10 mA 1 µA 4.5 A ∆VLOR VREF=1.25V Current Limit MAX. mV 0 IIL 2.2 3 TSD 125 150 °C 30 °C THERMAL PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis 3.3V≤VCNTL≤5V Guaranteed by design SHUTDOWN SPECIFICATIONS Shutdown Threshold Output ON (VREF=0V 1.25V) Output OFF (VREF=1.25V 0V) 0.8 V 0.2 Note 2: VOS is the voltage measurement, which is defined as the difference between VOUT and VREF. Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low ON time. Note 4: Current limit is measured by pulsing a short time. Note 5: To operate the system safely; V CNTL must be always greater than VIN. Note 6: Specifications are guaranteed by Statistical Quality Controls (SQC), and not production tested, within the operating temperature range of -40°C to 85°C. 11/07/2004 Rev.2.01 www.SiliconStandard.com 3 of 7 SS6383A(G) 0.52 VCNTL=3.3V 0.48 VIN=2.5V 0.52 Threshold Voltage (V) Threshold Voltage (V) TYPICAL PERFORMANCE CHARACTERISTICS 0.44 0.40 0.36 0.48 VCNTL=5V VIN=2.5V 0.44 0.40 0.36 0.32 0.32 -20 0 20 40 60 80 Temperature (°C) 100 40 120 20 0 20 40 60 80 100 120 Temperature (°C) Fig. 2 Turn On Threshold vs. Temp. Fig. 1 Turn-On Threshold vs. Temp. 4.0 3.5 3.0 VCNTL=3.3V, VIN=2.5V VCNTL=3.3V VIN=2.5V VREF=1.25V No Load 4 Sourcing Current (A) Output Voltage Offset (mV) 5 4.5 2.5 2.0 1.5 1.0 VOUT=1.25V 3 2 1 0.5 0.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 3 Output Voltage Offset vs. Temp. 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 4 Current-Limit (Sourcing) vs. Temp. 5 Sinking Current (A) VCNTL=3.3V, VIN=2.5V 4 VOUT=1.25V 3 2 1 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 5 Current Limit (Sinking) vs. Temp. 11/07/2004 Rev.2.01 www.SiliconStandard.com 4 of 7 SS6383A(G) TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VCNTL=3.3V, VCNTL=3.3V VIN=2.5V VIN=2.5V VREF=1.25V VREF=1.25V Fig. 6 Fig.7 Output Short-Circuit (Sourcing) Output Short-Circuit (Sinking) VCNTL=3.3V, VCNTL=3.3V VIN=2.5V VIN=1.8V VREF=0.9V VREF=1.25V Fig.8 Transient Response at 1.25VTT/2A Fig. 9 Transient Response at 0.9VTT/2A BLOCK DIAGRAM VCNTL VIN + Control VREF VOUT Current Limit Thermal Shutdown VOUT Shutdown GND 11/07/2004 Rev.2.01 www.SiliconStandard.com 5 of 7 SS6383A(G) PIN DESCRIPTIONS (TO-252-5) PIN 4: PIN 1: PIN 2: PIN 3: VIN - Input supply pin. It provides main power to create the external reference voltage by divider resistors for regulating VREF and VOUT. GND - Ground pin. VCNTL - Input supply pin. It is used to supply all the internal control circuitry. PIN 5: VREF - Reference voltage input. Pull this pin low to shutdown device. VOUT - Output pin. APPLICATION INFORMATION Layout Consideration As the SS6383A is in SO-8 and TO-252-5 packages, it is unable to dissipate heat easily when it operates at high current. To avoid exceeding the maximum junction temperature, a suitable copper area must be used. Figure 10. Top layer 11/07/2004 Rev.2.01 The large copper area shown at V CNTL pins is able to relieve the thermal dissipation. Using the via to direct heat into the large copper area shown on the bottom layer also helps significantly. All capacitors should be placed as close as possible to the relevant pins. Figure 11. Bottom layer www.SiliconStandard.com Figure 12. Placement 6 of 7 SS6383A(G) PHYSICAL DIMENSIONS SO-8 D SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 H E e e A H 5.80 6.20 L 0.40 1.27 SYMBOL MIN MAX A 2.19 2.38 A1 0 0.13 b3 5.21 5.46 c2 0.46 0.58 D 5.33 5.59 E 6.35 6.73 A1 C B 1.27(TYP) L TO-252-5 A E b3 c2 L3 D H e e A A L L2 A1 1.27 BSC H 9.40 10.41 L 1.4 1.78 L1 2.67 REF L2 0.51 BSC L3 1.52 2.03 θ 0° 8° L1 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/07/2004 Rev.2.01 www.SiliconStandard.com 7 of 7