SS6383(G) 1.5A DDR Termination Regulator FEATURES DESCRIPTION Source and sink current capability of 1.5A The SS6383 linear regulator is designed to provide 1.5A source and sink current while regulating an output voltage to within 25mV. Low output voltage offset, ±20mV High accuracy output voltage at full-load VOUT adjustable by external resistors The SS6383 converts voltage supplies ranging from 1.6V to 6V into an output voltage that is set by two external voltage-divider resistors. It provides an excellent voltage source for active termination schemes for high-speed transmission lines such as those seen in highspeed memory buses. Low external component count Current limit protection Thermal protection SO-8 package APPLICATIONS Mother Board Graphic Cards DDR Termination Voltage Supply - supports DDR1 (1.25VTT), DDR2 (0.9VTT), and meets JEDEC SSTL-2 and SSTL-3 term. specifications The built-in current-limiting in source and sink mode, together with thermal shutdown, provides maximum protection to the SS6383 against fault conditions. TYPICAL APPLICATION CIRCUIT 1 VIN=2.5V CIN 470µF + R1 100K 2 3 C1 R2 EN 100pF 100K SSM7002EN VOUT=1.25V + 4 COUT VIN VCNTL GND VCNTL VREF VCNTL VOUT VCNTL 8 VCNTL=3.3V + 7 CCNTL 47µF 6 5 SS6383 220µF This device is available with Pb-free lead finish (second-level interconnect) as SS6383GS 10/07/2004 Rev.1.01 www.SiliconStandard.com 1 of 7 SS6383(G) ORDERING INFORMATION PIN CONFIGURATION SS6383XX XX SO-8 TOP VIEW Packing TR: Tape and reel Package type CS: SO-8, Commercial GS: SO-8, Commercial with Pb-free lead finish Example: VIN 1 8 VCNTL GND 2 7 VCNTL VREF 3 6 VCNTL VOUT 4 5 VCNTL SS6383GSTR in SO-8 package with Pb-free lead finish shipped on tape and reel ABSOLUTE MAXIMUM RATINGS Supply Voltage -0.4V to 7V Operating Temperature Range -40°C~85°C Junction Temperature Range 125°C Lead Temperature (Solder, 10sec) 260°C -65°C ~150°C Storage Temperature Range Thermal Resistance .JC SO-8 40°C /W Thermal Resistance θJA SO-8 160°C /W (Assumes no ambient airflow, no heatsink) Note1: Any stress beyond these Absolute Maximum Ratings may cause permanent damage to the device. TEST CIRCUIT 2.5V/1.8V 1.25V/0.9V VOUT 10/07/2004 Rev.1.01 + COUT 10µF 1 VIN VCNTL 2 GND VCNTL 3 VREF VCNTL 4 VOUT VCNTL 8 3.3V 7 6 5 SS6383 www.SiliconStandard.com 2 of 7 SS6383(G) ELECTRICAL CHARACTERISTICS VCNTL=3.3V, VIN=2.5V, VREF=0.5VIN, C OUT=10µF, TA=25°C, unless otherwise specified) (Note 1) PARAMETER TEST CONDITIONS SYMBOL MIN. TYP. Input Voltage (DDR1/2) Keep VCNTL≥VIN during power on and off sequences VIN 1.6 2.5/1.8 VCNTL 3.0 3.3 Output Voltage IOUT = 0mA VOUT Output Voltage Offset IOUT = 0mA (Note 2) VOS Load Regulation (DDR1/2) (Note 3) Quiescent Current IOUT =0.1mA ~ +1.5A IOUT = 0.1mA ~ -1.5A VREF<0.2V, VOUT = OFF Operating Current of VCNTL No load VREF Bias Current Current Limit 6 VREF -20 UNIT V V 20 mV 10 25 10 25 IQ 8 30 µA ICNTL 3 10 mA 1 µA 4.5 A ∆VLOR VREF=1.25V (Note 4) MAX. mV IIL 2.1 3 TSD 125 150 °C 30 °C THERMAL PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis 3.3V≤VCNTL≤5V Guaranteed by design SHUTDOWN SPECIFICATIONS Shutdown Threshold Output ON (VREF=0V 1.25V) Output OFF (VREF=1.25V 0V) 0.8 0.2 V Note 1: Specifications are production-tested at T A=25°C. Specifications over the -40°C to 85°C operating temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). Note 2: VOS is the difference between VOUT and VREF. Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Note 4: Current limit is measured using a low duty cycle. Note 5: To operate safely, V CNTL must always be greater than VIN. 10/07/2004 Rev.1.01 www.SiliconStandard.com 3 of 7 SS6383(G) TYPICAL PERFORMANCE CHARACTERISTICS 0.55 0.55 VCNTL=3.3V Threshold Voltage (V) Threshold Voltage (V) VCNTL=5V VIN=2.5V 0.50 0.45 0.40 0.35 0.50 VIN=2.5V 0.45 0.40 0.35 0.30 -40 -20 0 20 40 60 Temperature (°C) 80 100 0.30 -40 120 -20 2.0 VIN=2.5V VREF=1.25V No Load 60 80 100 120 100 120 4 1.5 1.0 3 2 VCNTL=3.3V 1 0.5 0.0 -40 40 5 V =3.3V, V =2.5V VCNTL CNTL=3.3VIN VOUT=1.25V Sourcing Current (A) Output Voltage Offset (mV) 2.5 20 Temperature (°C) Fig. 2 Turn-On Threshold vs. Temp Fig. 1 Turn-On Threshold vs. Temp. 3.0 0 VIN=2.5V VOUT=1.25V -20 0 20 40 60 80 100 120 o Temperature( C) 0 -40 -20 0 20 40 60 80 Temperature (°C) Fig. 4 Current-Limit (Sourcing) vs. Temperature Fig. 3 Output Voltage Offset vs. Temperature 5 Sinking Current (A) 4 V CNTL=3.3V VIN=2.5V VOUT=1.25V 3 2 1 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 5 Current-Limit (Sinking) vs. Temperature 10/07/2004 Rev.1.01 www.SiliconStandard.com 4 of 7 SS6383(G) TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VIN=2.5V VCNTL=3.3V VREF=1.25V VIN=2.5V VCNTL=3.3V VREF=1.25V IOUT : 1A/DIV IOUT : 1A/DIV Fig. 6 Output Short-Circuit (Sinking) Fig. 7 Output Short-Circuit Protection (Sourcing) VOUT: 50mV/DIV VOUT: 50mV/DIV VIN=2.5V VCNTL=3.3V VREF=1.25V IOUT : 1A/DIV VIN=1.8V VCNTL=3.3V VREF=0.9V IOUT : 1A/DIV Fig. 9 Transient Response at 0.9VTT/1.5A Fig. 8 Transient Response at 1.25VTT/1.5A BLOCK DIAGRAM VCNTL VIN + Control VREF VOUT Current Limit Thermal Shutdown VOUT Shutdown GND 10/07/2004 Rev.1.01 www.SiliconStandard.com 5 of 7 SS6383(G) PIN DESCRIPTIONS PIN 1: PIN 2: PIN 3: VIN - Input supply pin - provides power to create the external reference voltage using a resistor divider for regulating VREF and VOUT. GND - Ground pin. VREF - Reference voltage input. Pull this pin low to shut the device down. PIN 4: VOUT - Output pin. PIN 5~8: VCNTL - Input supply pin - supplies all the internal control circuitry. APPLICATION INFORMATION The large copper area around the VCNTL pins can Layout Consideration The SS6383 is in an SO-8 package and is unable to dissipate heat easily when operating with high currents. In order to avoid exceeding the maximum junction temperature, an appropriate area of copper must be used. Fig. 10. Top layer 10/07/2004 Rev.1.01 be used to assist the heat dissipation. Vias to lead heat into the bottom layer are also recommended. All capacitors should be placed as close to the relative IC pin as possible. Fig. 11. Bottom layer www.SiliconStandard.com Fig. 12. Placement 6 of 7 SS6383(G) PHYSICAL DIMENSIONS (unit: mm) SO-8 D SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 H E e h x 45° e A 0.25 C A1 Gauge Plane Seating Plane B Θ L 1.27BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 Θ 0° 8° Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/07/2004 Rev.1.01 www.SiliconStandard.com 7 of 7