SS6652 Micro-Power Inverting DC/DC Controller n n FEATURES DESCRIPTION The SS6652 is a high-performance inverting l 2.4V to 7V input voltage operation. l Adjustable output voltage up to -40V. l Low quiescent current at 80µA. l Pulse frequency modulation maintains high DC/DC controller, designed to drive an external power switch to generate programmable negative voltages, and is particularly suited to LCD bias contrast applications. Efficiency of 87% can be efficiency (87%). achieved with low cost PNP bipolar transistor l 70KHz to 160KHz switching frequency. l Power-saving shutdown mode (0.7µA typical). l High efficiency with low cost external P- drivers. Output voltage can be scaled to -40V or greater by two external resistors. A pulse frequency modulation scheme is employed to main- channel MOSFET or PNP bipolar transistor. tain high-efficiency conversion over a wide input voltage range. Quiescent current is about 80µA n l and can be reduced to 0.7µA in shutdown mode. APPLICATIONS With switching frequencies in the 70KHz to Negative LCD Contrast Bias for 160KHz range, the small size switching compo- 1. Notebook & Palmtop Computers. nents are ideal for battery powered portable 2. Pen-Based Data System. equipment, like notebook and palmtop computers. 3. Portable Data Collection Terminals. 4. Personal Digital Assistants. l n Negative Voltage Supply. TYPICAL APPLICATION CIRCUIT VIN 2.4V ~ 7V RCL 100µF + C1 CL VIN VREF DHI SHDN DLOW RB 150µH *L SS6652 0.047µF C4 R2 1N5819 470~1.8K GND FB Q1 9012 D1 C2 100µF VOUT -12V~ -40V -10mA + R1 1M C3 100K * Sumida CD-54 Series VOUT = -1.22V x R1/R2 10nF Negative LCD Contrast Bias Power Supply Rev.2.01 6/26/2003 www.SiliconStandard.com 1 of 6 SS6652 n ORDERING INFORMATION SS6652CXXX PIN CONFIGURATION PACKING TYPE TR: TAPE & REEL TB: TUBE DIP-8 SO-8 TOP VIEW PACKAGE TYPE N: PLASTIC DIP S: SMALL OUTLINE EX: SS6652CSTR à in SO-8 Package in Tape & Reel Packing VIN 1 8 CL VREF 2 7 DHI SHDN 3 6 DLOW FB 4 5 GND (CN is not available in TR packing type.) n ABSOLUTE MAXIMUM RATINGS Supply Voltage ..................................................................…………………............ 7V SHDN Voltage ...............................................……………..................................... 7V Operation Temperature Range ................................……….......................... 0°C~70°C Storage Temperature Range .................................…………................. -65°C~ 150°C n TEST CIRCUIT Refer to Typical Application Circuit. n ELECTRICAL CHARACTERISTICS PARAMETER TEST CONDITIONS (VIN=5V, Ta=25°C, unless otherwise specified.) MIN. TYP. MAX. UNIT 7 V 80 150 µA 1.22 1.28 V 2.4 Input Voltage Switch Off Current VFB=-50mV VREF Voltage ISOURCE = 250µA 1.16 µA 250 VREF Source Current DLOW “ON Resistance” 5 Ω DHI “ON Resistance” 7 Ω CL Threshold 70 mV 0.8 Shutdown Threshold Shutdown Mode Current Rev.2.01 6/26/2003 V SHDN = 0V www.SiliconStandard.com 1.5 2.4 V 0.7 2 µA 2 of 6 SS6652 n TYPICAL PERFORMANCE CHARACTERISTICS 1.5 350 Shutdown Current (µA) Source Current (µA) 300 250 200 150 100 1 0.5 50 0 2 3 4 5 6 7 0 8 VIN (V) Fig. 1 VREF Source Current vs. VIN 1 2 3 Fig. 2 4 5 6 7 8 VIN (V) Shutdown Current vs. VIN 100 95 130 Duty Cycle (%) Frequency (KHz) 150 110 TA=0°C 90 TA=25°C TA=0°C 90 TA=25°C TA=70°C 85 70 50 2 3 TA=70° C Fig. 3 n 80 4 VIN (V) 5 6 2 7 3 4 Fig. 4 Frequency vs. VIN Voltage VIN (V) 5 6 7 Duty Cycle vs. VIN Voltage BLOCK DIAGRAM VIN VREF SHDN FB Rev.2.01 6/26/2003 V IN CURRENT LIMIT COMPARATOR 1 70mV + 2 3 4 PFM OSCILLATOR CL V IN LATCH 1.22V REFERENCE VOLTAGE OUTPUT DRIVER 7 DHI 6 DLOW + - 8 5 GND ERROR COMPARATOR www.SiliconStandard.com 3 of 6 SS6652 n PIN DESCRIPTIONS PIN 1: VIN - Input supply voltage (2.4V~7V) PIN 6: DLOW - Driver sinking output. Connected to DHI when using an external Pchannel MOSFET. When using an external PNP bipolar transistor, connect a resistor RB from this pin to DHI. RB value depends on VIN, inductor and PNP bipolar transistor. By adjusting the RB value, efficiency can be optimized. PIN 2: VREF - Reference output (1.22V). Bypass with a 0.047µF capacitor to GND. Sourcing capability is guaranteed to be greater than 250µA. PIN 3: SHDN- Logic input to shutdown the chip. >1.5V = normal operation, GND = shutdown In shutdown mode DLOW and DHI pins are at high level. PIN 4: FB - Feedback signal input to sense ground. Connecting a resistor R1 to VOUT and a resistor R2 to VREF pin yields the output voltage: PIN 7: DHI - Driver sourcing output. Connect to gate of the external P-channel MOSFET or base of the PNP bipolar transistor. PIN 8: CL - Current-limit input. This pin clamps the switch peak current to prevent over-current damage to the external switch. VOUT = - (R1/R2 ) x VREF PIN 5: GND - Power ground. n APPLICATION INFORMATION The typical application circuit generates an adjustable Max. Output Power vs VIN negative voltage for contrast bias of LCD displays. Ef- 0.8 Max. Output Power (W) Typical Application Circuit 0.6 0.4 100µH ficiency and output power can be optimized by using 120µH appropriate inductor and switch. The following formu- 150µH lae provide a guideline for determining the optimal 180µH component values: 220µH L Inductor Value = (11.1 − 0.15 × V IN) × 0.2 PNP : 0 2 4 6 V CEO > V IN + V OUT I C, MAX ≥ 200 × 8 V IN (V) I OUT V IN × V OUT I OUT VIN V CE < 0. 4V at I C = 200 × IOUT V IN and β = 10 RB ≅ 3 x L x (VIN - 0.8) where, VIN(V), VOUT(V), IOUT(A), L(µH), RB(Ω) Rev.2.01 6/26/2003 www.SiliconStandard.com 4 of 6 SS6652 n APPLICATION CIRCUIT (Refer to TYPICAL APPLICATION CIRCUIT) 90 90 VOUT = -15V L =150µH VIN =7V Efficiency (%) Efficiency (%) VIN=5V 85 VOUT =-15V IOUT =-10mA 88 VIN=3V 80 75 L=220µH 86 84 L=150µH 82 L=100µH 80 70 0 5 10 15 20 25 Load Current (mA) Fig. 5 Efficiency vs. Load Current 30 2 3 4 5 7 8 Fig. 6 Efficiency vs. VIN 90 90 VOUT =-22V L =120µH 85 Efficiency (%) Efficiency (%) VOUT =-22V IOUT =-10mA 88 VIN=7V VIN=5V VIN=3V 80 L=220µH 86 L=150µH 84 75 L=100µH 82 70 0 5 10 15 20 25 80 30 2 Load Current (mA) Fig. 7 Efficiency vs. Load Current 3 4 5 6 7 8 VIN (V) Fig. 8 Efficiency vs. VIN 90 90 VOUT =-30V L =100µH VIN=7V VOUT =-30V IOUT =-10mA 88 85 VIN=5V 80 Efficiency (%) Efficiency (%) 6 VIN (V) VIN=3V L=150µH 86 L=120µH 84 75 L=100µH 82 70 0 Rev.2.01 6/26/2003 5 10 15 20 Load Current (mA) Fig. 9 Efficiency vs. Load Current 25 30 80 2 www.SiliconStandard.com 3 4 5 6 7 8 VIN (V) Fig. 10 Efficiency vs. VIN 5 of 6 SS6652 n PHYSICAL DIMENSIONS l 8 LEAD PLASTIC SO (unit: mm) D SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 H E e e A A1 C B l 1.27(TYP) H 5.80 6.20 L 0.40 1.27 L 8 LEAD PLASTIC DIP (unit: mm) D E1 E A2 A1 MAX A1 0.381 — A2 2.92 4.96 b 0.35 0.56 C 0.20 0.36 D 9.01 10.16 E 7.62 8.26 E1 6.09 7.12 e eB e MIN C L b SYMBOL 2.54 (TYP) eB — 10.92 L 2.92 3.81 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.01 6/26/2003 www.SiliconStandard.com 6 of 6