SS6804
Three/Four-cell Lithium-Ion Battery Protection IC
FEATURES
DESCRIPTION
Ultra-low quiescent current, 17µA (4-cell, Vcell = 3.5V).
Ultra-low power-down current, 2.2µA (4-cell, Vcell = 2.3V).
Wide supply voltage range: 2V to 18V.
Precision over-charge protection voltage:
4.35V±30mV for the SS6804A
4.30V±30mV for the SS6804B
4.25V±30mV for the SS6804C
4.20V±30mV for the SS6804D
Externally set over-charge, over-discharge and
over-current delay time.
Built-in cell-balancing bleeding network under
over-charge condition.
Three detection levels for over-current protection.
The SS6804 is designed to protect a lithium-ion
battery from damage or degraded lifetime due to
over-charging, over-discharging and over-current
for three- or four-cell lithium-ion battery powered
systems such as notebook PCs.
It provides the cell-balancing "bleeding" function
to automatically discharge the over-charged cell
until the over-charge condition is eliminated.
Safe charging with full utilization is ensured by
the accurate ±30mV over-charge detection. Four
different specification values for over-charge
protection voltage are provided for various
protection requirements. The very low standby
current represents little drain from the cell while in
storage.
APPLICATIONS
Protection IC for three/four-cell lithium-ion battery packs.
TYPICAL APPLICATION CIRCUIT
R8
1K
NSL
VCC
R1
16
200
C1
0.1µF
2
UD1 15
OC
3 CS
VC1
2K
UD2 13
VC2 12
6
CTI
2.2nF
UD3 11
10
TI
7 TC
CTC
82nF 8
C4
UD4 9
BAT1
BAT2
2K
FUSE
BATT+
R5
1M
R6
1M
BAT3
R7
1M
R4
VC3
GND
SSM4435M
M2
R3
C3
0.1µF
CTD
82nF
M1
R2
14
C2
0.1µF
4 OD
5 TD
SSM4435M
2N3906
Q1
1
33K
0.1µF
BAT4
SS6804
BATT-
Protection Circuit for Four-Cell Lithium-Ion Battery Pack
12/29/2003 Rev.2.02
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SS6804
ORDERING INFORMATION
PIN CONFIGURATION
SS6804XCXXX
Packing type
TR: Tape and reel
TB: Tube
TOP VIEW
Package type
S: SO-16
Over-charge Protection
Voltage
A: 4.35V
B: 4.30V
C: 4.25V
D: 4.20V
NSL 1
16 VCC
OC 2
15 UD1
CS
3
14 VC1
OD 4
13 UD2
TD
5
12 VC2
TI
6
11 UD3
TC
7
10 VC3
9
GND 8
UD4
Example: SS6804ACSTR
$4.35V version, in SO-16, shipped on tape and reel
ABSOLUTE MAXIMUM RATINGS
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!$4-"%$DDDDDC°E°
TEST CIRCUIT
ROC
1M
IOC
S1
1
2
VOC
VCC 16
NSL
OC
UD1 15
R8
3
VCS
1K
4
VOD
VC1 14
CS
OD
5 TD
13
VC2 12
6 TI
UD3 11
CTI
2.2nF
7 TC
CTC
1nF
8
IUD1
R1 200
C1
0.1µF
VC3
GND
10
UD4 9
VCC
IC1
R2 2K
UD2
CTD
1nF
ICC
IUD2
C2
0.1µF
IC2
IUD3
R3 2K
C3
0.1µF
IC3
IUD4
VC1
R4 33K
C4
0.1µF
VC2
VC3
SS6804
12/29/2003 Rev.2.02
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SS6804
ELECTRICAL CHARACTERISTICS
PARAMETER
(TA=25°C, unless otherwise specified.)
TEST CONDITIONS
SYMBOL
MIN.
TYP.
MAX. UNIT
VCC Pin Input Current in Normal
VCELL=3.5V
Mode
ICC
17
26
µA
VC1 Pin Input Current in Normal
VCELL=3.5V
Mode
IC1
0.7
1.8
µA
VC2 Pin Input Current in Normal
VCELL=3.5V
Mode
IC2
0.4
1.0
µA
VC3 Pin Input Current in Normal
VCELL=3.5V
Mode
IC3
0.2
0.5
µA
Vcc Pin Input Current in PowerDown Mode
VCELL=2.3V
ICC(PD)
2.2
4.0
µA
VC1,VC2,VC3 Input Current in
Power-Down Mode
VCELL=2.3V
IC(PD)
0.01
0.15
µA
SS6804A
SS6804B
Overcharge Protection Voltage
4.32
4.35
4.38
4.27
4.30
4.33
4.22
4.25
4.28
VOCP
SS6804C
SS6804D
V
4.17
4.20
4.23
Overcharge Hysteresis Voltage
VHYS
150
200
250
mV
Overdischarge Protection Voltage
VODP
2.27
2.40
2.53
V
Overdischarge Release Voltage
VODR
2.85
3.00
3.15
V
VOIP
135
150
165
mV
TOC
10
21
32
mS
TOD
10
21
32
mS
TOI1
7
15
23
mS
Overcurrent Protection Voltage
Overcharge Delay Time
VCELL=3.5V
VCELL1=VOCP - 30mV
→VOCP+30mV
VCELL2= VCELL3= VCELL4=
3.5V, CTC=1nF
VCELL1= 2.5V→ 2.3V
Overdischarge Delay Time
Overcurrent Delay Time (1)
12/29/2003 Rev.2.02
VCELL2= VCELL3= VCELL4=
3.5V, CTD=1nF
VCELL= 3.5V,0.15V<VCC VCS <0.3V,CTI=2.2nF
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SS6804
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
Overcurrent Delay Time (2)
TEST CONDITIONS
VCELL=3.5V,
0.3V<VCC-VCS<1.0V
SYMBOL
MIN.
TYP.
MAX. UNIT
TOI2
2
4
6
mS
Overcurrent Delay Time (3)
VCELL=3.5V, VCC– VCS>1.0V
TOI3
150
300
450
µS
OC Pin Sink Current
VCELL1=4.4V,
VCELL2= VCELL3=
VCELL4=3.5V,
OC Pin Short to VCC
IOC
2.2
3.2
4.2
mA
OD Pin Output “H” Voltage
VDH
OD Pin Output “L” Voltage
VDL
Charge Detection Threshold
Voltage
VCELL=2.3V
UD1 Pin Cell-Balancing
Bleeding Current
VCELL1=4.4V,
UD2 Pin Cell-Balancing
Bleeding Current
VCELL2=4.4V,
UD3 Pin Cell-Balancing
Bleeding Current
VCELL3=4.4V,
UD4 Pin Cell-Balancing
Bleeding Current
VCELL4=4.4V,
VCELL2= VCELL3=
VCELL4=3.5V
VCELL1= VCELL3=
VCELL4=3.5V
VCELL1= VCELL2=
VCELL4=3.5V
VCELL1= VCELL2=
VCELL3=3.5V
V
VCC-0.15V VCC-0.03V
0.01
VCH
0.15
VCC+0.4 VCC+0.55
V
V
IUD1
6.5
9.3
12.1
mA
IUD2
6.3
9.0
11.7
mA
IUD3
6.2
8.8
11.4
mA
IUD4
6.4
9.2
12.0
mA
Note: VCELL means the battery cell voltage. Therefore,
VCELL1 = VCC – VC1
VCELL2 = VC1 – VC2
VCELL3 = VC2 – VC3
VCELL4 = VC3
12/29/2003 Rev.2.02
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SS6804
TYPICAL PERFORMANCE CHARACTERISTICS
2.2
Vcc Pin Power-Down Current (µA)
22
Vcc Pin Input Current (µA)
TA=25°C
20
18
16
14
10.4
11.2
12.0
12.8
13.6
14.4
15.2
1.8
1.6
1.4
1.2
1.0
16.0
TA=25°C
2.0
6.0
VCELL =3.5V
20
18
16
14
-20
7.2
7.6
8.0
8.4
8.8
9.2
-10
0
10
20
30
40
50
60
2.8
2.6
VCELL=2.3V
2.4
2.2
2.0
1.8
1.6
-20
70
SS6804C
4.28
4.26
4.24
4.22
0
20
40
60
70
Temperature (°C)
Fig. 5 Overcharge Protection Voltage vs. Temperature
12/29/2003 Rev.2.02
Overdischarge Protection Voltage (V)
4.30
-20
-10
0
10
20
30
40
50
60
70
-10
0
10
20
30
40
50
60
70
Temperature (°C)
Fig. 4 Vcc Pin Power-Down Current vs. Temperature
Temperature (°C)
Fig. 3 Vcc Pin Input Current vs. Temperature
Overcharge Protection Voltage (V)
6.8
3.0
Vcc Pin Power-Down Current (uA)
Vcc Pin Input Current (µA)
22
4.20
6.4
Supply Voltage (V)
Fig. 2 Vcc Pin Power-Down Current vs. Supply Voltage
Supply Voltage (V)
Fig. 1 Vcc Pin Input Current vs. Supply Voltage
2.42
2.41
2.40
2.39
2.38
2.37
2.36
-20
Temperature (°C)
Fig. 6 Overdischarge Protection Voltage vs. Temperature
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SS6804
Overcurrent Protection Voltage (V)
152.0
151.5
VCELL=3.5V
151.0
150.5
150.0
149.5
149.0
148.5
148.0
-20
-10
0
10
20
30
40
50
60
70
Temperature(°C)
Fig. 7 Overcurrent Protection Voltage vs. Temperature
Overcharge/Overdischarge Delay Time (mS)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Overcharge Release Voltage (V)
Overcurrent Delay Time 1 (mS)
VCELL =3.5V
18
16
14
12
10
-20
CTC /CTD=1nF
24
22
20
18
16
14
-20
-10
0
10
20
30
40
50
60
70
Temperature(°C)
Fig. 8 Overcharge/Overdischarge Delay Time vs.
Temperature
4.08
22
20
26
-10
0
10
20
30
40
50
60
70
Temperature (°C)
Fig. 9 Overcurrent Delay Time 1 vs. Temperature
4.07
4.06
4.05
4.04
4.03
4.02
-20
-10
0
10
20
30
40
50
60
70
Temperature (°C)
Fig. 10 Overcharge Release Voltage vs. Temperature
Overdischarge Release Voltage (V)
3.01
3.00
2.99
2.98
2.97
-20
-10
0
10
20
30
40
50
60
Temperature o(°C)
Fig. 11 Overdischarge Release Voltage vs. Temperature
12/29/2003 Rev.2.02
70
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SS6804
BLOCK DIAGRAM
CS
3
VCC
VC1
VC2
VC3
UD1
16
14
Battery
Voltage
Sense
Circuit
12
Wake-Up Control
VCC+0.4V
VCC-0.15V
10
Overcurrent Delay
Circuit
15
300
VCC-0.3V
4
UD2
13
OD
VCC-1V
350
UD3
11
Overdischarge Delay
Circuit
400
UD4
Power-Down
Control
2
OC
Overcharge Delay
Circuit
9
450
1.2V
GND
8
7
TC
5
6
TD TI
PIN DESCRIPTIONS
PIN 1: NSL-
Input pin for cell number
selection. Connect this pin to
VCC for three-cell application
and to GND for four-cell
application.
PIN 2: OC-
NMOS open drain output for
control of the charge control
MOSFET M2. When overcharge
occurs, this pin sinks current to
switch the external PNP Q1 on,
and charging is inhibited by
turning off the charge control
MOSFET M2.
PIN 3: CS-
12/29/2003 Rev.2.02
Input pin for current sensing.
Using the drain-source voltage of
the discharge control MOSFET
M1 (voltage between VCC and
CS), it senses the discharge
current
during normal mode
and detects whether charging
current
is
present
during
power-down mode.
PIN 4: OD -
of
Output pin for control
discharge control MOSFET M1.
When overdischarge occurs, this
pin goes high to turn off the
discharge control MOSFET M1
and discharging is inhibited.
PIN 5: TD -
Overdischarge delay time setting
pin.
PIN 6: TI -
Overcurrent delay time setting
pin.
PIN 7: TC -
Overcharge delay time setting
pin.
PIN 8: GND -
Ground pin. This pin is to be
connected to the negative
terminal of the battery cell BAT4.
PIN 9: UD4-
This pin is to be connected to the
positive terminal of the battery
cell BAT4 for cell-balancing
bleeding
function
under
overcharge condition.
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SS6804
PIN10: VC3-
PIN11: UD3 -
PIN12: VC2 -
Input pin for battery BAT4
voltage sensing. This pin is to be
connected
to
the
positive
terminal of the battery cell BAT4.
This pin is to be connected to
the
positive terminal of the
battery cell BAT3
for
cellbalancing
bleeding function
under overcharge condition.
Input pin for battery BAT3
voltage sensing. This pin is to be
connected
to
the
positive
terminal of the battery cell BAT3.
PIN13: UD2 - This pin is to be connected to the
positive terminal of the battery
cell BAT2 for cell-balancing
bleeding
function
overcharge condition.
under
PIN14: VC1 -
Input pin for battery BAT2
voltage sensing. This pin is to be
connected
to
the
positive
terminal of the battery cell BAT2.
PIN15: UD1 -
positive terminal of the battery
BAT1 for cell-balancing bleeding
function
under
overcharge
condition.
PIN16: VCC - Power supply pin and input for
battery BAT1 voltage sensing.
This pin is to be connected to the
positive terminal of the battery
cell BAT1.
APPLICATION INFORMATION
THE OPERATION
Initialization
On initial power-up, such as connecting the
battery pack for the first time to the SS6804, the
SS6804 enters the power-down mode. A
charger must be applied to the SS6804 circuit
to enable the pack.
Overcurrent Protection
Overcharge Protection
When the voltage of either of the battery cells
exceeds the overcharge protection voltage
(VOCP) beyond the overcharge delay time (TOC)
period, charging is inhibited by the turning-off of
the charge control MOSFET M2. The
overcharge delay time is set by the external
capacitor CTC. Inhibition of charging is
immediately released when the voltage of the
overcharged
cell
becomes
lower
than
overcharge release voltage (VOCR or VOCP-VHYS)
through discharging.
Overdischarge Protection
When the voltage of either of the battery cells
falls below the overdischarge protection voltage
(VODP) beyond the overdischarge delay time
(TOD) period, discharging is inhibited by the
12/29/2003 Rev.2.02
turning-off of the discharge control MOSFET M1.
The overdischarge delay time is set by the
external capacitor CTD. Inhibition of discharging
is immediately released when the voltage of the
overdischarge cell becomes higher than the
overdischarge release voltage (VODR) through
charging.
In normal mode, the SS6804 continuously
monitors the discharge current by sensing the
voltage of CS pin. If the voltage VCC-VCS
exceeds the overcurrent protection voltage (VOIP)
beyond the overcurrent delay time (TOI) period,
the overcurrent protection circuit operates and
discharging is inhibited by the turning-off of the
discharge control MOSFET M1. Discharging
must be inhibited for at least 256ms after
overcurrent takes place to avoid damage to
external control MOSFETs due to rapidly
switching transient between BATT+ and BATTterminals. The overcurrent condition returns to
normal mode when the load is released and the
impedance between the BATT+ and BATTterminals is 20MΩ or higher.
The SS6804 is provided
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with the
three
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SS6804
overcurrent detection levels (0.15V, 0.3V and
1.0V) and the three overcurrent delay time (TOI1,
TOI2 and TOI3) corresponding to each
overcurrent detection level. TOI1 is set by the
external capacitor CTI. TOI2 and TOI3 default to
4ms and 300µs respectively, and can not be
adjusted due to protection of external MOSFETs
charger is connected to the battery pack, the
SS6804 immediately turns on all the timing
generation and detection circuitry and goes into
normal mode. Charging is determined to be in
progress if the CS pin voltage is higher than
VCC + 0.4V (charge detection threshold voltage
VCH).
DESIGN GUIDE
Cell-Balancing Bleeding after
Overcharge
When either of the battery cells is overcharged,
the SS6804 provides the cell-balancing
bleeding function to discharge the overcharged
cell at about 9mA until the voltage of the
overcharged cell decreases to overcharge
release voltage (VOCR or VOCP-VHYS).
Connecting UD1, UD2, UD3 and UD4 pins to the
positive terminals of battery cells BAT1, BAT2,
BAT3 and BAT4 accomplish this function,
respectively. Inserting resistors along UD2 pin to
BAT2 positive terminal path and UD4 pin to
BAT4 positive terminal path can decrease the
bleeding current.
Power-Down after Overdischarge
When overdischarge occurs, the SS6804 will go
into power-down mode, turning off all the timing
generation and detection circuitry to reduce the
quiescent current to about 2.2µA (VCC=9.2V). In
the unusual case where one battery cell is
overdischarged while another one under
overcharge condition, the SS6804 will turn off
all the detection circuitry except the overcharge
detection circuit for the cell under overcharge
condition.
Cell Number Selection
The user must configure the SS6804 for three
or four series cells application. For three-cell
application, NSL pin should be connected
directly to VCC pin. For four-cell application,
NSL pin should be connected directly to GND
pin.
No. of Series Cells
NSL Pin
3-cell
Connected to VCC
4-cell
Connected to GND
The protection circuit for three-cell lithium-ion
battery pack is shown in application examples
Fig. 1.
Setting the Overcharge and
Overdischarge Delay Time
The overcharge delay time is set by the external
capacitor CTC and the overdischarge delay time
is set by the external capacitor CTD. The
relationship between capacitance of the external
capacitors and delay time is tabulated as below.
CTC ‚CTD(nF)
TOC ‚TOD(ms)
1
21
5
52
10
132
22
253
33
347
47
617
68
748
82
1004
100
1630
Charge Detection after
Overdischarge
When overdischarge occurs, the discharge
control MOSFET M1 turns off and discharging is
inhibited. However, charging is still permitted
through the parasitic diode of M1. Once the
12/29/2003 Rev.2.02
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SS6804
The delay time can also be approximately
calculated by the following equations (if CTC,
CTD ≤ 82nF) :
TOC(mS) = 11.8 x CTC(nF)
TOD(mS) = 11.8 x CTD(nF)
Setting the Overcurrent Delay Time 1
The overcurrent delay time 1 (TOI1) at 0.15V <
VCC-VCS < 0.3V is set by the external capacitor
CTI, while the overcurrent delay time 2 and 3
(TOI2 and TOI3) is fixed by IC internal circuit.The
relationship between capacitance of the external
capacitor and delay time is tabulated as below.
CT I (nF)
TOI (ms)
1
4.8
2.2
15.0
3.3
18.8
5
23.6
6.8
31.0
10
61.8
Selection of External Control
MOSFETs
Because the overcurrent protection voltage is
preset, the threshold current for overcurrent
detection is determined by the turn-on
resistance of the discharge control MOSFET M1.
The turn-on resistance of the external control
MOSFETs can be determined by the equation:
RON=VOIP/IT (IT is the overcurrent threshold
current). For example, if the overcurrent
threshold current I T is designed to be 5A, the
turn-on resistance of the external control
MOSFETs must be 30mΩ. Users should be
aware that turn-on resistance of the MOSFET
changes with temperature variation due to heat
12/29/2003 Rev.2.02
dissipation. It changes with the voltage between
gate and source as well. (Turn-on resistance of
a MOSFET increases as the voltage between
gate and source decreases). Once the turn-on
resistance of the external MOSFET changes,
the overcurrent threshold current will change
accordingly.
Suppressing the Ripple and
Disturbance from Charger
To suppress the ripple and disturbance from
charger, connecting R1 to R4 and C1 to C4 is
recommended. Larger R1 will cause larger error
of battery sense voltage.
Controlling the Charge Control
MOSFET
R5, R6, R7 and NPN transistor Q1 are used to
switch the charge control MOSFET M2. If
overcharge does not occur, no current flows into
OC pin and Q1 is turned off, then M2 is turned
on. When overcharge occurs, current flows into
OC pin and Q1 is turned on, which turns off M2
in turn.
Protection at CS Pin
R8 is used for protection of IC when charger is
connected in reverse. The charge detection
function after overdischarge is possibly disabled
by larger value of R8. Resistance of 1KΩ is
recommended.
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SS6804
APPLICATION EXAMPLE
R8
1K
NSL
2
OC
3
CS
4
5
CTD +
82nF
+
+ C
TC
82nF
OD
TD
TI
7
TC
8
R1
C1
0.1µF
15
UD1
14
VC1
1K
UD3
VC3
C2 1K
0.1µF
GND
UD4
SSM4435M
M2
M1
C3 1K
0.1µF
FUSE
BATT+
R5
1M
BAT1
R3
11
10
9
SSM4435M
R2
13
UD2
12
VC2
6
CTI
2.2nF
16
VCC
2N3906
Q1
1
R6
1M
BAT2
R7
1M
R4
1K
C4
0.1µF
BAT3
BATT-
SS6804
Fig. 12 Protection Circuit for Three-Cell Lithium-Ion Battery Pack
TIMING DIAGRAM
Overcharge and Overdischarge Protection (VCS=VCC)
<TOC
TOC
V BAT1
V OCP
VCELL
V OCP - VHYS
VODR
V BAT2
V BAT4
V BAT3
VODP
TOD
<TOD
VOC
VOD
12/29/2003 Rev.2.02
Hi-Z
Hi-Z
0V
VCC
0V
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SS6804
Overcurrent Protection (V CELL=3.5V)
<256ms
>256ms
VCC
VCC - 0.15V
VCC - 0.3V
VCS
VCC - 1V
0V
TOI1
<TOI2
<TOI1
TOI3
VCC
VOD
0V
256ms
<256ms
VOC
Hi-Z
PHYSICAL DIMENSIONS
16 LEAD PLASTIC SO (150 mil) (unit: mm)
D
SYMBOL
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
9.80
10.00
E
3.80
4.00
H
E
e
e
H
5.80
6.20
L
0.40
1.27
A1
A
1.27 (TYP)
B
C
L
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
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