Low Noise/Low Power
X9258
Quad Non-Volatile Digital Potentiometer
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
The X9258 digital potentiometer contains 4
separate 100KΩ potentiometers with a digitally
programmable wiper position to one of 256 taps on
each pot. (Other values of resistance will be available at
a later date). The wiper position is determined by a
serial digital code that is received on the 2-wire
serial port. The 255 individual resistors in each pot
are all equal, creating a linear taper from one end of
each pot to the other. There are also four 8 bit nonvolatile data registers associated with each pot for
storing system data and the most recent wiper
position. Powering up the device causes the
contents of R0 register of each pot to be loaded into
the Wiper Counter register, restoring the last know
wiper position for each pot.
Quad—Four Separate Pots
256 Resistor Taps/Pot—0.4% resolution
2-Wire Serial Interface
Wiper Resistance, 150Ω typical
Four Non-Volatile Data Registers for Each Pot
Non-Volatile Storage of Wiper Position
Standby Current < 5µA Max (Total Package)
VCC = 2.7V to 5.5V Operation
100KΩ, 50KΩ Total Pot Resistance
100 Year Data Retention
24-Lead SOIC, 24-Lead XBGA
FUNCTIONAL DIAGRAM
POT0
WP
SCL
SDA
A0
A1
A2
A3
R0
R1
R2
R3
WIPER
COUNTER
REGISTER
(WCR)
VH0
R0
R1
VL0
R2
R3
WIPER
COUNTER RESISTOR
ARRAY
REGISTER
(WCR)
POT 2
VW0
INTERFACE
AND
CONTROL
CIRCUITRY
VH2
VL2
VW2
8
VW1
DATA
R0
R2
R1
R3
Xicor, Inc. 2000 Patents Pending
9900-2006.2 2/28/00 EP
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WIPER
COUNTER RESISTOR
ARRAY
REGISTER
POT 1
(WCR)
VW3
VH1
R0
VL1
R2
R1
WIPER
COUNTER RESISTOR
ARRAY
REGISTER
(WCR)
POT 3
R3
VH3
VL3
Characteristics subject to change without notice
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X9258
PIN DESCRIPTIONS
VW (VW0 – VW3)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9258.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to the
wiper counter registers.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs. An open drain output requires the use
of a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for
the DCP analog section.
PRINCIPLES OF OPERATION
The X9258 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and the
DCP potentiometers.
Device Address (A0–A3)
The Address inputs are used to set the least significant 4
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with the
X9258. A maximum of 16 devices may occupy the 2-wire
serial bus.
Serial Interface — 2-Wire
The X9258 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. Therefore,
the X9258 will be considered a slave device in all
applications.
Potentiometer Pins
VH (VH0 – VH3), VL (VL0 – VL3)
The VH and VL inputs are equivalent to the terminal
connections on either end of a mechanical
potentiometer.
PIN CONFIGURATION
PIN NAMES
SOIC
NC
1
Symbol
24
A3
A0
2
23
SCL
VW3
3
22
VL2
VH3
4
21
VH2
VL3
5
20
VW2
V+
6
19
V–
18
VSS
X9258
VCC
7
VL0
8
17
VW1
VH0
9
16
VH1
VW0
10
15
VL1
A2
11
14
A1
WP
12
13
SDA
1
A
B
C
XBGA
2
3
V W0 A2
4
A 1 VL1
V L0 WP SDA VW1
VCC VH0 VH1 VSS
D
E
F
V+ VH3 VH2 VV L3 NC
A3 VW2
VW3 A0 SCL VL2
Top View–Bumps Down
Description
SCL
Serial Clock
SDA
Serial Data
A0-A3
Device Address
VH0–VH3,
VL0–VL3
Potentiometers
(terminal equivalent)
VW0–VW3
Potentiometers
(wiper equivalent)
WP
Hardware Write Protection
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection (Allowed)
Characteristics subject to change without notice
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X9258
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (tLOW). SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9258 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and during
this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of
data.
The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte.
If the command is followed by a data byte the X9258 will
respond with a final acknowledge.
Array Description
The X9258 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (VH and VL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (VW)
output. Within each individual array only one switch may
be turned on at a time. These switches are controlled by
the Wiper Counter Register (WCR). The 8 bits of the
WCR are decoded to select, and enable, one of 256
switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated data
registers into the WCR. These data registers and the
WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(refer to Figure 1 below). For the X9258 this is fixed as
0101[B].
Figure 1. Slave Address
DEVICE TYPE
IDENTIFIER
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9258 compares the serial
data stream with the address input state; a successful
compare of all four address bits is required for the X9258
to respond with an acknowledge. The A0–A3 inputs can
be actively driven by CMOS input signals or tied to VCC
or VSS.
Acknowledge Polling
The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of
the typical 5ms E2PROM write cycle time. Once the stop
condition is issued to indicate the end of the nonvolatile
write command the X9258 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the device
slave address. If the X9258 is still busy with the write
operation no ACK will be returned. If the X9258 has
completed the write operation an ACK will be returned
and the master can then proceed with the next operation.
Characteristics subject to change without notice
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X9258
Flow 1. ACK Polling Sequence
Figure 2. Instruction Byte Format
REGISTER
SELECT
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
I3
ISSUE
START
ISSUE STOP
NO
YES
FURTHER
OPERATION?
I1
I0
INSTRUCTIONS
ISSUE SLAVE
ADDRESS
ACK
RETURNED?
I2
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
Instruction Structure
The next byte sent to the X9258 contains the instruction
and register pointer information. The four most significant
bits are the instruction. The next four bits point to one of
the two pots and when applicable they point to one of
four associated registers. The format is shown below in
Figure 2.
R1
R0
P1
P0
WIPER COUNTER
REGISTER SELECT
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction is
issued. The last bits (P1, P0) select which one of the four
potentiometers is to be affected by the instruction.
Four of the nine instructions end with the transmission of
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the data
registers. A transfer from a data register to a Wiper
Counter Register is essentially a write to a static RAM.
The response of the wiper to this action will be delayed
tWRL. A transfer from the Wiper Counter Register
(current wiper position), to a data register is a write to
nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it
may occur globally, wherein the transfer occurs between
all of the potentiometers and one of their associated
registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9258; either between the host and one of
the data registers or directly between the host and the
Wiper Control Latch. These instructions are: Read Wiper
Control Latch (read the current wiper position of the
selected pot), Write Wiper Counter Register (change
current wiper position of the selected pot), Read Data
Register (read the contents of the selected nonvolatile
register) and Write Data Register (write a new value to
the selected data register). The sequence of operations
is shown in Figure 4.
Characteristics subject to change without notice
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X9258
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
S
T
O
P
is HIGH, the selected wiper will move one resistor
segment towards the VH terminal. Similarly, for each SCL
clock pulse while SDA is LOW, the selected wiper will
move one resistor segment towards the VL terminal. A
detailed illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9258 has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one
segment steps; thereby, providing a fine tuning capability
to the host. For each SCL clock pulse (tHIGH) while SDA
Table 1. Instruction Set
Instruction Set
I0 R1 R0
I3
I2
I1
P1
P0
Read Wiper Counter
Register
1
0
0
1
0
0
1/0
1/0
Write Wiper Counter
Register
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Counter Register
pointed to by P1–P0
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed
to by P1–P0 and R1–R0
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
Write new value to the Data Register pointed to
by P1–P0 and R1–R0
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
1/0
1/0
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0
1/0
0
1/0
Global XFR Data Registers to Wiper
Counter Registers
0
0
0
1
1/0
1/0
0
0
Global XFR Wiper
Counter Registers to
Data Register
1
0
0
0
1/0
1/0
0
0
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
1/0
1/0
Instruction
Notes:
(7)
Operation
Read the contents of the Wiper Counter Register pointed to by P1–P0
Transfer the contents of the Data Register
pointed to by P1–P0 and R1–R0 to its associated Wiper Counter Register
Transfer the contents of the Wiper Counter
Register pointed to by P1–P0 to the Data Register pointed to by R1–R0
Transfer the contents of both Data Registers
pointed to by R1–R0 to their respective Wiper
Counter Registers
Transfer the contents of both Wiper Counter
Registeres to their respective data Registers
pointed to by R1–R0
Enable Increment/decrement of the Control
Latch pointed to by P1–P0
1/0 = data is one or zero
Characteristics subject to change without notice
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X9258
Figure 4. Three-Byte Command Sequence 2-Wire Interface
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
D7
D6 D5 D4
D3 D2
D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Command Squence 2-Wire Interface
F
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
ISSUED
t WRID
SCL
SDA
VW
VOLTAGE OUT
Characteristics subject to change without notice
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X9258
Figure 7. Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
Figure 8. Detailed Potentiometer Block Diagram Detailed Operation
SERIAL DATA PATH
VH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
C
O
U
N
T
E
R
REGISTER 1
8
REGISTER 2
8
REGISTER 3
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
D
E
C
O
D
E
INC/DEC
LOGIC
IF WCR = 00[H] THEN VW = VL
UP/DN
IF WCR = FF[H]THEN VW = VH
MODIFIED SCL
UP/DN
VL
CLK
VW
Characteristics subject to change without notice
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X9258
All DCP potentiometers share the serial interface and
share a common architecture. Each potentiometer has a
Wiper Counter Register and four data registers. A
detailed discussion of the register organization and array
operation follows.
Wiper Counter Register
The X9258 contains four Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter Register
can be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data
registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the
Increment/ Decrement instruction. Finally, it is loaded
with the contents of its data register zero (R0) upon
power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9258 is powered-down. Although the
register is automatically loaded with the value in R0 upon
power-up, it should be noted this may be different from
the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile data registers.
These can be read or written directly by the host and
data can be transferred between any of the four data
registers and the control latch. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of 10ms.
REGISTER DESCRIPTIONS
Data Registers, (8-bit), non-volatile:
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
NV
NV
NV
NV
NV
NV
NV
(MSB)
NV
(LSB)
Four 8-bit Data Registers for each DCP. (sixteen 8-bit
registers in total).
• {D7~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four different
wiper values. The contents of Data Register 0 are
automatically moved to the wiper counter register on
power-up.
Wiper Counter Register, (8-bit), volatile:
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
V
V
V
V
V
V
V
(MSB)
V
(LSB)
One 8-bit Wiper Counter Register for each DCP. (Four 8bit registers in total.)
• {D7~D0}: These bits specify the wiper position of the
respective DCP. The Wiper Counter Register is loaded
on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other
Data Register or directly. The contents of the WCR can
be saved in a DR.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Characteristics subject to change without notice
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X9258
Instruction Format
Notes: (1)
(2)
(3)
(4)
(5)
“MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
“A3 ~ A0”: stands for the device addresses sent by the master.
“X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
“I”: stands for the increment operation, SDA held high during active SCL phase (high).
“D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
wiper
S
opcode
addresses
A
C
P P
K 1 0 0 1 0 0 1 0
wiper position
S
(sent by slave on SDA)
A
C W W W W W W W W
K P P P P P P P P
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
instruction
wiper
S
opcode
addresses
A
C
P P
K 1 0 1 0 0 0 1 0
wiper position
S
(sent by master on SDA)
A
C W W W W W W W W
K P P P P P P P P
7 6 5 4 3 2 1 0
S
A
C
K
S
T
O
P
instruction
wiper
S
opcode
addresses
A
C
R R P P
K 1 0 1 1 1 0 1 0
wiper position
S
(sent by slave on SDA)
A
C W W W W W W W W
K P P P P P P P P
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
Write Wiper Counter Register
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
Read Data Register
device
S device type
identifier
addresses
T
A
R 0 1 0 1 A A A A
3 2 1 0
T
Write Data Register
S device type
device
instruction
wiper
S
T identifier
addresses
opcode
addresses
A
A
C
R R P P
R 0 1 0 1 A A A A
1 1 0 0
3 2 1 0 K
1 0 1 0
T
wiper position
S
(sent by master on SDA)
A
C W W W W W W W W
P P P P P P P P
K
7 6 5 4 3 2 1 0
S
A
C
K
S
T HIGH-VOLTAGE
O WRITE CYCLE
P
XFR Data Register to Wiper Counter Register
S device type
device
instruction
wiper
S
T identifier
addresses
opcode
addresses
A
A
C
R R P P
R 0 1 0 1 A A A A
1 1 0 1
3 2 1 0 K
1 0 1 0
T
S
A
C
K
S
T
O
P
Characteristics subject to change without notice
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X9258
Write Wiper Counter Register to Data Register
S device type
device
T identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
wiper
S
opcode
addresses
A
C
R R P P
K 1 1 1 0 1 0 1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
wiper
S
opcode
addresses
A
C
P P
K 0 0 1 0 0 0 1 0
increment/decrement
S
(sent by master on SDA)
A
C I/ I/
I/ I/
K D D . . . . D D
S
T
O
P
Global XFR Data Register to Wiper Counter Register
S device type
device
identifier
addresses
T
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
wiper
S
opcode
addresses
A
C
R R
K 0 0 0 1 1 0 0 0
S
A
C
K
S
T
O
P
Global XFR Wiper Counter Register to Data Register
S device type
device
T identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
wiper
S
opcode
addresses
A
C
R R
1 0 0 0
0 0
K
1 0
SYMBOL TABLE
WAVEFORM
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
RESISTANCE (K)
120
VCC MAX
RMIN =
=1.8KΩ
IOL MIN
tR
RMAX =
CBUS
MAX.
RESISTANCE
100
80
60
40
20
0
MIN.
RESISTANCE
0
20
40
60
80 100 120
BUS CAPACITANCE (pF)
Characteristics subject to change without notice
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X9258
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .........................–65°C to +135°C
Storage temperature ..............................–65°C to +150°C
Voltage on SDA, SCL or any address input
with respect to VSS ..................................... –1V to +7V
Voltage on V+ (referenced to VSS) .............................. 10V
Voltage on V- (referenced to VSS) ..............................-10V
(V+) – (V-) .................................................................... 12V
Any VH ........................................................................... V+
Any VL ............................................................................. VLead temperature (soldering, 10 seconds)............. 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those listed
in the operational sections of this specification) is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
Max.
Device
Supply Voltage (VCC) Limits
0°C
+70°C
X9258
5V ±10%
–40°C
+85°C
X9258-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
End to end resistance
Min.
Typ.
Max.
Units
–20
+20
%
50
mW
–3
+3
mA
250
Ω
Power rating
IW
Wiper current
RW
Wiper resistance
150
V+
Voltage on V+ Pin
V-
Voltage on V- Pin
VTERM
X9258
+4.5
+5.5
X9258-2.7
+2.7
+5.5
X9258
-5.5
-4.5
X9258 -2.7
-5.5
-2.7
Voltage on any VH or VL pin
V-
Noise
Resolution (4)
Absolute linearity
(1)
linearity (2)
Relative
Temperature coefficient of resistance
V+
Test Conditions
25°C, each pot
Wiper Current = ± 1mA
V
V
V
-120
dBV
1.6
%
Ref: 1kHz
–1
+1
MI(3)
Vw(n)(actual) – Vw(n)(expected)
–0.6
+0.6
MI(3)
Vw(n + 1) – [Vw(n) + MI]
±300
ppm/°C
Characteristics subject to change without notice
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X9258
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
mA
fSCL = 400KHz, SDA = Open,
Other Inputs = VSS
100
µA
fSCL = 400KHz, SDA = Open,
Other Inputs = VSS
VCC current (standby)
5
µA
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.1
V
VIL
Input LOW voltage
–0.5
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
ICC1
VCC supply current
(Nonvolatile Write)
ICC2
VCC supply current (move
wiper, write, read)
ISB
1
IOL = 3mA
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/255 or (VH – VL)/255, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum endurance
100,000
Data changes per register
Data retention
100
years
CAPACITANCE
Symbol
(5)
CI/O
(5)
CIN
Test
Max.
Units
Test Conditions
Input/output capacitance (SDA)
8
pF
VI/O = 0V
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
Min.
Max.
Units
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
50
V/msec
POWER-UP TIMING
Symbol
tPUR(6)
(6)
tPUW
(8)
tR VCC
Parameter
VCC Power up ramp
0.2
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can
be issued. These parameters are periodically sampled and not 100% tested.
(7) The power supply sequence should be VSS, V-, VCC, V+ and the VCC with no slope reversals.
(8) This is not a tested or guaranteed parameter and should be used as a guideline.
Characteristics subject to change without notice
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X9258
A.C. TEST CONDITIONS
Input Pulse Levels
EQUIVALENT A.C. LOAD CIRCUIT
VCC x 0.1 to VCC x 0.9
Input rise and fall times
Input and output timing level
5V
10ns
2.7V
1533Ω
VCC x 0.5
SDA OUTPUT
100pF
100pF
AC TIMING (Over recommended operating condition)
Symbol
Parameter
fSCL
Clock frequency
tCYC
Clock cycle time
tHIGH
tLOW
Min.
Max.
Units
400
KHz
2500
ns
Clock high time
600
ns
Clock low time
1300
ns
tSU:STA
Start setup time
600
ns
tHD:STA
Start hold time
600
ns
tSU:STO
Stop setup time
600
ns
tSU:DAT
SDA data input setup time
100
ns
tHD:DAT
SDA data input hold time
30
ns
tR
SCL and SDA rise time
tF
SCL and SDA fall time
tAA
SCL low to SDA data output valid time
100
tDH
SDA data output hold time
50
ns
TI
Noise suppression time constant at
SCL and SDA inputs
50
ns
tBUF
Bus free rime (prior to any transmission)
1300
ns
tSU:WPA
WP, A0, A1, A2 and A3 setup time
0
ns
tHD:WPA
WP, A0, A1, A2 and A3 hold time
0
ns
300
ns
300
ns
900
ns
Characteristics subject to change without notice
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X9258
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
Max.
Units
5
10
ms
DCP TIMING
Symbol
Parameter
Min.
Max.
Units
tWRPO
Wiper response time after the third (last) power supply is stable
10
µS
tWRL
Wiper response time after instruction issued (all load instructions)
10
µS
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement
instruction)
10
µS
Notes: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge
of SCL.
Characteristics subject to change without notice
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X9258
TIMING DIAGRAMS 2-WIRE INTERFACE
Figure 9. START and STOP Timing
(START)
(STOP)
tF
tR
SCL
tSU:STA
tHD:STA
tR
tF
tSU:STO
SDA
Figure 10. Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Figure 11. Output Timing
SCL
SDA
tDH
tAA
Figure 12. DCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
LSB
tWRL
VWx
Characteristics subject to change without notice
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X9258
Figure 13. DCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec
tWRID
VWx
Figure 14. Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
A2, A3
Characteristics subject to change without notice
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X9258
24-ball BGA (X9258TA/X9258UA)
a
a
l
j
m
1
2
3
4
4
3
2
1
A
A
B
B
k
C
C
D
D
E
E
b
b
f
F
Top View (Bump Side Down)
F
Bottom View (Bump Side Up)
Note: Drawing not to scale
= Die Oridentation mark
d
c
e
Side View (Bump Side Down)
Millimeters
Inches
Symbol
Min
Nom
Max
Min
Nom
Max
Package Body Dimension X
a
2.753
2.783
2.813
0.10838
0.10956
0.11074
Package Body Dimension Y
b
4.531
4.561
4.591
0.17838
0.17956
0.18074
Package Height
c
0.697
0.730
0.763
0.02744
0.02874
0.03004
Package Body Thickness
d
0.444
0.457
0.470
0.01748
0.01799
0.01850
Ball Height
e
0.253
0.273
0.293
0.00996
0.01075
0.01154
Ball Diameter
f
0.360
0.374
0.388
0.01417
0.01472
0.01528
Total Ball Count
g
24
Ball Count X Axis
h
4
Ball Count Y Axis
i
6
Pins Pitch XAxis
j
0.5
Pins Pitch Y Axis
k
0.5
Edge to Ball Center (Corner)
Distance Along X
l
0.611
0.641
0.671
0.02407
0.02525
0.02643
Edge to Ball Center (Corner)
Distance Along Y
m
1.000
1.030
1.060
0.03939
0.04057
0.04175
Characteristics subject to change without notice
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X9258
24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" TYPICAL
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" TYPICAL
24 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice
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X9258
ORDERING INFORMATION
X9258
Y
P
T
V
VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
Z24 = 24-Lead BGA
Potentiometer Organization
Pot 0 Pot 1 Pot 3 Pot 4
T = 100KΩ 100KΩ 100KΩ 100KΩ
U= 50KΩ 50KΩ 50KΩ 50KΩ
PART MARK CONVENTION
24 Lead XBGA
Top Mark
X9258UZ24I-2.7
XABE
X9258UZ24
XABF
X9258TZ24
XABX
X9258TZW24I-2.7
XABW
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc.
All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461;
4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880;
5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice
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