0 R XCR3032XL 32 Macrocell CPLD DS023 (v2.2) September 15, 2008 0 Product Specification 14 Features Description • • • • • The CoolRunner™ XPLA3 XCR3032XL device is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide 750 usable gates. Pin-to-pin propagation delays are as fast as 4.5 ns with a maximum system frequency of 213 MHz. • • • • • • • TotalCMOS Design Technique for Fast Zero Power CoolRunner XPLA3 CPLDs offer a TotalCMOS solution, both in process technology and design technique. Xilinx® CPLDs employ a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, one must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of the XCR3032XL TotalCMOS CPLD (data taken with two resetable up/down, 16-bit counters at 3.3V, 25° C). 20 Typical ICC (mA) • Low power 3.3V 32 macrocell CPLD 4.5 ns pin-to-pin logic delays System frequencies up to 213 MHz 32 macrocells with 750 usable gates Available in small footprint packages - 48-ball CS BGA (36 user I/O pins) - 44-pin VQFP (36 user I/Os) Optimized for 3.3V systems - Ultra-low power operation - Typical Standby Current of 17 μA at 25°C - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero Power (FZP) CMOS technology - 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance) Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 available clocks per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access Refer to the CoolRunner XPLA3 family data sheet (DS012) for architecture description 15 10 5 0 0 20 40 60 80 100 120 140 160 180 200 Frequency (MHz) DS023_01_080101 Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C) Frequency (MHz) 0 1 5 10 20 50 100 200 Typical ICC (mA) 0.017 0.13 0.54 1.06 2.09 5.2 10.26 20.3 © 2000–2008 Xilinx, Inc. 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DS023 (v2.2) September 15, 2008 Product Specification www.xilinx.com 1 R XCR3032XL 32 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol VOH(2) Parameter(1) Output High voltage VOL IIL(4) IIH(4) ICCSB(8) ICC Output Low voltage Input leakage current I/O High-Z leakage current Standby current Dynamic current(5,6) CIN CCLK CI/O Input pin capacitance(7) Clock input capacitance(7) I/O pin capacitance(7) Test Conditions VCC = 3.0V to 3.6V, IOH = –8 mA VCC = 2.7V to 3.0V, IOH = –8 mA IOH = –500 μA IOL = 8 mA VIN = GND or VCC to 5.5V VIN = GND or VCC to 5.5V VCC = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz Typical 24.5 - Min. 2.4 2.0 90% VCC(3) –10 –10 - Max. 0.4 10 10 100 0.25 7.5 8 12 10 Unit V V V V μA μA μA mA mA pF pF pF Notes: 1. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. Typical leakage current is less than 1 μA. 5. See Table 1, Figure 1 for typical values. 6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 7. Typical values, not tested. 8. Typical value at 70°C. 100 90 IOL (3.3V) 80 70 mA 60 50 IOH (3.3V) 40 30 IOH (2.7V) 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Volts DS012_10_031802 Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25°C 2 www.xilinx.com DS023 (v2.2) September 15, 2008 Product Specification R XCR3032XL 32 Macrocell CPLD AC Electrical Characteristics Over Recommended Operating Conditions -5 Parameter(1, 2) Symbol TPD1 Min. Propagation delay time (single p-term) array)(3) -7 -10 Max. Min. Max. Min. Max. Unit 4.5 - 7.0 - 9.1 ns 5.0 - 7.5 - 10.0 ns 5.0 - 6.5 ns TPD2 Propagation delay time (OR TCO Clock to output (global synchronous pin clock) TSUF Setup time (fast input register) 2.5 - 3.0 - 3.0 - ns TSU1(4) Setup time (single p-term) 3.0 - 4.3 - 5.4 - ns TSU2 Setup time (OR array) 3.5 - 4.8 - 6.3 - ns TH(4) Hold time 0 - 0 - 0 - ns TWLH(4) TPLH(4) Global Clock pulse width (High or Low) 2.5 - 3.0 - 4.0 - ns P-term clock pulse width 4.0 - 5.0 - 6.0 - ns TAPRPW Asynchronous preset/reset pulse width (High or Low) 4.0 - 5.0 - 6.0 - ns TR(4) TL(4) Input rise time - 20 - 20 - 20 ns Input fall time - 20 - 20 - 20 ns fSYSTEM(4) Maximum system frequency - 213 - 119 - 95 MHz TCONFIG(4) Configuration time(5) - 30 - 30 - 30 μs TINIT(4) ISP initialization time - 30 - 30 - 30 μs P-term OE to output enabled - 7.2 - 9.3 - 11.2 ns - 7.2 - 9.3 - 11.2 ns TPOE (4) disabled(6) 3.5 TPOD (4) P-term OE to output TPCO (4) P-term clock to output - 6.0 - 8.3 - 10.7 ns P-term set/reset to output valid - 6.5 - 9.3 - 11.2 ns TPAO(4) Notes: 1. Specifications measured with one output switching. 2. See CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 3 mA at 3.6V. 6. Output CL = 5 pF. DS023 (v2.2) September 15, 2008 Product Specification www.xilinx.com 3 R XCR3032XL 32 Macrocell CPLD Internal Timing Parameters -5 Parameter(1, 2) Symbol -7 -10 Min. Max. Min. Max. Min. Max. Unit Buffer Delays TIN Input buffer delay - 0.7 - 1.6 - 2.2 ns TFIN Fast Input buffer delay - 2.2 - 3.0 - 3.1 ns TGCK Global Clock buffer delay - 0.7 - 1.0 - 1.3 ns TOUT Output buffer delay - 1.8 - 2.7 - 3.6 ns TEN Output buffer enable/disable delay - 4.5 - 5.0 - 5.7 ns - 1.3 - 1.6 - 2.0 ns Internal Register, Product Term, and Combinatorial Delays TLDI Latch transparent delay TSUI Register setup time 1.0 - 1.0 - 1.2 - ns THI Register hold time 0.3 - 0.5 - 0.7 - ns TECSU Register clock enable setup time 2.0 - 2.5 - 3.0 - ns TECHO Register clock enable hold time 3.0 - 4.5 - 5.5 - ns TCOI Register clock to output delay - 1.0 - 1.3 - 1.6 ns TAOI Register async. S/R to output delay - 2.0 - 2.3 - 2.1 ns TRAI Register async. recovery - 3.5 - 5.0 - 6.0 ns TPTCK Product term clock delay - 2.5 - 2.7 - 3.3 ns TLOGI1 Internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns TLOGI2 Internal logic delay (PLA OR term) - 2.5 - 3.2 - 4.2 ns - 0.2 - 2.9 - 3.5 ns Feedback Delays TF ZIA delay Time Adders TLOGI3 Foldback NAND delay - 2.0 - 2.5 - 3.0 ns TUDA Universal delay - 1.2 - 2.0 - 2.5 ns TSLEW Slew rate limited delay - 4.0 - 5.0 - 6.0 ns Notes: 1. These parameters guaranteed by design and characterization, not testing. 2. See the CoolRunner XPLA3 family data sheet (DS012) for timing model. 4 www.xilinx.com DS023 (v2.2) September 15, 2008 Product Specification R XCR3032XL 32 Macrocell CPLD Switching Characteristics VCC S1 Component R1 R2 C1 R1 Values 390Ω 390Ω 35 pF VIN VOUT R2 Measurement TPOE (High) TPOE (Low) TP C1 S1 Open Closed Closed S2 Closed Open Closed Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH – 300 mV. S2 DS023_03_102401 Figure 3: AC Load Circuit 4.5 +3.0V 90% 10% TPD (ns) 4.0 0V TR 1.5 ns 3.5 3.0 1 2 4 8 16 TL 1.5 ns Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS023_06_042800 Outputs DS023_05_061101 Figure 5: Voltage Waveform Figure 4: Derating Curve for TPD2 DS023 (v2.2) September 15, 2008 Product Specification www.xilinx.com 5 R XCR3032XL 32 Macrocell CPLD Pin Descriptions Table 3: XCR3032XL I/O Pins Table 2: XCR3032XL User I/O Pins PC44(1) VQ44 CS48 VQ44 CS48 2 10 31 25 E7 36 36 36 2 11 29 23 F7 2 12 28 22 G7 2 13 27 21 G6 2 14 26 20 F5 2 15 25 19 G5 2 16 24 18 F4 This is an obsolete package type. It remains here for legacy support only. Table 3: XCR3032XL I/O Pins Function Block Macrocell PC44(1) VQ44 CS48 1 1 4 42 A2 1 2 5 43 A1 1 3 6 44 C4 1 4 7(2) 1(2) B1(2) 1 5 8 2 C2 1 6 9 3 C1 1 7 11 5 D3 Pin Type PC44(1) VQ44 CS48 1 8 12 6 D1 IN0 / CLK0 2 40 A3 1 9 13(2) 7(2) D2(2) IN1 / CLK1 1 39 B4 1 10 14 8 E1 IN2 / CLK2 44 38 A4 1 11 16 10 F1 IN3 / CLK3 43 37 B5 1 12 17 11 G1 TCK 32 26 E5 1 13 18 12 E4 TDI 7 1 B1 1 14 19 13 F2 TDO 38 32 B7 1 15 20 14 G2 TMS 13 7 D2 1 16 21 15 F3 PORT_EN 10(2) 4(2) C3(2) 2 1 41 35 C5 VCC 2 2 40 34 A6 3, 15, 23, 35 9, 17, 29, 41 B3, C7, E2, G4 2 3 39 33 B6 GND 22, 30, 42 16, 24, 36 A5, E3, E6 2 4 38(2) 32(2) B7(2) No Connects - - A7, B2, F6, G3 2 5 37 31 D4 2 6 36 30 C6 2 7 34 28 D6 2 8 33 27 D7 9 32(2) 26(2) E5(2) 2 6 Macrocell PC44(1) Total User I/O Pins 1. Function Block Notes: 1. This is an obsolete package type. It remains here for legacy support only. 2. JTAG pins. Table 4: XCR3032XL Global, JTAG, Port Enable, Power, and No Connect Pins Notes: 1. This is an obsolete package type. It remains here for legacy support only. 2. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full explanation. www.xilinx.com DS023 (v2.2) September 15, 2008 Product Specification R XCR3032XL 32 Macrocell CPLD Device Part Marking R XCRxxxxXL TQ144 Device Type Package This line not related to device part number 7C Speed Operating Range 1 Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: · · · · Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 3064XL. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes; C1 = CS48, C2 = CSG48. Ordering Combination Information Speed (pin-to-pin delay) Pkg. Symbol No. of Pins XCR3032XL-5VQ44C 5 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3032XL-5VQG44C 5 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3032XL-5CS48C 5 ns CS48 48 Chip Scale Package (CSP) C XCR3032XL-5CSG48C 5 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3032XL-7VQ44C 7.5 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3032XL-7VQG44C 7.5 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3032XL-7CS48C 7.5 ns CS48 48 Chip Scale Package (CSP) C XCR3032XL-7CSG48C 7.5 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3032XL-7VQ44I 7.5 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) I XCR3032XL-7VQG44I 7.5 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free I XCR3032XL-7CS48I 7.5 ns CS48 48 Chip Scale Package (CSP) I XCR3032XL-7CSG48I 7.5 ns CSG48 48 Chip Scale Package (CSP); Pb-Free I XCR3032XL-10VQ44C 10 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3032XL-10VQG44C 10 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb- Free C XCR3032XL-10CS48C 10 ns CS48 48 Chip Scale Package (CSP) C XCR3032XL-10CSG48C 10 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3032XL-10VQ44I 10 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) I Device Ordering and Part Marking Number DS023 (v2.2) September 15, 2008 Product Specification Package Type www.xilinx.com Operating Range(1) 7 R XCR3032XL 32 Macrocell CPLD Ordering Combination Information (Continued) Speed (pin-to-pin delay) Pkg. Symbol No. of Pins Package Type Operating Range(1) XCR3032XL-10VQG44I 10 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free I XCR3032XL-10CS48I 10 ns CS48 48 Chip Scale Package (CSP) I XCR3032XL-10CSG48I 10 ns CSG48 48 Chip Scale Package (CSP); Pb-Free I Device Ordering and Part Marking Number Notes: 1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C 8 www.xilinx.com DS023 (v2.2) September 15, 2008 Product Specification R XCR3032XL 32 Macrocell CPLD Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Additional Information CoolRunner XPLA3 CPLD Data Sheets and Application Notes Device Packages Device Package User Guide Revision History The following table shows the revision history for this document. Date Version 11/18/00 1.0 Initial Xilinx release. 02/05/01 1.1 Removed Timing Model. 04/11/01 1.2 Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers, Table 1 and updated Figure 1. Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. 04/19/01 1.3 Updated Typical I/V curve, Figure 2: added voltage levels. 08/27/01 1.4 Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial packages. Added 200 MHz to Figure 1 and Table 1. changed -5 FSYSTEM to 200 MHz, -5 TF to 0.5 ns. 01/08/02 1.5 Updated THI spec to correct a typo. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement.Updated note 5 in AC Characteristics table lowering typical current draw during configuration. 01/06/03 1.6 Added voltage and temperature to Figure 2. Increased -5 TPCO to 6.0 (from 5.5 ns) by adding TPTCK parameter to internal timing model. Increased -5 FMAX. Updated Ordering Information format. 07/15/03 1.7 Updated Device Part Marking. Updated test conditions for IIL and IIH. 08/21/03 1.8 Updated Package Device Marking Pin 1 orientation. 02/13/04 1.9 Add solder temperature specification. Add links to data sheets, application notes and packages. 04/08/05 2.0 Added ICCSB Typical and TAPRPW specifications. Removed TSOL specification. Added note about Pb-free packages. 03/31/06 2.1 Added Warranty Disclaimer; Added Pb-Free ordering information. 09/15/08 2.2 Added notes to tables to indicate PC44 and PCG44 packages are obsolete. Removed part number references to the obsolete PC44C and PCG44C packages in the Ordering Combination Information. See Product Discontinuation Notice xcn07022.pdf. DS023 (v2.2) September 15, 2008 Product Specification Revision www.xilinx.com 9