AKM AKD4140

ASAHI KASEI
[AK4140]
AK4140
Digital BTSC Decoder
GENERAL DESCRIPTION
The AK4140 is a BTSC decoder, which is optimized for Digital STB/TV application. The AK4140 achieves
high audio performance using original demodulation techniques for 4.5MHz inter-carrier sound, and the
digital BTSC decoding architecture using digital dbx-TV® technology licensed from THAT Corporation
requires no alignment of external parts. The AK4140 supports major audio data formats (MSB justified,
I2S, TDM) to interface with usual DSP. Therefore, the AK4140 is suitable for the systems such as Digital
STB/TV, AV recorder etc.
The dbx-TV® brand identifies a range of technology solutions for digital TV-audio decoding developed and
licensed by THAT Corporation. The dbx-TV provides high performance solutions with high quality sound.
FEATURES
† Capable of receiving 4.5MHz intercarrier sound and FM demodulation
† Alignment Free Digital BTSC decoding (Mono/Stereo/SAP)
† Programmable pilot/SAP/noise detection threshold
† Automatic return to mono dependant on pilot/noise level
† Mono/Stereo/SAP selectable output
† Digital volume control
† Soft Mute function
† Digital HPF for DC-Offset cancel
† Sampling Rate (fs): 32k/44.1k/48kHz
† Master Clock: 256fs/384fs /512fs/768fs
† Audio Interface: Master or Slave Mode
† Output format: 16bit MSB justified / I2S or TDM
† S/(N+D): 0.13%
† S/N:
73dB
† Power Supply: 2.7 ~ 3.6V
† Ta: -20 ~ 85°C
VDD
VSS
PDN
MCLK
FILT
Clock Divider
TDMIN
LRCK
SIF
FM
Demodulator
BTSC
Decoder
Serial I/O
Interface
SCLK
SDTO
Control
Register
CAD1 CAD0
SCL
SDA INT0 INT1
.
MS0547-E-01
2007/03
-1-
ASAHI KASEI
[AK4140]
„ Ordering Guide
AK4140VF
AKD4140
-20 ∼ +85°C
Evaluation Board
24pin VSOP
„ Pin Layout
FILT
1
24
TST2
AVSS
2
23
TST1
AVDD
3
22
TSTI2
SIF
4
21
TSTI1
DVSS
5
20
TSTO
DVDD
6
19
PDN
SDTO
7
18
INT1
SCLK
8
17
INT0
LRCK
9
16
CAD1
MS
10
15
CAD0
TDMIN
11
14
SCL
MCLK
12
13
SDA
Top
View
MS0547-E-01
2007/03
-2-
ASAHI KASEI
[AK4140]
PIN/FUNCTION
No.
Pin Name
I/O
1
FILT
2
3
AVSS
AVDD
-
4
SIF
I
5
6
DVSS
DVDD
-
7
SDTO
O
8
SCLK
I/O
9
LRCK
I/O
10
MS
I
11
TDMIN
I
12
13
14
15
16
17
18
MCLK
SDA
SCL
CAD0
CAD1
INT0
INT1
I
I/O
I
I
I
O
O
19
PDN
I
20
TSTO
O
21
TSTI1
I
22
TSTI2
I
23
TST1
I
24
TST2
I
-
Function
Filter Pin
2.2nF should be connected between FILT pin and VSS pin.
Analog Ground Pin
Analog Power Supply Pin, 2.7 ∼ 3.3V
4.5MHz SIF Input Pin.
Should be AC-coupled with 68nF.
Digital Ground Pin
Digital Power Supply Pin, 2.7 ∼ 3.3V
Audio Serial Data Output Pin
“L” Output at Power-down mode.
Audio Serial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
Output Channel Clock Pin
“L” Output in Master Mode at Power-down mode.
Master/Slave Control Pin
“H”: Master Mode, “L”: Slave Mode
TDM Serial Data Input Pin
Should be connected to “L” in normal mode.
Master Clock Input Pin
Control Data Pin.
Control Data Clock Pin.
Chip Address Pin 0
Chip Address Pin 1
Interrupt Pin 0
Interrupt Pin 1
Power Down Mode Pin
“H”: Power up, “L”: Power down and reset. The AK4140 must be reset once upon
power-up.
Test Output Pin
Should be open.
Test Input Pin 1 (pull-down pin. typ: 150k ohm.)
Should be connected to DVSS.
Test Input Pin 2
Should be connected to DVSS.
Test Mode Pin 1 (pull-down pin. typ: 150k ohm.)
Should be connected to DVSS.
Test Mode Pin 2 (pull-down pin. typ: 150k ohm.)
Should be connected to DVSS.
MS0547-E-01
2007/03
-3-
ASAHI KASEI
[AK4140]
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 1)
Parameter
Power Supplies (Note 2)
Analog
Digital
Input Current, Any Pin Except Supply
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (powered applied)
Storage Temperature
Symbol
AVDD
DVDD
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
−0.3
−0.3
−20
−65
max
4.6
4.6
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
mA
V
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V;Note 1)
Parameter
Power Supplies
AVDD
DVDD
Symbol
AVDD
DVDD
min
2.7
2.7
typ
3.3
3.3
max
3.6
3.6
Units
V
V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
AUDIO CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; fs=48kHz; SCLK=64fs; Signal Frequency=1kHz; 16bit Data;
Measurement frequency=50Hz ∼ 13kHz; unless otherwise specified)
Parameter
Min
typ
max
Units
Resolution
16
Bits
Input Voltage
100
mVrms
S/(N+D)
(1kHz, 100% modulation)
mono
0.13
%
(1kHz, 66% modulation L or R) Stereo
0.13
%
(1kHz, 100% modulation)
SAP
0.86
%
S/N
(input off)
mono
73
dB
(A-weighted)
(input off) Stereo
73
dB
(input off)
SAP
80
dB
Interchannel Isolation
20
35
dB
Frequency response (50~12kHz)
mono
-1
1
dB
(50~12kHz)
Stereo
-1
1
dB
(50~9kHz)
SAP
-1
1
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”): VDD
Power down mode (PDN pin = “L”): VDD
(Note 3)
50
10
80
100
mA
μA
Note 3. All digital input pins are held to VSS.
MS0547-E-01
2007/03
-4-
ASAHI KASEI
[AK4140]
FILTER CHARACTERISTICS (MONO/STEREO)
(Ta=-20∼ 85°C; AVDD=DVDD=2.7~3.6V, fs=48kHz)
Parameter
Symbol
min
typ
Digital Filter (LPF):
Passband
±1dB
PB
Group Delay
(Note 4)
GD
13
Digital Filter (HPF):
Frequency Response
−3dB
FR
1.0
−0.1dB
6.5
FILTER CHARACTERISTICS (SAP)
(Ta=-20∼ 85°C; AVDD=DVDD=2.7~3.6V, fs=48kHz)
Parameter
Symbol
min
typ
Digital Filter (LPF):
Passband
(Note 9) ±1dB
PB
Group Delay
(Note 4)
GD
24
Digital Filter (HPF):
Frequency Response
−3dB
FR
1.0
−0.1dB
6.5
max
Units
12
kHz
1/fs
Hz
Hz
max
Units
9
kHz
1/fs
Hz
Hz
Note 4. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 16bit data both channels to the output register for the device.
DC CHARACTERISTICS
(Ta=-20∼ 85°C; AVDD=DVDD=2.7~3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-400μA)
Low-Level Output Voltage
(Except SDA pin: Iout= 400μA)
(SDA pin: Iout= 3mA)
Input Leakage Current
Symbol
VIH
VIL
VOH
min
70%VDD
VDD-0.4
typ
-
Max
30%VDD
-
Units
V
V
V
VOL
VOL
Iin
-
-
0.4
0.4
± 10
V
V
μA
MS0547-E-01
2007/03
-5-
ASAHI KASEI
[AK4140]
SWITCHING CHARACTERISTICS
(Ta=-20∼ 85°C; AVDD=DVDD=2.7~3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
8.192
fCLK
Master Clock
256fs:
27
tCLKL
Pulse Width Low
27
tCLKH
Pulse Width High
12.288
fCLK
384fs:
20
tCLKL
Pulse Width Low
20
tCLKH
Pulse Width High
16.384
fCLK
512fs:
16
tCLKL
Pulse Width Low
16
tCLKH
Pulse Width High
24.576
fCLK
768fs:
11
tCLKL
Pulse Width Low
11
tCLKH
Pulse Width High
LRCK Timing (Slave Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
Duty Cycle
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
“H” time
“L” time
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
“H” time
“L” time
LRCK Timing (Master Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
Duty Cycle
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
“H” time
(Note 5)
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
“H” time
(Note 5)
typ
max
Units
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
18.432
24.576
36.864
fs
Duty
32
45
48
55
kHz
%
fs
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
fs
tLRH
tLRL
32
1/128fs
1/128fs
48
kHz
ns
ns
fs
Duty
32
48
kHz
%
fs
tLRH
32
48
kHz
ns
fs
tLRH
32
48
kHz
ns
50
1/8fs
1/4fs
Note 5. “L” time at I2S format.
MS0547-E-01
2007/03
-6-
ASAHI KASEI
Parameter
Audio Interface Timing (Slave mode)
Normal mode (TDM1=“L”, TDM0=“L”)
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
(Note 6)
SCLK “↑” to LRCK Edge
(Note 6)
2
LRCK to SDTO(MSB) (Except I S mode)
SCLK “↓” to SDTO
TDM256 mode (TDM1=“L”, TDM0=“H”)
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
(Note 6)
SCLK “↑” to LRCK Edge
(Note 6)
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
TDM128 mode (TDM1=“H”, TDM0=“H”)
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
(Note 6)
SCLK “↑” to LRCK Edge
(Note 6)
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
[AK4140]
Symbol
min
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
160
65
65
30
30
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
MS0547-E-01
typ
max
Units
35
35
ns
ns
ns
ns
ns
ns
ns
20
10
10
20
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2007/03
-7-
ASAHI KASEI
Parameter
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDM256 mode (TDM1=“L”, TDM0=“H”)
SCLK Frequency
SCLK Duty
(Note 7)
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
TDM128 mode (TDM1=“H”, TDM0=“H”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
Power-Down & Reset Timing
PDN Pulse Width
(Note 8)
PDN “↑” to SDTO valid
(Note 9)
[AK4140]
Symbol
fBCK
dBCK
tMBLR
tBSD
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
tPD
tPDV
min
typ
max
Units
20
40
Hz
%
ns
ns
64fs
50
−20
−40
12
20
Hz
%
ns
ns
ns
ns
12
20
Hz
%
ns
ns
ns
ns
256fs
50
−12
−20
10
10
128fs
50
−12
−20
10
10
150
ns
1/fs
516
Note 6. SCLK rising edge must not occur at the same time as LRCK edge.
Note 7. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 8. The AK4140 can be reset by bringing the PDN pin = “L”.
Note 9. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Parameter
Control Interface Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 10)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
Symbol
Min
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
typ
max
Units
1.3
0.6
400
-
kHz
μs
μs
1.3
0.6
0.6
0
0.1
0.6
0
0.3
0.3
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
0
400
pF
Note 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS0547-E-01
2007/03
-8-
ASAHI KASEI
[AK4140]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
SCLK
VIL
tBCKH
tBCKL
Clock Timing (Normal mode)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
SCLK
VIL
tBCKH
tBCKL
Clock Timing (TDM256/TDM128A/B mode)
MS0547-E-01
2007/03
-9-
ASAHI KASEI
[AK4140]
VIH
LRCK
VIL
tBLR
tLRB
VIH
SCLK
VIL
tLRS
tBSD
SDTO
50%VDD
Audio Interface Timing (Slave mode, Normal Mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
SCLK
VIL
tBSD
SDTO
50%VDD
tSDS
tSDH
VIH
TDMIN
VIL
Audio Interface Timing (Slave mode, TDM256/TDM128A/B Mode)
MS0547-E-01
2007/03
- 10 -
ASAHI KASEI
[AK4140]
50%VDD
LRCK
tMBLR
dBCK
SCLK
50%VDD
tBSD
SDTO
50%VDD
Audio Interface Timing (Master mode, Normal Mode)
50%VDD
LRCK
tMBLR
50%VDD
SCLK
tBSD
SDTO
50%VDD
tSDS
tSDH
VIH
TDMIN
VIL
Audio Interface Timing (Master mode, TDM256/TDM128A/B Mode)
VIH
PDN
VIL
tPDV
SDTO
50%VDD
tPD
PDN
VIL
Power Down & Reset Timing
MS0547-E-01
2007/03
- 11 -
ASAHI KASEI
[AK4140]
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
I2C Bus mode Timing
MS0547-E-01
2007/03
- 12 -
ASAHI KASEI
[AK4140]
OPERATION OVERVIEW
„ System reset and Power-down Mode
The AK4140 should be reset once by bringing PDN PIN = “L” upon power-up.
PDN pin: Power down pin
“H”: Normal operation
“L”: Device power down & reset.
„ System Clock
The external clocks required to operate the AK4140 are MCLK, LRCK and SCLK. The AK4140 supports 256fs, 384fs,
512fs and 768fs as master clock (MCLK). The CKS1/0 bits select MCLK frequency. The AK4140 should be reset by
PDN pin= “L” after threse clocks are provided. If the external clocks are not present, place the AK4140 in power-down
mode. After exiting reset at power-up etc., the AK4140 remains in power-down mode until MCLK and LRCK are input.
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
768fs
12.2880MHz 16.3840MHz
24.576MHz
16.9344MHz 22.5792MHz
33.8688MHz
18.4320MHz 24.5760MHz
36.8640MHz
Table 1. System clock example (Slave mode)
CKS1
bit
0
0
1
1
SCLK
64fs
128fs
2.0480MHz 4.0960MHz
2.8224MHz 5.6448MHz
3.0720MHz 6.1440MHz
CKS0
MCLK
bit
0
256fs
(default)
1
384fs
0
512fs
1
768fs
Table 2. Master clock frequency select
„ Audio Interface Format
The AK4140 supports 16 types of audio data interface selected by the TDM1-0, DIF bits and M/S pin as shown in Table
3. In all formats the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of
SCLK.
In normal mode, Mode 0-1 are the slave mode, and SCLK is available up to 128fs. SCLK outputs 64fs clock in Mode 2-3.
In TDM256 mode, SCLK should be fixed to 256fs. In the slave mode, “H” time and “L” time of LRCK should be 1/256fs
at least. In the master mode, “H” time (“L” time at I2S mode) of LRCK is 1/8fs typically.
In TDM128A mode, SCLK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be
1/128fs at least. In the master mode, “H” time (“L” time at I2S mode) of LRCK is 1/4fs typically.
In TDM128B mode, SCLK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be
1/128fs at least. In the master mode, “H” time (“L” time at I2S mode) of LRCK is 1/8fs typically.
MS0547-E-01
2007/03
- 13 -
ASAHI KASEI
[AK4140]
TDM1
bit
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TDM0
bit
M/S
pin
DIF
bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Normal
(2ch)
0
TDM256
(max: 8ch)
0
TDM128A
(max: 4ch)
1
TDM128B
(max: 8ch)
1
0
1
0
1
1
0
0
1
0
1
1
SDTO
16bit, MSB justified
16bit, I2S Compatible
16bit, MSB justified
16bit, I2S Compatible
16bit, MSB justified
16bit, I2S Compatible
16bit, MSB justified
16bit, I2S Compatible
16bit, MSB justified
16bit, I2S Compatible
16bit, MSB justified
16bit, I2S Compatible
16bit, MSB justified
16bit, I2S Compatible
16bit, MSB justified
16bit, I2S Compatible
LRCK
I/O
H/L
I
L/H
I
H/L
O
L/H
O
I
↑
I
↓
O
↑
O
↓
I
↑
I
↓
O
↑
O
↓
I
↑
I
↓
O
↑
O
↓
SCLK
I/O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
32-128fs
32-128fs
64fs
64fs
256fs
256fs
256fs
256fs
128fs
128fs
128fs
128fs
128fs
128fs
128fs
128fs
Table 3 Audio Interface Formats (default : Mode 0)
LRCK
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
SCLK(64fs
SDTO1/2(o)
15 14
1
0
15 14
1
0
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0, 2 Timing (Normal mode, MSB justified)
LRCK
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
SCLK(64fs
SDTO1/2(o)
15
2
15:MSB, 0:LSB
1
0
15
Lch Data
2
1
0
Rch Data
Figure 2. Mode 1, 3 Timing (Normal mode, I2S Compatible)
MS0547-E-01
2007/03
- 14 -
ASAHI KASEI
[AK4140]
256 BICK
LRCK (Mode 6)
LRCK (Mode 4)
SCLK (256fs)
SDTO1
15 14
0
15 14
0
L1
R1
32 BICK
32 BICK
15 14
Figure 3. Mode 4, 6 Timing (TDM256 mode, MSB justified)
256 BICK
LRCK (Mode 7)
LRCK (Mode5)
SCLK (256fs)
SDTO1
15
0
15
0
L1
R1
32 BICK
32 BICK
23
Figure 4. Mode 5, 7 Timing (TDM256 mode, I2S Compatible)
128 BICK
LRCK (Mode 10)
LRCK (Mode 8)
SCLK (128fs)
SDTO1
15 14
0
15 14
0
L1
R1
32 BICK
32 BICK
15 14
Figure 5. Mode 8, 10 Timing (TDM128A mode, MSB justified)
128 BICK
LRCK (Mode 11)
LRCK (Mode 9)
SCLK (128fs)
SDTO1
15 14
0
15 14
0
L1
R1
32 BICK
32 BICK
15
Figure 6. Mode 9, 11 Timing (TDM128A mode, I2S Compatible)
MS0547-E-01
2007/03
- 15 -
ASAHI KASEI
[AK4140]
128 BICK
LRCK (Mode 14)
LRCK (Mode 12)
SCLK (128fs)
SDTO1
15 14
0 15 14
0
L1
R1
16 BICK
16 BICK
15 14
Figure 7. Mode 12, 14 Timing (TDM128B mode, MSB justified)
128 BICK
LRCK (Mode 15)
LRCK (Mode 13)
SCLK (128fs)
SDTO
15
0 15
0
L1
R1
16 BICK
16 BICK
15
Figure 8. Mode 13, 15 Timing (TDM128B mode, I2S Compatible)
MS0547-E-01
2007/03
- 16 -
ASAHI KASEI
[AK4140]
„ Cascade TDM Mode
The AK4140 supports cascading connection of up to four devices in a daisy chain configuration at TDM256 mode. In this
mode, SDTO pin of device #N is connected to TDMIN pin of device #(N+1). The device can output up to 8ch TDM data
multiplexed with TDMIN data. Figure 8 shows a connection example of a daisy chain.
AK4140 #1
MCLK
256fs or 512fs
LRCK
48kHz
SCLK
256fs
TDMIN
GND
SDTO
MCLK
AK4140 #2
LRCK
SCLK
TDMIN
(TDMIN of
AK4140 #3)
SDTO
Figure 9. Cascade TDM Connection Diagram
256 BICK
LRCK
SCLK (256fs)
#1 SDTO(o)
= #2 TDMIN(i)
#2 SDTO(o)
= #3 TDMIN(i)
#3 SDTO(o)
= #4 TDMIN(i)
#4 SDTO(o)
15 14
0
15 14
0
L #1
R #1
32 BICK
32 BICK
15 14
0
15 14
0
15 14
15 14
0
15 14
0
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
15 14
0
15 14
0
15 14
0
15 14
0
15 14
15 14
0
15 14
0
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
15 14
0
15 14
0
15 14
0
15 14
0
15 14
0
15 14
0
15 14
15 14
0
15 14
0
L #4
R #4
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
15 14
Figure 10. Cascade TDM Timing (4devices)
MS0547-E-01
2007/03
- 17 -
ASAHI KASEI
[AK4140]
„ Audio Sampling Rate
The AK4140 supports 3 sampling rates as 32kHz, 44.1kHz and 48kHz.
FS1
0
0
1
1
FS0
0
1
0
1
Sampling rate
32kHz
44.1kHz
48kHz
(Reserved)
(default)
Table 4. Sampling rate select
„ Digital High Pass Filter
The AK4140 has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1Hz
(@fs=48kHz) and scales with sampling rate (fs).
„ Pilot/SAP/Noise Detection (read)
PILOT bit: Pilot Signal Detection
Pilot signal
Detected
Not detected
PILOT bit
1
0
(default)
Table 5. Pilot Signal Detection
0Æ1:
Pilot Signal Level ≥ Pilot Threshold Level (PTHR1,0 bit)
+ Pilot Hysteresis Level (PHYS1,0 bit) / 2 (in dB)
1Æ0:
Pilot Signal Level < Pilot Threshold Level (PTHR1,0 bit)
- Pilot Hysteresis Level (PHYS1,0 bit) / 2 (in dB)
SAP bit: SAP Signal Detection
SAP signal
Detected
Not detected
SAP bit
1
0
(default)
Table 6. SAP Signal Detection
0Æ1:
SAP Signal Level ≥ SAP Threshold Level (STHR1,0 bit)
+ SAP Hysteresis Level (SHYS1,0 bit) / 2 (in dB)
1Æ0:
SAP Signal Level <SAP Threshold Level (STHR1,0 bit)
- SAP Hysteresis Level (SHYS1,0 bit) / 2 (in dB)
MS0547-E-01
2007/03
- 18 -
ASAHI KASEI
[AK4140]
NOISE bit: Noise Detection
noise signal
Detected
Not detected
NOISE bit
1
0
Table 7. Noise Detection
0Æ1:
Noise Level ≥ Noise Threshold Level (NTHR1,0 bit)
+ Noise Hysteresis Level (NHYS1,0 bit) / 2 (in dB)
1Æ0:
Noise Level
< Noise Threshold Level (NTHR1,0 bit)
- Noise Hysteresis Level (NHYS1,0 bit) / 2 (in dB)
Hysteresis Level
(Controlled by PHYS1-0,
SHYS1-0, NHYS1-0 bits)
1
Output (PILOT/SAP/NOISE bit)
Threshold Level
(Controlled by PTHR1-0,
STHR1-0, NTHR1-0 bits)
0
Input Level (Pilot/SAP/Noise) [dB]
Figure 11. Pilot, SAP, Noise Detection Function
„ Pilot/SAP/Noise Detection Threshold Control
PTHR1 bit
0
0
1
1
PTHR0 bit
0
1
0
1
Threshold Level (typ)
-1.5dB
-3dB
-6dB (default)
-9dB
0dB= full scale of 1fH Pilot tone
Table 8. Pilot(fH) Threshold Level Control
MS0547-E-01
2007/03
- 19 -
ASAHI KASEI
[AK4140]
STHR1 bit
0
0
1
1
STHR0 bit
0
1
0
1
Threshold Level (typ)
-1dB
-4.5dB
-9dB (default)
-13.5dB
0dB= full scale of 5fH SAP carrier
Table 9. SAP(5fH) Threshold Level Control
NTHR1 bit
0
0
1
1
NTHR0 bit
0
1
0
1
Threshold Level (typ)
-2dB
-7dB
-13dB (default)
-20dB
0dB= full scale of 5fH SAP carrier, BW=5fH+/-10kHz
Table 10. Noise(5fH) Threshold Level Control
„ Pilot/SAP/Noise Detection On/Off Hysteresis Range
PHYS1 bit
0
0
1
1
PHYS0 bit
0
1
0
1
Hysteresis Level (typ)
3dB
6dB (default)
9dB
12dB
0dB= full scale of 1fH Pilot tone
Table 11. Pilot(fH) Hysteresis Level Control
SHYS1 bit
0
0
1
1
SHYS0 bit
0
1
0
1
Hysteresis Level (typ)
2dB
4dB (default)
6dB
8dB
0dB= full scale of 5fH SAP carrier
Table 12. SAP(5fH) Hysteresis Level Control
NHYS1 bit
0
0
1
1
NHYS0 bit
0
1
0
1
Hysteresis Level (typ)
1dB
2.5dB (default)
4dB
6.5dB
0dB= full scale of 5fH SAP carrier, BW=5fH+/-10kHz
Table 13. Noise(5fH) Hysteresis Level Control
MS0547-E-01
2007/03
- 20 -
ASAHI KASEI
[AK4140]
„ Output control
The OUT4-0 bits and the status bits (PILOT, SAP, NOISE bits) control the Output Mode.
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Control bit
OUT4
OUT3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Operation
OUT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OUT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
OUT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Fix to Mono
Fix to Stereo
Fix to Mono/ SAP
Fix to Mono/ SAP*
Fix to SAP
Fix to SAP*
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Mono ⇔ Stereo Auto
Mono ⇔ Stereo ⇔ Mono/ SAP Auto 1(NOISE ignored)
Mono ⇔ Stereo ⇔ Mono/ SAP Auto 2
Mono ⇔ Stereo ⇔ Mono/ SAP ⇔ Mono/ SAP* Auto
Mono ⇔ Stereo ⇔ SAP Auto 1(NOISE ignored)
Mono ⇔ Stereo ⇔ SAP Auto 2
Mono ⇔ Stereo ⇔ SAP ⇔ SAP* Auto (default)
MONO ⇔ Mono/ SAP Auto 1(NOISE ignored)
MONO ⇔ Mono/ SAP Auto 2
MONO ⇔ Mono/ SAP ⇔ Mono/ SAP* Auto
MONO ⇔ SAP Auto 1(NOISE ignored)
MONO ⇔ SAP Auto 2
MONO ⇔ SAP ⇔ SAP* Auto
SAP ⇔ SAP* Auto
Mono/ SAP ⇔ Mono/ SAP* Auto
Table 14. Output Control (OUT4-0)
MS0547-E-01
2007/03
- 21 -
ASAHI KASEI
[AK4140]
Mode
in Table 14
Operation
0
Fix Mono
1
Fix Stereo
2
Fix
Mono/SAP
3
Fix
Mono/SAP*
4
Fix SAP
5
Fix SAP*
Status
PILOT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MS0547-E-01
SAP
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
NOISE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Lch
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L
L
L
L
L
L
L
L
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
SAP
SAP
SAP
SAP
SAP
SAP
SAP
SAP
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
Rch
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
R
R
R
R
R
R
R
R
SAP
SAP
SAP
SAP
SAP
SAP
SAP
SAP
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
SAP
SAP
SAP
SAP
SAP
SAP
SAP
SAP
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
SAP*
2007/03
- 22 -
ASAHI KASEI
[AK4140]
Mode
in Table 14
16
17
18
19
20
21
Operation
Mono
⇔
Stereo
Auto
Mono
⇔
Stereo
⇔
MONO/SAP
Auto 1
Mono
⇔
Stereo
⇔
MONO/SAP
Auto 2
Mono
⇔
Stereo
⇔
MONO/SAP
⇔
MONO/SAP*
Auto
Mono
⇔
Stereo
⇔
SAP
Auto 1
Mono
⇔
Stereo
⇔
SAP
Auto 2
Status
PILOT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MS0547-E-01
SAP
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
NOISE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Lch
L+R
L+R
L+R
L+R
L
L
L
L
L+R
L+R
L+R
L+R
L
L
L+R
L+R
L+R
L+R
L+R
L+R
L
L
L+R
L
L+R
L+R
L+R
L+R
L
L
L+R
L+R
L+R
L+R
SAP
SAP
L
L
SAP
SAP
L+R
L+R
SAP
L+R
L
L
SAP
L
Rch
L+R
L+R
L+R
L+R
R
R
R
R
L+R
L+R
SAP
SAP
R
R
SAP
SAP
L+R
L+R
SAP
L+R
R
R
SAP
R
L+R
L+R
SAP
SAP*
R
R
SAP
SAP*
L+R
L+R
SAP
SAP
R
R
SAP
SAP
L+R
L+R
SAP
L+R
R
R
SAP
R
2007/03
- 23 -
ASAHI KASEI
[AK4140]
Mode
in Table 14
22
23
24
25
26
27
Operation
Mono
⇔
Stereo
⇔
SAP
⇔
SAP*
Auto
Mono
⇔
Mono/SAP
Auto 1
Mono
⇔
Mono/SAP
Auto 2
Mono
⇔
Mono/SAP
⇔
Mono/SAP*
Auto
Mono
⇔
SAP
Auto 1
Mono
⇔
SAP
Auto 2
Status
PILOT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MS0547-E-01
SAP
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
NOISE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Lch
L+R
L+R
SAP
SAP*
L
L
SAP
SAP*
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
SAP
SAP
L+R
L+R
SAP
SAP
L+R
L+R
SAP
L+R
L+R
L+R
SAP
L+R
Rch
L+R
L+R
SAP
SAP*
R
R
SAP
SAP*
L+R
L+R
SAP
SAP
L+R
L+R
SAP
SAP
L+R
L+R
SAP
L+R
L+R
L+R
SAP
L+R
L+R
L+R
SAP
SAP*
L+R
L+R
SAP
SAP*
L+R
L+R
SAP
SAP
L+R
L+R
SAP
SAP
L+R
L+R
SAP
L+R
L+R
L+R
SAP
L+R
2007/03
- 24 -
ASAHI KASEI
[AK4140]
Mode
in Table 14
28
29
30
Operation
Status
PILOT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mono
⇔
SAP
⇔
SAP*
Auto
SAP
⇔
SAP*
Auto
Mono/SAP
⇔
Mono/SAP*
Auto
SAP
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
NOISE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Lch
L+R
L+R
SAP
SAP*
L+R
L+R
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
L+R
L+R
L+R
L+R
L+R
L+R
L+R
L+R
Rch
L+R
L+R
SAP
SAP*
L+R
L+R
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
SAP
SAP*
: These status bits are not reflected to the output data.
SAP*: -7dB attenuated.
Table 15 Output Control
„ Output Lch/Rch Swapping Operation
When the LRR bit is “1”, the output data is swapped between Lch and Rch. When the LR bit is “0”, the output data is as
Table 15.
LR bit
0
1
Mode
Normal
Operation
Output Lch/Rch data as Table 15
Swap Lch/Rch data as Table 15
Swap
Table 16. Output Channel Control
MS0547-E-01
2007/03
- 25 -
ASAHI KASEI
[AK4140]
„ Soft Transition Operation
When the STR bit is “1”, the transition among MONO, Stereo and SAP is operated using soft muting function. When the
STR bit is “0”, the transition among MONO, Stereo and SAP is operated immediately.
Control Timing
Output Data
at STR bit = “0”
MONO
SAP
(2)
0dB
Output Data
at STR bit = “1”
MONO
SAP
-∞dB
(1)
(1)
Notes:
(1) Transition time. 768 LRCK cycles (768/fs) for both muting and unmuting.
(2) When the STR bit = “0”, a noise may occur at transition.
Figure 12. Soft Transition Control (ex. MONO to SAP)
MS0547-E-01
2007/03
- 26 -
ASAHI KASEI
[AK4140]
„ Stereo Volume Control
The AK4140 has a digital output volume (25 levels, 1dB step, Mute). The L4-0 and R4-0 bits can set the volume. The
volume is placed in front of a stereo matrix block. The input data of the digital volume is changed from +12 to –12dB or
MUTE. When the VOLC bit = “1” (default), the L4-0 bits control both Lch and Rch attenuation levels. When the VOLC
bit = “0”, the L4-0 bits control Lch level and R4-0 bits control Rch level. This volume has a soft transition function. When
changing levels, transitions are executed with soft changes; thus no switching noise occurs during these transitions. The
transition time of 1 level and all levels are shown in Table 17.
Transition Time
1 Level
+12 to -12
8LRCK
192LRCK
Table 17. ATT Transition Time
L4
1
1
…
0
0
0
…
0
0
0
L3
1
1
…
1
1
1
…
0
0
0
L2
0
0
…
1
1
1
…
0
0
0
L1
0
0
…
1
0
0
…
1
0
0
L0
1
0
…
0
1
0
…
0
1
0
Gain
+12dB
+11dB
…
+1dB
0dB
-1dB
…
-11dB
-12dB
Mute (default)
Table 18. Volume (Lch)
R4
1
1
…
0
0
0
…
0
0
0
R3
1
1
…
1
1
1
…
0
0
0
R2
0
0
…
1
1
1
…
0
0
0
R1
0
0
…
1
0
0
…
1
0
0
R0
1
0
…
0
1
0
…
0
1
0
Gain
+12dB
+11dB
…
+1dB
0dB
-1dB
…
-11dB
-12dB
Mute (default)
Table 19. Volume (Rch)
MS0547-E-01
2007/03
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ASAHI KASEI
[AK4140]
„ Soft Mute Operation (default = Mute)
When the SMUTE bit goes to “1”, the output signal is attenuated from 0dB to -∞dB during 768 LRCK cycles. When the
SMUTE bit returns to “0”, the mute is cancelled and the attenuation gradually changes to 0dB during 768 LRCK cycles.
If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returns to 0dB. This return takes
the same number of clock cycles as the point at which the soft mute cancel was initiated, i.e. if 500 clock cycles passed
and then a soft mute cancel was issued, it will take 500 clock cycles to return to 0dB. The soft mute is used primarily when
changing the signal source.
SMUTE
0dB
Attenuation Level
at SDTO
-∞dB
(2)
(1)
(1)
Notes:
(1) Transition time. 768 LRCK cycles (768/fs).
(2) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued
and returned to 0dB by the same number of clock cycles.
Figure 13. Soft Mute
MS0547-E-01
2007/03
- 28 -
ASAHI KASEI
[AK4140]
„ Status Change Handling
The INT1/0 pin goes “H” when one of following three statuses changes without masking. Each change of status can be
masked by MPLT bit, MSP bit and MNS bit. When masked, the interrupt event does not affect the operation of the INT1/0
pin (the masks do not affect the status registers). When the PDN pin= “L” or RSTN= “0”, the INT pin goes to “L”.
1. PILOT bit : PILOT detection
Goes “1” when the Pilot signal is detected.
2. SAP bit
: SAP detection
Goes “1” when the SAP signal is detected.
3. NOISE bit
: Noise detection
Goes “1” when the noise is detected.
Once INT1/0 pin goes to “H”, it remains “H” for the hold time controlled by the INT11-10, INT01-00 bits.
INT01 bit
0
0
1
1
INT00 bit
0
1
0
1
INT0 pin Hold time
1LRCK cycle
1024 LRCK cycle
4096 LRCK cycle
Holds “H” until the status register is read.
Table 20. INT0 pin Hold Time Control
INT11 bit
0
0
1
1
INT10 bit
0
1
0
1
INT1 pin Hold time
1LRCK cycle
1024 LRCK cycle
4096 LRCK cycle
Holds “H” until the status register is read.
Table 21. INT1 pin Hold Time Control
Event
(PILOT, SAP or NOISE bit)
Hold Time
INT1/0 pin
Hold Time
Internal Counter Initialized
Figure 14. INT pin Timing
MS0547-E-01
2007/03
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ASAHI KASEI
[AK4140]
PDN pin = “L” to “H”
Initialize
Unmask
INT pin= “H”
No
Yes
Read Status
(STEREO=”1”/”0”,
SAP=”1”/”0”, etc.)
Each Setting
(set to stereo/mono/SAP mode
by OUT4-0 bits)
Figure 15. Status Change Handling Sequence Example
MS0547-E-01
2007/03
- 30 -
ASAHI KASEI
[AK4140]
„ Control Interface (I2C-bus)
AK4140 supports a fast-mode I2C-bus system (max : 400kHz).
1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4140 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device
pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated
by the master device.
1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 16. Data transfer
1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 17. START and STOP conditions
MS0547-E-01
2007/03
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ASAHI KASEI
[AK4140]
1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4140 will
generates an acknowledge after each byte has been received.
In the read mode, the slave, the AK4140 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP
condition.
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 18. Acknowledge on the I2C-bus
1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the
transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the
SDA line.
The most significant five bits of the slave address are fixed as “10000”. The next two bits are CAD1 and CAD0 (device
address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0 pin)
set them. The eighth bit (LSB) of the first byte (R/W bit) defines whether the master requests a write or read condition. A
“1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed.
1
0
0
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins.)
Figure 19. The First Byte
MS0547-E-01
2007/03
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ASAHI KASEI
[AK4140]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4140.
After receipt the start condition and the first byte, the AK4140 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4140. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 20. The Second Byte
After receipt the second byte, the AK4140 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 21. Byte structure after the second byte
The AK4140 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4140 generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceed 08H prior to generating the stop condition, the address counter will “roll over” to 00H
and the previous data will be overwritten.
S
T
A
R
T
SDA
Register
Address(n)
Slave
Address
S
T
Data(n+x) O
P
Data(n+1)
Data(n)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 22. WRITE Operation
MS0547-E-01
2007/03
- 33 -
ASAHI KASEI
[AK4140]
3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4140.
After transmission of a data, the master can read next address’s data by generating the acknowledge instead of terminating
the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address counter is
incremented by one, and the next data is taken into next address automatically. If the address exceed 08H prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The AK4140 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
3-1. CURRENT ADDRESS READ
The AK4140 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1.
After receipt of the slave address with R/W bit set to “1”, the AK4140 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does
not generate an acknowledge to the data but generate the stop condition, the AK4140 discontinues transmission
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 23. CURRENT ADDRESS READ
3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4140 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge to the data but generate the stop condition, the AK4140 discontinues
transmission.
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 24. RANDOM READ
MS0547-E-01
2007/03
- 34 -
ASAHI KASEI
[AK4140]
„ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
CKS1
CKS0
TDM1
TDM0
DIF
0
SMUTE
RSTN
01H
CLK & Power Down
Control
Output Control
FS1
FS0
LR
OUT4
OUT3
OUT2
OUT1
OUT0
02H
Threshold Control
STR
0
NTHR1
NTHR0
STHR1
STHR0
PTHR1
PTHR0
03H
Hysteresis Control
ATTR
ATTL
NHYS1
NHYS0
SHYS1
SHYS0
PHYS1
PHYS0
04H
Lch ATT
VOLC
0
0
L4
L3
L2
L1
L0
05H
Rch ATT
0
0
0
R4
R3
R2
R1
R0
06H
Signal Status
0
0
0
0
0
NOISE
SAP
PILOT
07H
INT0 Mask
0
0
0
INT01
INT00
MNS0
MSP0
MPLT0
08H
INT1 Mask
0
0
0
INT11
INT10
MNS1
MSP1
MPLT1
00H
When the PDN pin goes “L”, the registers are initialized to their default values.
While the PDN pin =“H”, all registers can be accessed.
Do not write any data to the register over 08H.
When RSTN bit goes “0”, the internal timing is reset and registers are not initialized to their default values.
MS0547-E-01
2007/03
- 35 -
ASAHI KASEI
[AK4140]
Reset & Initialize
Addr
Register Name
00H CLK & Power Down Control
R/W
Default
D7
D6
D5
D4
CKS1
CKS0
TDM1
TDM0
R/W
0
R/W
0
R/W
0
R/W
0
D3
D2
D1
D0
DIF
0
SMUTE
RSTN
R/W
0
R/W
0
R/W
1
R/W
1
RSTN: Timing Reset & Register Initialize
0: Reset & Initialize
1: Normal Operation (Default)
SMUTE: Soft Mute Enable
0: Normal Operation
1: Soft-muted (Default)
DIF, TDM1-0: Data Interface Control
Default: 16bit, MSB justified. Please refer Table 3.
CKS1-0: Master Clock Frequency Select
Default: 256fs
Output Control
Addr
01H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Output Control
FS1
FS0
LR
OUT4
OUT3
OUT2
OUT1
OUT0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
R/W
Default
OUT4-0: Output Control
Please refer Table 14.
LR: Output Channel Control
Please refer Table 16.
FS1-0: Sampling Rate Select
Default: 48kHz
MS0547-E-01
2007/03
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ASAHI KASEI
[AK4140]
Threshold Control
Addr
02H
Register Name
D7
D6
Threshold Control
STR
0
R/W
Default
R/W
0
RD
0
D5
D4
NTHR1 NTHR0
R/W
1
R/W
0
D3
D2
D1
D0
STHR1
STHR0
PTHR1
PTHR0
R/W
1
R/W
0
R/W
1
R/W
0
PTHR1-0: Pilot Detection Threshold Level Control
STHR1-0: SAP Detection Threshold Level Control
NTHR1-0: Noise Detection Threshold Level Control
STR: Switching Sequence Control
Hysteresis Control
Addr
03H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Hysteresis Control
ATTR
ATTL
NHYS1
NHYS0
SHYS1
SHYS0
PHYS1
PHYS0
RD
0
RD
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
Default
ATTR: Rch Attenuation Control
0: 0dB
1: -6dB (Default)
ATTL: Lch Attenuation Control
0: 0dB
1: -6dB (Default)
PHYS1-0: Pilot Detection Hysteresis Level Control
SHYS1-0: SAP Detection Hysteresis Level Control
NHYS1-0: Noise Detection Hysteresis Level Control
MS0547-E-01
2007/03
- 37 -
ASAHI KASEI
[AK4140]
Lch Volume control
Addr
04H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Lch ATT
VOLC
0
0
L4
L3
L2
L1
L0
R/W
1
RD
0
RD
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Default
L4-0: Lch Volume Control
VOLC: Lch/Rch Volume Common Control Enable
0: Independent Control. L4-0 and R4-0 bits control Lch and Rch independently.
1: Common Control (default). L4-0 bits control both Lch and Rch. R4-0 bits are ignored.
Rch Volume control
Addr
05H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Rch ATT
0
0
0
R4
R3
R2
R1
R0
RD
0
RD
0
RD
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Default
R4-0: Rch Volume Control when VOLC bit = “0”. Don’t care when VOLC bit = “1”.
Signal Status
Addr
06H
Register Name
Signal Status
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
NOISE
SAP
PILOT
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
PILOT: Pilot signal status
0: Pilot signal.
1: Pilot signal is detected.
SAP: SAP signal status
0: No SAP signal.
1: SAP signal is detected.
NOISE: NOISE status
0: No noise.
1: Noise is detected.
MS0547-E-01
2007/03
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ASAHI KASEI
[AK4140]
INT Mask
Addr
07H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
INT0 Mask
0
0
0
INT01
INT00
MNS0
MSP0
MPLT0
RD
0
RD
0
RD
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
Default
MPLT0: Mask enable for PILOT bit
0: Mask disable
1: Mask enable (Default)
MSP0: Mask enable for SAP bit
0: Mask disable
1: Mask enable (Default)
MNS0: Mask enable for NOISE bit
0: Mask disable
1: Mask enable (Default)
When mask is set to “1”, corresponding event does not affect INT0 pin operation.
INT01-00: INT0 Hold Time Control
Addr
08H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
INT1 Mask
0
0
0
INT11
INT10
MNS1
MSP1
MPLT1
RD
0
RD
0
RD
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
Default
MPLT1: Mask enable for PILOT bit
0: Mask disable
1: Mask enable (Default)
MSP1: Mask enable for SAP bit
0: Mask disable
1: Mask enable (Default)
MNS1: Mask enable for NOISE bit
0: Mask disable
1: Mask enable (Default)
When each mask bit is set to “1”, corresponding event does not affect INT1 pin operation.
INT11-10: INT1 Hold Time Control
MS0547-E-01
2007/03
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ASAHI KASEI
[AK4140]
SYSTEM DESIGN
Figure 25 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
2.2n
10u
+3.3V Analog
4.5MHz SIF
68n
0.1u
FILT
TST2
AVSS
TST1
AVDD
TSTI2
SIF
TSTI1
DVSS
0.1u
+3.3V Digital
AK4140
DVDD
PDN
SDTO
INT1
SCLK
INT0
LRCK
CAD1
MS
CAD0
fs
DSP
256fs
TSTO
+3.3V Digital
uP
10kohm
TDMIN
SCL
MCLK
SDA
10kohm
Figure 25. System Connection Example (CAD1/0 bit = “00”, Master Mode, Normal (Non-TDM) Mode.
MS0547-E-01
2007/03
- 40 -
ASAHI KASEI
[AK4140]
PACKAGE
24pin VSOP (Unit: mm)
1.25±0.2
*7.9±0.2
13
A
7.6±0.2
*5.6±0.2
24
12
1
0.22±0.1
0.65
0.15
+0.1
-0.05
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Material & Lead finish
Package molding compound: Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder plate (Pb Free)
MS0547-E-01
2007/03
- 41 -
ASAHI KASEI
[AK4140]
MARKING
AKM
AK4140VF
AAXXXX
Contents of AAXXXX
AA: Lot#
XXXX: Date Code
Revision History
Date (YY/MM/DD)
06/10/11
07/03/14
Revision
00
01
Reason
First Edition
Error Correction
Page
Contents
4
Error Correction
8
Error Correction
13
Absolute Maximum Ratings AVDD, DVDD
6.0V Æ 4.6V
I2C Bus Timing
tHD:DAT(max): 0.9 Æ BICK Æ SCLK
MS0547-E-01
2007/03
- 42 -
ASAHI KASEI
[AK4140]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0547-E-01
2007/03
- 43 -