ASAHI KASEI [AK4113] AK4113 192kHz 24bit DIR with 6:1 Selector GENERAL DESCRIPTION The AK4113 is a 24-bit stereo digital audio receiver that supports sampling rates up to 216kHz. The channel status bits decoder supports both consumer and professional modes. The AK4113 automatically detects non-PCM bit streams such as Dolby Digital, MPEG etc. When combined with the multi channel codec (AK4626 or AK4628), the two chips provide a system solution for Dolby Digital applications. Control of AK4113 is achieved though a µP or pin strapping (parallel mode). It is packaged in a space-saving 30-pin VSOP. * Dolby Digital is a trademark of Dolby Laboratories. FEATURES AES/EBU, IEC60958, S/PDIF, EIAJ CP1201 Compatible Low Jitter Analog PLL PLL Lock Range: 8k ∼ 216kHz Clock source: PLL or X'tal 6-channel Receiver Input and 1-channel Transmission Output (Through output) Auxiliary Digital Input De-emphasis for 32kHz, 44.1kHz and 48kHz Detection Functions - Non-PCM Bit Stream Detection - DTS-CD Bit Stream Detection - Sampling Frequency Detection (8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz) - Unlock & Parity Error Detection - Validity Detection - DAT Start ID Detection Up to 24bit Audio Data Format Audio Interface: Master or Slave Mode 40-bit Channel Status Buffer Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream Q-subcode Buffer for CD bit stream Serial µP Interface: I2C (max. 400kHz) or 4-wire Two Master Clock Outputs: 64fs/128fs/256fs/512fs Operating Voltage: 2.7 to 3.6V with 5V Logic Tolerance Small Package: 30pin VSOP Ta: - 40 ∼ 85°C MS0349-E-02 2005/08 -1- ASAHI KASEI [AK4113] AVSS AVDD R XTI XTO X'tal RX1 Oscillator RX2 RX3 RX4 Input Clock Recovery Clock MCKO1 Generator MCKO2 (BOUT) Selector RX5 DEM RX6 DAIF Audio Decoder I/F V/TX LRCK BICK SDTO DAUX PDN CSN DVDD Error & STATUS Detect AC-3/MPEG DVSS TVDD Detect INT0 Q-subcode buffer µP I/F CCLK CDTO CDTI INT1(C, UOUT) P/SN= “L” I2C Figure 1. Serial control mode AVSS AVDD R XTI XTO X'tal Oscillator RX1 Input RX5 Selector Clock Recovery Clock MCKO1 Generator MCKO2 DEM DAIF V Audio Decoder I/F DIF0 DIF1 LRCK BICK SDTO DIF2 DAUX IPS PDN OCKS0 DVDD DVSS TVDD AC-3/MPEG Detect Error & STATUS Detect INT0 INT1 OCKS1 CM0 CM1 FS96 P/SN=“H” Figure 2. Parallel control mode MS0349-E-02 2005/08 -2- ASAHI KASEI [AK4113] Ordering Guide AK4113VF AKD4113 -40 ~ +85 °C 30pin VSOP (0.65mm pitch) Evaluation board for AK4113 PIN Layout DVDD 1 30 CM0/CDTO/CAD1 DVSS 2 29 CM1/CDTI/SDA TVDD 3 28 OCKS1/CCLK/SCL V/TX 4 27 OCKS0/CSN/CAD0 XTI 5 26 MCKO1 XTO 6 25 MCKO2 PDN 7 24 DAUX R 8 23 BICK AVDD 9 22 SDTO AVSS 10 21 LRCK RX1 11 20 INT0 RX2/DIF0 12 19 FS96/I2C RX3/DIF1 13 18 P/SN RX4/DIF2 14 17 INT1 RX5 15 16 IPS/RX6 Top View MS0349-E-02 2005/08 -3- ASAHI KASEI [AK4113] PIN/FUNCTION No. 1 2 3 Pin Name DVDD DVSS TVDD V TX XTI XTO I/O O O I O Function Digital Power Supply Pin, 3.3V Digital Ground Pin Input Buffer Power Supply Pin, 3.3V or 5V Validity Flag Output Pin in Parallel control mode 4 Transmit channel (Through data) Output Pin in serial control mode 5 X'tal Input Pin 6 X'tal Output Pin Power-Down Mode Pin 7 PDN I When “L”, the AK4113 is powered-down and reset. External Resistor Pin 8 R This pin must be connected to AVSS via 15kΩ ±5% resistor. 9 AVDD Analog Power Supply Pin 10 AVSS Analog Ground Pin 11 RX1 I Receiver Channel #1 Pin (Internal Biased Pin) DIF0 I Audio Data Interface Format #0 Pin in parallel control mode 12 RX2 I Receiver Channel #2 Pin in serial control mode (Internal Biased Pin) DIF1 I Audio Data Interface Format #1 Pin in parallel control mode 13 RX3 I Receiver Channel #3 Pin in serial control mode (Internal Biased Pin) DIF2 I Audio Data Interface Format #2 Pin in parallel control mode 14 RX4 I Receiver Channel #4 Pin in serial control mode (Internal Biased Pin) 15 RX5 I Receiver Channel #5 Pin (Internal Biased Pin) IPS I Input Channel Select Pin in parallel control mode 16 RX6 I Receiver Channel #6 Pin (Internal Biased Pin) Interrupt #1 Pin (when BCU bit = “0”) U-bit Output Pin (when BCU bit = “1”, UCE bit = “0”) 17 INT1 O C-bit Output Pin (when BCU bit = “1”, UCE bit = “1”) Parallel/Serial Select Pin 18 I P/SN “L”: Serial control mode, “H”: Parallel control mode 96kHz Sampling Detect Pin in parallel control mode FS96 O This function is enabled when the input frequency of XTI is 24.576MHz. 19 “L”: fs=54kHz or less, “H”: fs=64kHz or more I2C Select Pin in Serial control mode. I2C I “L”: 4-wire Serial, “H”: I2C 20 INT0 O Interrupt #0 Pin 21 LRCK I/O Output Channel Clock Pin 22 SDTO O Audio Serial Data Output Pin 23 BICK I/O Audio Serial Data Clock Pin 24 DAUX I Auxiliary Audio Data Input Pin Master Clock #2 Output Pin (when BCU bit = “0”) 25 MCKO2 O Block Start Signal Output Pin (when BCU bit = “1”) 26 MCKO1 O Master Clock #1 Output Pin OCKS0 I Output Clock Select #0 Pin in parallel control mode 27 CSN I Chip Select Pin in serial control mode, I2C pin = “L” CAD0 I Chip Address #0 Pin in serial control mode, I2C pin = “H” Note 1. Do not allow digital input pins expect internal biased pins (RX1-6 pins) to float. MS0349-E-02 2005/08 -4- ASAHI KASEI No. [AK4113] Pin Name I/O Function OCKS1 I Output Clock Select #1 Pin in parallel control mode CCLK I Control Data Clock Pin in serial control mode, I2C pin = “L” SCL I Control Data Clock Pin in serial control mode, I2C pin = “H” CM1 I Master Clock Operation Mode #1 Pin in parallel control mode 29 CDTI I Control Data Input Pin in serial control mode, I2C pin = “L” Control Data Pin in serial control mode, I2C pin = “H” SDA I/O CM0 I Master Clock Operation Mode #0 Pin in parallel control mode 30 CDTO O Control Data Output Pin in serial control mode CAD1 I Chip Address #1 Pin in serial control mode, I2C pin = “H” Note 1. Do not allow digital input pins expect internal biased pins (RX1-6 pins) to float. 28 Handling of Unused Pin The unused I/O pin should be processed appropriately as below. Classification Analog Input Pin Name RX1, RX2/DIF0, RX3/DIF1, RX4/DIF2, RX5, RX6/IPS RX1, RX5 Digital Input Digital Output DAUX, XTI V/TX, XTO, INT0, INT1, MCKO1, MCKO2 I2C/FS96 CAD1/CDTO/CM0 MS0349-E-02 Setting These pins should be open in serial control mode. These pins should be open in parallel control mode. These pins should be connected to DVSS. These pins should be open. This pin should be open in parallel control mode. This pin should be open in serial control mode and 4-wire mode (I2C pin = “L”). 2005/08 -5- ASAHI KASEI [AK4113] Compare AK4112B with AK4113 1. Function Function RX Input Channel Serial control mode Parallel control mode PLL Lock Range Resistor value for R pin PLL Lock Time DTS-CD Bit Stream Detection DAT Start ID Detection Q-subcode Buffer for CD bit Stream fs Detection in serial control mode Serial µP Interface Error Handling Pins Master Clock Output Frequency Channel Status Bit MCKO2 Clock Source in serial control mode Audio I/F at Reset in serial control mode Package AK4112B 4ch 1ch 22kHz to 108kHz 18k ± 1% AK4113 6ch 2ch 8kHz to 216kHz 15k ± 5% FAST bit =“0”: ≤ (15ms+384/fs) ≤ 20ms FAST bit =“1”: ≤ (15ms+1/fs) Not available Available Not available Available Not available Available ≤ 54kHz 8k / 11.025k / 16k / 22.05k / 24k/ ≥or 32k / 44.1k / 48k / 64k / 88.2k / ≥88.2kHz 96k / 176.4k / 192kHz 4-wire 4-wire/I2C (max.400kHz) AUTO, ERF, FS96 INT0, INT1 128fs/256fs/512fs 64fs/128fs/256fs/512fs 32bit 40bit Depend on CM1-0, XMCK and Depend on CM1-0 bits BCU bits Master Mode Slave Mode 28pin VSOP 30pin VSOP MS0349-E-02 2005/08 -6- ASAHI KASEI [AK4113] 2. Pin Layout AK4112B DVDD 1 30 CM0/CDTO/CAD1 DVSS 2 29 CM1/CDTI/SDA TVDD 3 28 OCKS1/CCLK/SCL V/TX 4 27 OCKS0/CSN/CAD0 XTI 5 26 MCKO1 XTO 6 25 MCKO2 PDN 7 24 DAUX R 8 23 BICK AVDD 9 22 SDTO AVSS 10 21 LRCK RX1 11 20 INT0 (ERF) RX2/DIF0 12 19 FS96/I2C (FS96) RX3/DIF1 13 18 P/SN 14 17 INT1 (AUTO) 15 16 IPS/RX6 (None) RX4/DIF2 (None) RX5 Top View AK4113 Note: 1) Light gray highlights indicate the difference between AK4112B and AK4113. 2) The inside of “( )” indicates the pin name of AK4112B. 3. Control register Control registers of between AK4112B and AK4113 are not compatible. MS0349-E-02 2005/08 -7- ASAHI KASEI [AK4113] ABSOLUTE MAXIMUM RATING (AVSS, DVSS=0V; Note 2) Parameter Symbol min -0.3 Power Supplies: Analog AVDD -0.3 Digital DVDD -0.3 Input Buffer TVDD |AVSS-DVSS| (Note 3) ∆GND Input Current (Any pins except supplies) IIN Input Voltage VIN -0.3 Ambient Temperature (Power applied) Ta -40 Storage Temperature Tstg -65 Note 2. All voltage with respect to ground. Note 3. AVSS and DVSS must be connected to the same ground. max 4.6 4.6 6.0 0.3 ±10 TVDD+0.3 85 150 Units V V V V mA V °C °C WARING: Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes. RECOMMEND OPERATIONG CONDITIONS (AVSS, DVSS=0V; Note 2) Parameter Symbol min typ 3.3 2.7 AVDD Power Supplies: Analog 3.3 2.7 DVDD Digital 3.3 DVDD TVDD Input Buffer 0 -0.3 AVDD - DVDD Difference Note 2. All voltage with respect to ground S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Symbol min typ Input Resistance Zin 10 Input Voltage VTH 350 Input Hysteresis VHY 185 Input Sample Frequency fs 8 - MS0349-E-02 max 3.6 3.6 5.5 0.3 Units V V V V max Units kΩ mVpp mV kHz 216 2005/08 -8- ASAHI KASEI [AK4113] DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current mA 42 26 Normal operation: PDN pin = “H” (Note 4) 100 10 Power down: PDN pin = “L” (Note 5) µA High-Level Input Voltage VIH 70%DVDD TVDD V Low-Level Input Voltage VIL DVSS - 0.3 30%DVDD V High-Level Output Voltage V DVDD-0.4 VOH (Except TX pin: Iout=-400µA) Low-Level Output Voltage V 0.4 VOL (Except TX and SDA pins: Iout=400µA) 0.4 VOL V ( SDA pin: Iout= 3mA) TX Output Level (Note 6) VTXO 0.4 0.5 0.6 V Input Leakage Current (Except RX1-6, XTI pins) Iin ± 10 µA Note 4. AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1 bit = “1”, OCKS0 bit = “1”. TX circuit = Figure 19, Master Mode; AVDD=5mA (typ), DVDD=21mA (typ), TVDD=0.1µA (typ). Note 5. RX inputs are open and all digital input pins are held DVDD or DVSS. Note 6. By using Figure 19 SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 External Clock Frequency fECLK 11.2896 Duty dECLK 40 MCKO1 Output Frequency fMCK1 1.024 Duty dMCK1 40 MCKO2 Output Frequency fMCK2 0.512 Duty dMCK2 40 PLL Clock Recover Frequency (RX1-6) fpll 8 LRCK Frequency fs 8 Duty Cycle dLCK 45 Audio Interface Timing Slave Mode 72 tBCK BICK Period 27 tBCKL BICK Pulse Width Low 27 tBCKH Pulse Width High 15 tLRB LRCK Edge to BICK “↑” (Note 7) 15 tBLR BICK “↑” to LRCK Edge (Note 7) tLRM LRCK to SDTO (MSB) tBSD BICK “↓” to SDTO 15 tDXH DAUX Hold Time 15 tDXS DAUX Setup Time Master Mode fBCK BICK Frequency dBCK BICK Duty -15 tMBLR BICK “↓” to LRCK tBSD BICK “↓” to SDTO 15 tDXH DAUX Hold Time 15 tDXS DAUX Setup Time Note 7. BICK rising edge must not occur at the same time as LRCK edge. MS0349-E-02 typ 50 50 50 - max Units 24.576 24.576 60 27.648 60 27.648 60 216 216 55 MHz MHz % MHz % MHz % kHz kHz % 20 20 64fs 50 15 15 ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns 2005/08 -9- ASAHI KASEI [AK4113] SWITCHING CHARACTERISTICS (Continued) (Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min Control Interface Timing (4-wire serial mode) 200 tCCK CCLK Period 80 tCCKL CCLK Pulse Width Low 80 tCCKH Pulse Width High 50 tCDS CDTI Setup Time 50 tCDH CDTI Hold Time 150 tCSW CSN “H” Time 50 tCSS CSN “↓” to CCLK “↑” 50 tCSH CCLK “↑” to CSN “↑” tDCD CDTO Delay tCCZ CSN “↑” to CDTO Hi-Z Control Interface Timing (I2C Bus mode): fSCL SCL Clock Frequency 1.3 tBUF Bus Free Time Between Transmissions 0.6 tHD:STA Start Condition Hold Time (prior to first clock pulse) 1.3 tLOW Clock Low Time 0.6 tHIGH Clock High Time 0.6 tSU:STA Setup Time for Repeated Start Condition 0 tHD:DAT SDA Hold Time from SCL Falling (Note 8) 0.1 tSU:DAT SDA Setup Time from SCL Rising tR Rise Time of Both SDA and SCL Lines tF Fall Time of Both SDA and SCL Lines 0.6 tSU:STO Setup Time for Stop Condition Cb Capacitive load on bus 0 tSP Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing PDN Pulse Width tPW 150 Note 8. Data must be held for sufficient time to bridge the 300ns transition time of SCL. Note 9. I2C is a registered tradmark of Philips Semiconductors. MS0349-E-02 typ max Units 45 70 ns ns ns ns ns ns ns ns ns ns 400 0.3 0.3 400 50 kHz µs µs µs µs µs µs µs µs µs µs pF ns ns 2005/08 - 10 - ASAHI KASEI [AK4113] Timing Diagram 1/fECLK VIH XTI VIL tECLKH tECLKL dECLK = tECLKH x fECLK x 100 = tECLKL x fECLK x 100 1/fMCK1 50%DVDD MCKO1 tMCKH1 tMCKL1 dMCK1 = tMCKH1 x fMCK1 x 100 = tMCKL1 x fMCK1 x 100 1/fMCK2 50%DVDD MCKO2 tMCKH2 tMCKL2 dMCK2 = tMCKH2 x fMCK2 x 100 = tMCKL2 x fMCK2 x 100 1/fs VIH LRCK VIL tLRH tLRL dLCK = tLRH x fs x 100 = tLRL x fs x 100 Figure 3. Clock Timing VIH LRCK VIL tBCK tBLR tLRB tBCKL tBCKH VIH BICK VIL tLRM tBSD 50%DVDD SDTO tDXS tDXH VIH DAUX VIL Figure 4. Serial Interface Timing (Slave Mode) MS0349-E-02 2005/08 - 11 - ASAHI KASEI [AK4113] 50%DVDD LRCK tMBLR 50%DVDD BICK tBSD 50%DVDD SDTO tDXS tDXH VIH DAUX VIL Figure 5. Serial Interface Timing (Master Mode) VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS CDTI CDTO C1 C0 R/W A4 VIH VIL Hi-Z Figure 6. WRITE/READ Command Input Timing (4-wire serial mode) MS0349-E-02 2005/08 - 12 - ASAHI KASEI [AK4113] tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z CDTO Figure 7. WRITE Data Input Timing (4-wire serial mode) VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD Hi-Z CDTO D7 D6 D5 50%DVDD Figure 8. READ Data Output Timing 1 (4-wire serial mode) tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 D0 50%DVDD Figure 9. READ Data Output Timing 2 (4-wire serial mode) MS0349-E-02 2005/08 - 13 - ASAHI KASEI [AK4113] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Figure 10. I2C Bus Mode Timing tPW PDN VIL Figure 11. Power-down & Reset Timing MS0349-E-02 2005/08 - 14 - ASAHI KASEI [AK4113] OPERATION OVERVIEW Non-PCM (Dolby Digital, MPEG, etc) and DTS-CD Bitstream Detection The AK4113 has a non-PCM bit stream auto-detection function, When the 32bit mode non-PCM preamble based on Dolby “Dolby Digital Data Stream in IEC 60958 Interface” is detected, the NPCM bit sets to “1”. The 96-bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM bit to “1”. Once the NPCM bit is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync pattern being detected. When those preambles are detected, the burst preambles Pc (burst information: Table 17) and Pd (length code: Table 18) that follow those sync codes are stored to registers. The AK4113 has also a DTS-CD bitstream auto-detection function. When the AK4113 detects DTS-CD bitstream, the DTSCD bit sets to “1”. If the next sync code does not occur within 4096frames, the DTSCD bit sets to “0” until a non-PCM bitstream is detected again. The ORed value of NPCM and DTSCD bits are output to AUTO bit. The AK4113 detects the 14-bit sync word and the 16-bit sync word of a DTS-CD bitstream, the detection function can be set ON/OFF by DTS14 and DTS16 bits in serial control mode. In parallel control mode, logical OR value of the AUTO and AUDION bits are outputted to the INTI pin. The DTS-CD detects both the 14-bit sync word and the 16-bit sync word. 216kHz Clock Recovery The integrated low jitter PLL has a wide lock range from 8kHz to 216kHz. The lock time depends on sampling frequency (fs) and FAST bit. (See Figure 12) FAST bit is useful at lower sampling frequency and is fixed to “0” in parallel control mode. In serial control mode, the AK4113 has a sampling frequency detection function (8kHz, 11.025kHz, 16kHz 22.05kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz) that uses either a clock comparison against the X’tal oscillator or the channel status information from the setting of XTL1-0 bits. In parallel control mode, the sampling frequency is detected by using the reference frequency, 24.576MHz. When the sampling frequency is more than 64kHz, FS96 pin goes to “H”. When the sampling frequency is less than 54kHz, FS96 pin goes to “L”. The PLL loses lock when the received sync interval is incorrect. FAST bit PLL Lock Time 0 Default ≤ (15 ms + 384/fs) 1 ≤ (15 ms + 1/fs) Figure 12. PLL Lock Time (fs: Sampling Frequency) MS0349-E-02 2005/08 - 15 - ASAHI KASEI [AK4113] Clock Operation Mode The CM0 and CM1 pins (or bits) select the clock source and the data source of SDTO. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored. For Mode2 and 3, it is recommended that the frequency of X’tal is different from the recovered frequency from PLL. Mode 0 1 CM1 0 0 CM0 0 1 UNLOCK PLL X'tal Clock source SDTO Default ON ON (Note) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 2 1 0 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note: When the X’tal is not used as clock comparison for fs detection (i.e. XTL1-0 bit = “11”), the X’tal is OFF. Table 1. Clock Operation Mode Select Master Clock The AK4113 has two clock outputs, MCKO1 and MCKO2. MCKO2 has two modes. These modes can be selected by the XMCK bit. 1) When XMCK bit = “0” and BCU bit = “0” This mode is compatibile AK4112B and AK4114. These clocks are derived from either the recovered clock or the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 and MCKO2) are set by OCKS0 and OCKS1 as shown in Table 2. The 512fs clock will not operate when the sampling frequency is 96kHz or 192kHz. The 256fs clock will not operate when the sampling frequency is 192kHz. No. 0 1 2 3 OCKS1 0 0 1 1 OCKS0 0 1 0 1 MCKO1 pin MCKO2 pin X’tal 256fs 256fs 256fs 256fs 128fs 256fs 512fs 256fs 512fs 128fs 64fs 128fs Table 2. Master Clock Output Frequency fs (max) 108 kHz 108 kHz 54 kHz 216 kHz Default 2) When XMCK bit “1” and BCU bit = “0” MCKO2 outputs the input clock of the XTI pin when BCU bit = “0” and XMCK bit = “1”. The settings of CM1-0 and OCKS1-0 bits are ignored. The output frequency can be set by the DIV bit. MCKO1 outputs a clock that is selected by the CM1-0 bits and OCKS1-0 bits. XMCK bit 1 1 DIV bit MCKO2 Clock Source MCKO2 Frequency 0 X’tal x1 1 X’tal x 1/2 Table 3. Select output frequency of MCKO2 MS0349-E-02 2005/08 - 16 - ASAHI KASEI [AK4113] Clock Source The following circuits are available to feed the clock to the XTI pin of the AK4113. 1) X’tal XTI AK4113 XTO Figure 13. X’tal mode Note: External capacitance depends upon the crystal oscillator (typ.10-40pF) 2) External clock XTI External Clock AK4113 XTO Figure 14. External clock mode 3) Fixed to the Clock Operation Mode 0 XTI AK4113 XTO Figure 15. OFF Mode MS0349-E-02 2005/08 - 17 - ASAHI KASEI [AK4113] Sampling Frequency and Pre-emphasis Detection The AK4113 has two methods for detecting the sampling frequency. 1. Clock comparison between the recovered clock and X’tal oscillator 2. Sampling frequency information on channel status The method is selected by the XTL1-0 bits. The detected frequency is available on the FS3-0 bits. When XTL1-0 bits = “11”, the sampling frequency is detected by the channel status sampling frequency information. The detected frequency is available on the FS3-0 bits. In parallel control mode, XTL1-0 bits are fixed to “10”. XTL1 bit 0 0 1 1 XTL0 bit X’tal Frequency 0 11.2896MHz 1 12.288MHz 0 24.576MHz 1 (Use channel status) Table 4. Reference X’tal frequency Default Except XTL1-0 bit = “11” Register output fs FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FS2 FS1 Clock comparison (Note 10) FS0 XTL1-0 bit = “11” Consumer mode (Note 11) Byte3 Bit3,2,1,0 0000 0001 0010 0011 0100 Professional mode (Note 12) Byte0 Bit7,6 01 Byte4 Bit6,5,4,3 0000 (Others) 10 0000 11 0000 00 1001 0 44.1kHz 0 0 44.1kHz ± 3% 0 0 1 Reserved 0 48kHz 1 0 48kHz ± 3% 0 32kHz 1 1 32kHz ± 3% 1 22.05kHz 0 0 22.05kHz ± 3% 1 0 1 11.025kHz 11.025kHz ± 3% 1 24kHz 0110 00 1 0 0001 24kHz ± 3% 1 1 1 16kHz 16kHz ± 3% 0 88.2kHz 1000 00 0 0 1010 88.2kHz ± 3% 0 0 1 8kHz 8kHz ± 3% 0 96kHz 1010 00 1 0 0010 96kHz ± 3% 0 1 1 64kHz 64kHz ± 3% 1 176.4kHz 1100 00 0 0 1011 176.4kHz ± 3% 1 192kHz 1110 00 1 0 0011 192kHz ± 3% Note 10. At least ±3% range is identified as the value in the. Table 5. In case of intermediate frequency of those two, FS3-0 bits indicate no value. When the frequency is much bigger than 192kHz or much smaller than 8kHz, FS3-0 bits may indicate “0001” or “1101”. Note 11. In consumer mode, Byte3 Bit3-0 are copied to FS3-0 bits. Note 12. In professional mode, FS3-0 bit indicates “0001” except for frequency shown by Table 5. Table 5. fs Information MS0349-E-02 2005/08 - 18 - ASAHI KASEI [AK4113] The pre-emphasis information is detected and reported on PEM bit. This information is extracted from channel 1 by default. It can be switched to channel 2 by the CS12 bit in control register. Byte 0 Bits 3-5 0 OFF ≠ 0X100 1 ON 0X100 Table 6. PEM in Consumer Mode PEM bit Pre-emphasis Byte 0 Bits 2-4 0 OFF ≠110 1 ON 110 Table 7. PEM in Consumer Mode PEM bit Pre-emphasis De-emphasis Filter Control The AK4113 includes a digital de-emphasis filter (tc=50/15µs). This is an IIR filter that corresponds to four sampling frequencies (32kHz, 44.1kHz and 48kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically by the sampling frequency and pre-emphasis information in the channel status. The AK4113 is in this mode by default. In parallel control mode, the AK4113 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. In serial control mode, DEM1-0 bits control the de-emphasis filter when the DEAU is “0”. The internal de-emphasis filter is bypassed and the recovered data is available without any change if the de-emphasis mode is OFF. When the PEM bit is “0”, the internal de-emphasis filter is always bypassed. PEM bit 1 1 1 1 0 FS3 bit 0 0 0 FS2 bit FS1 bit FS0 bit Mode 0 0 0 44.1kHz 0 1 0 48kHz 0 1 1 32kHz (Others) OFF x x x x OFF Table 8. De-emphasis Auto Control at DEAU bit = “1” (Default) PEM bit 1 1 1 1 0 DEM1 bit DEM0 bit Mode 0 0 44.1kHz 0 1 OFF Default 1 0 48kHz 1 1 32kHz x x OFF Table 9. De-emphasis Manual Control at DEAU bit = “0” MS0349-E-02 2005/08 - 19 - ASAHI KASEI [AK4113] System Reset and Power-Down The AK4113 has a power-down mode for all circuits using the PDN pin or it can be partially powerd-down with the PWN bit. The RSTN bit initializes the register and resets the internal timing. In parallel control mode, only control by the PDN pin is enabled. The AK4113 should be reset once by bringing PDN pin = “L” upon power-up. PDN Pin: All analog and digital circuits are placed in power-down and reset mode by bringing PDN pin = “L”. All the registers are initialized, and clocks are stopped. Reading/Witting to the registers are disabled. RSTN Bit (Address 00H; D0): All the registers except PWN and RSTN bits are initialized by bringing RSTN bit = “0”. The internal timings is also initialized. Writing to registers is not available except the PWN and RSTN bits. Reading from the registers is disabled. PWN Bit (Address 00H; D1): The clock recovery is initialized by bringing PWN bit = “0”. In this case, the clocks are stopped. The registers are not initialized and the mode settings are maintained. Writing and reading to the registers are enabled. MS0349-E-02 2005/08 - 20 - ASAHI KASEI [AK4113] Bi-phase Input Six receiver inputs (RX1-6) are available in serial control mode. IPS2-0 bits select the receiver channel. In parallel control mode, two receiver inputs (RX1 or RX5) are available. The receiver channel is selected by IPS pin. Each input includes an amplifier for unbalanced mode that can accept a signal of 350mV or more. When BCU and UCE bits are changed, the Block start signal, C bit and U bit can output from each pins. (See Table 12 and Figure 16) IPS2 bit IPS1 bit IPS0 bit INPUT Data 0 0 0 RX1 0 0 1 RX2 0 1 0 RX3 0 1 1 RX4 1 0 0 RX5 1 0 1 RX6 1 1 0 No use 1 1 1 No use Table 10. Recovery Data Select at serial control mode Default IPS pin INPUT Data L RX1 H RX5 Table 11. Recovery Data Select at parallel control mode BCU bit 0 1 1 UCE bit MCKO2 pin x (Don’t care) MCKO2 clock output 0 Block start signal output 1 Block start signal output Table 12. B, C, U output pins select INT1 pin INT1 output U-bit output C-bit output (B, C, U, V Output timing at RX mode, Master mode) B C (or U,V) C(R191) C(L0) C(R0) C(L1) C(L39) C(R39) C(L40) 1/4fs LRCK SDTO 2 (I S) SDTO 2 (except I S) L191 R191 L0 R0 R38 L39 R39 R190 L191 R191 L0 L38 R39 L39 * The block signal goes high at the start of frame 0 and remains high until the end of frame 39. Figure 16. B, C, U, V Output Timing MS0349-E-02 2005/08 - 21 - ASAHI KASEI [AK4113] Bi-phase Output In serial control mode, the source of the loop-through output from TX is selected from RX1-6. The bi-phase loop-through output is selected by OPS2-0 bits. The bi-phase loop-through output from TX can be stopped by XTE bit. In parallel control mode, the bi-phase loop-through output can not be outputted. OPS2 bit 0 0 0 0 1 1 1 1 OPS1 bit OPS0 bit INPUT Data 0 0 RX1 0 1 RX2 1 0 RX3 1 1 RX4 0 0 RX5 0 1 RX6 1 0 No use 1 1 No use Table 13. Output Data Select MS0349-E-02 Default 2005/08 - 22 - ASAHI KASEI [AK4113] Bi-phase signal input/output circuit 0.1uF RX 75Ω Coax 75Ω 0.47nF Note AK4113 Figure 17. Consumer Input Circuit (Coaxial Input) Note: For coaxial input, if a coupling level to this input from the next RX input line pattern exceeds 50mV, there may be an incorrect operation. In this case, it is possible to lower the coupling level by adding this decoupling capacitor. Optical Receiver Optical Fiber 470 RX O/E AK4113 Figure 18. Consumer Input Circuit (Optical Input) For coaxial input in serial mode, the input level of RX line is small, so care must be taken to avoid crosstalk among the RX input lines. In this case, a shield is recommended between the input lines. In parallel control mode, two channel inputs (RX1 and RX5) are available, RX2, RX3, RX4 and RX6 change to other pins for mode settings. Those pins must be fixed to “H” or “L” because they are not normal logic input. The AK4113 includes the TX output buffer. The output level meets combination 0.5V± 20% using the external resistor network. The T1 in Figure 19 is a transformer of 1:1. R1 TX 75Ω cable R2 DVSS T1 Vdd R1 R2 3.3V 240Ω 150Ω 3.0V 220Ω 150Ω Figure 19. TX External Resistor Network MS0349-E-02 2005/08 - 23 - ASAHI KASEI [AK4113] U-bit buffers The AK4113 has a Q-subcode buffer for CD application. The AK4113 takes the Q-subcode into registers by the following method. 1. The sync word (S0,S1) is constructed of at least 16 “0”s. 2. The start bit is “1”. 3. Those 7bits Q-W follows to the start bit. 4. The distance between two start bits are 8-16 bits. The QINT bit in the control register goes to “1” when the new Q-subcode differs from old one, and goes to “0” when the QINT bit is read. S0 S1 S2 S3 : S97 S0 S1 S2 S3 : 1 0 0 1 1 : 1 0 0 1 1 : 2 3 0 0 0 0 Q2 R2 Q3 R3 : : Q97 R97 0 0 0 0 Q2 R2 Q3 R3 : : 4 0 0 S2 S3 : S97 0 0 S2 S3 : 5 0 0 T2 T3 : T97 0 0 T2 T3 : 6 0 0 U2 U3 : U97 0 0 U2 U3 : 7 8 0 0 0 0 V2 W2 V3 W3 : : V97 W97 0 0 0 0 V2 W2 V3 W3 : : * 0… 0… 0… 0… : 0… 0… 0… 0… 0… : (*) number of "0" : min=0; max=8. Figure 20. Configuration of U-bit (CD) Q2 Q3 Q4 CTRL Q5 Q6 Q7 Q8 ADRS Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 TRACK NUMBER INDEX Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49 MINUTE SECOND FRAME Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73 ZERO ABSOLUTE MINUTE ABSOLUTE SECOND Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97 ABSOLUTE FRAME CRC G(x)=x16+x12+x5+1 Figure 21. Q-subcode Addr 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH Register Name Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame D7 D6 D5 D4 Q9 Q8 ··· ··· Q17 Q16 ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· Q81 Q80 ··· ··· Figure 22. Q-subcode register MS0349-E-02 D3 ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· D2 ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· D1 Q3 Q11 ··· ··· ··· ··· ··· ··· ··· Q75 D0 Q2 Q10 ··· ··· ··· ··· ··· ··· ··· Q74 2005/08 - 24 - ASAHI KASEI [AK4113] Error Handing The following nine events cause the INT0 and INT1 pins to show the status of the interrupt condition. When the PLL is OFF (Clock Operation Mode 1), INT0 and INT1 pins go to “L”. 1. UNLCK : PLL unlock state detect “1” when the PLL loses lock. The AK4113 loses lock when the distance between two preamble is not correct or when those preambles are not correct. 2. PAR : Parity error or bi-phase coding error detection “1” when parity error or bi-phase coding error is detected, updated every sub-frame cycle. 3. AUTO : Non-Linear PCM or DTS-CD Bit Stream detection The OR function of NPCM and DTSCD bits is available at the AUTO bit. 4. V : Validity flag detection “1” when validity flag is detected. Updated every sub-frame cycle. 5. AUDION : Non-audio detection “1” when the “AUDION” bit in recovered channel status indicates “1”. Updated every block cycle. 6. STC : Sampling frequency or pre-emphasis information change detection When either FS3-0 bit or PEM bit is changed, it maintains “1” during 1 sub-frame. 7. QINT : U-bit Sync flag “1” when the Q-subcode differs from the old one. Updated every sync code cycle for Q-subcode. 8. CINT : Channel status sync flag “1” when received C bit differs from the old one. Updated every block cycle. 9. DAT : DAT Start ID detect “1” when the category code indicates “DAT” and “DAT Start ID” is detected. When DCNT bit is “1”, it does not indicate “1” even if “DAT Start ID” is detected again within “3841 x LRCK”. When “DAT Start ID” is detected again after “3840 x LRCK” passed, it indicates “1”. When DCNT bit is “0”, it indicates “1” every “DAT Start ID” detection. MS0349-E-02 2005/08 - 25 - ASAHI KASEI [AK4113] 1. Parallel control mode In parallel control mode, the INT0 pin outputs the ORed signal between UNLCK and PAR. The INT1 pin outputs the ORed signal between AUTO and AUDION. Once INT0 goes ”H”, it maintains “H” for 1024/fs cycles after the all error events are removed. Table 14 shows the state of each output pins when the INT0/1 pin is “H”. UNLCK 1 0 0 x x x PAR x 1 0 x x x Event AUTO x x x 1 x 0 AUDION x x x x 1 0 INT0 “H” INT1 Note 13 “L” Note 14 “H” Pin SDTO “L” Previous Data Output V “L” Output Output Note 15 Note 16 “L” Note 13. INT1 pin outputs “L” or “H” in accordance with the ORed signal between AUTO and AUDION. Note 14. INT0 pin outputs “L” or “H” in accordance with the ORed signal between UNLCK and PAR. Note 15. SDTO pin outputs “L”, “Previous Data” or “Normal Data” in accordance with the ORed signal between UNLCK and PAR. Note 16. V pin outputs “L” or “Normal operation” in accordance with the ORed signal between PAR and UNCLK. Table 14. Error Handling in parallel control mode (x: Don’t care) 2. Serial control mode In serial control mode, the INT1 and INT0 pins output an ORed signal based on the above nine interrupt events. When masked, the interrupt event does not affect the operation of the INT1-0 pins (the masks do not affect the registers in 07H and DAT bit). Once the INT0 pin goes to “H”, it remains “H” for 1024/fs (this value can be changed with the EFH1-0 bits) after all events not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared. UNLCK, PAR, AUTO, AUDION and V bits in Address=07H indicate the interrupt status events above in real time. Once QINT, CINT and DAT bits goes to “1”, it stays “1” until the register is read. When the AK4113 loses lock, the channel status bit, user bit, Pc and Pd are initialized. In this initial state, INT0 pin outputs the ORed signal between UNLCK and PAR bits. INT1 pin outputs the ORed signal between AUTO and AUDION bits. UNLCK 1 0 x Event Pin PAR Others SDTO V TX x x “L” “L” Output 1 x Previous Data Output Output x x Output Output Output Table 15. Error Handling in serial control mode (x: Don’t care) MS0349-E-02 2005/08 - 26 - ASAHI KASEI Error (Unlock, Parity...) [AK4113] (Error) INT0 pin Hold Time (max: 4096/fs) INT1 pin Hold Time = 0 Register (PAR,STC,CINT,QINT) Reset Hold “1” Register (others) Command MCKO,BICK,LRCK (Unlock) READ 07,08H Free Run (fs: around 5kHz) MCKO,BICK,LRCK (except Unlock) SDTO (Unlock) SDTO (Parity error) Previous Data SDTO (others) Vpin (Unlock) Vpin (except Unlock) Normal Operation Figure 23. INT0/1 pin Timing MS0349-E-02 2005/08 - 27 - ASAHI KASEI [AK4113] PDN pin = “L” to “H” Initialize Read (07H,08H) INT0/1 pin= “H” No Yes Release Muting Mute DAC output Read (07H,08H) (Each Error Handling) Read (07H,08H) (Resets registers) No INT0/1 pin= “H” Yes Figure 24. Error Handling Sequence Example 1 MS0349-E-02 2005/08 - 28 - ASAHI KASEI [AK4113] PDN pin = “L” to “H” Initialize Read (07H,08H) No INT1 pin =“H” Yes Read (07H,08H) and Detect QSUB= “1” (Read Q-buffer) QCRC = “0” No New data is invalid Yes INT1 pin = “L” No Yes New data is valid Figure 25. Error Handling Sequence Example (for Q/CINT) MS0349-E-02 2005/08 - 29 - ASAHI KASEI [AK4113] Audio Serial Interface Format The DIF0, DIF1 and DIF2 pins can select eight serial data formats as shown in Table 16. In all formats the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and DAUX is latched on the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to 128fs at fs=48kHz. If the data word length is equal or less than 20-bits (Mode0-2), the LSBs in the sub-frame are truncated. In Mode 3-7, the last 4-LSBs are auxiliary data (see Figure 26). When the Parity Error, Bi-phase Error or Frame Length Error occurs in a sub-frame, the AK4113 continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4113 outputs “0” from SDTO. If DAUX is used, the data is transformed and outputted from SDTO. DAUX is used in Clock Operation Mode 1, 3 and unlock state of Mode 2. The input data format to DAUX should be left justified except in Mode 5 and 7. In Mode 5 or 7, both the input data format of DAUX and output data format of SDTO are I2S. Mode 6 and 7 are Slave Modes that corresponds to the Master Mode of Mode 4 and 5. In Slave mode, LRCK and BICK should be synchronized with MCKO1/2. sub-frame of IEC60958 0 3 4 preamble 7 8 11 12 27 28 29 30 31 Aux. V U C P LSB MSB MSB LSB 23 0 AK4113 Audio Data (MSB First) Figure 26. Bit configuration Mode DIF2 DIF1 DIF0 DAUX SDTO 0 1 2 3 4 5 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 24-bit, Left justified 24-bit, Left justified 24-bit, Left justified 24-bit, Left justified 24-bit, Left justified 24-bit, I2S 16-bit, Right justified 18-bit, Right justified 20-bit, Right justified 24-bit, Right justified 24-bit, Left justified 24-bit, I2S LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O 6 1 1 0 24-bit, Left justified 24-bit, Left justified H/L I 7 1 1 1 24-bit, I2S 24-bit, I2S L/H I BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs (Note 17) 64-128fs (Note 17) I/O O O O O O O I Default I Table 16. Audio Data Format Note 17. This frequency must not exceed a maximum BICK frequency that is defined in “Switching Characteristics”. MS0349-E-02 2005/08 - 30 - ASAHI KASEI [AK4113] LRCK(O) 0 1 2 15 16 17 31 0 1 2 15 16 17 31 0 1 0 1 0 1 BICK (O:64fs) 15 14 1 0 15 14 1 0 SDTO(O) 15:MSB, 0:LSB Rch Data Lch Data Figure 27. Mode 0 Timing LRCK(O) 0 1 2 9 10 12 11 31 0 1 2 9 10 11 12 31 BICK (O:64fs) 23 22 21 20 1 0 23 22 21 20 1 0 SDTO(O) 23:MSB, 0:LSB Rch Data Lch Data Figure 28. Mode 3 Timing LRCK 0 1 2 21 22 24 23 31 0 1 2 21 22 23 24 31 BICK (64fs) 23 22 21 2 1 0 23 22 3 2 1 0 23 22 SDTO(O) 23:MSB, 0:LSB Rch Data Lch Data Figure 29. Mode 4, 6 Timing Mode4 : LRCK, BICK : Output Mode6 : LRCK, BICK : Input LRCK 0 1 2 22 24 23 25 31 0 1 2 21 22 23 24 25 31 0 1 BICK (64fs) SDTO(O) 23 22 21 2 1 23 22 0 3 2 1 0 23 23:MSB, 0:LSB Rch Data Lch Data Figure 30. Mode 5, 7 Timing MS0349-E-02 Mode5 : Mode7 : LRCK, BICK : Output LRCK, BICK : Input 2005/08 - 31 - ASAHI KASEI [AK4113] Serial Control Interface 1. 4-wire serial control mode (I2C pin = “L”) The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, C1-0 are fixed to “00”), Read/Write (1-bit), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI WRITE C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z CDTO CDTI READ C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z CDTO C1,C0: R/W: A4-A0: D7-D0: D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Chip Address (Fixed to “00”) READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 31. 4-wire Serial Control I/F Timing * The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN pin is “L”. MS0349-E-02 2005/08 - 32 - ASAHI KASEI [AK4113] 2. I2C bus control mode (I2C pin = “H”) The AK4113 supports a fast-mode I2C-bus system (max : 400kHz). 2-1. Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4113 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master device. 2-1-1. Data validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition. SCL SDA DATA LINE STABLE : DATA VALID CHANGE OF DATA ALLOWED Figure 32. Data transfer 2-1-2. START and STOP condition A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from the START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the STOP condition. SCL SDA START CONDITION STOP CONDITION Figure 33. START and STOP conditions MS0349-E-02 2005/08 - 33 - ASAHI KASEI [AK4113] 2-1-3. ACKNOWLEDGE ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4113 will generates an acknowledge after each byte has been received. In the read mode, the slave, the AK4113 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition. Clock pulse for acknowledge SCL FROM MASTER 1 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER START CONDITION acknowledge Figure 34. Acknowledge on the I2C-bus 2-1-4. FIRST BYTE The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the SDA line. The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0 pin) set them. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read condition is requested by the master. A “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. 0 0 1 0 0 CAD1 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins.) Figure 35. The First Byte MS0349-E-02 2005/08 - 34 - ASAHI KASEI [AK4113] 2-2. WRITE Operations Set R/W bit = “0” for the WRITE operation of AK4113. After receipt the start condition and the first byte, the AK4113 generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of AK4113. The format is MSB first, and those most significant 3-bits are “Don’t care”. * * * A4 A3 A2 A1 A0 (*: Don’t care) Figure 36. The Second Byte After receipt the second byte, the AK4113 generates an acknowledge, and awaits the third byte. Those data after the second byte contain control data. The format is MSB first, 8bits. D7 D6 D5 D4 D3 D2 D1 D0 Figure 37. Byte structure after the second byte The AK4113 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4113 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1CH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. S T A R T SDA Register Address(n) Slave Address S T Data(n+x) O P Data(n+1) Data(n) S P A C K A C K A C K A C K Figure 38. WRITE Operation MS0349-E-02 2005/08 - 35 - ASAHI KASEI [AK4113] 2-3. READ Operations Set R/W bit = “1” for the READ operation of AK4113. After transmission of a data, the master can read next address’s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1CH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4113 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 2-3-1. CURRENT ADDRESS READ The AK4113 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4113 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4113 discontinues transmission S T A R T SDA Slave Address Data(n) Data(n+1) S Data(n+x) T O P Data(n+2) S P A C K A C K A C K A C K Figure 39. CURRENT ADDRESS READ 2-3-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues the start condition, slave address(R/W bit =“0”) and then the register address to read. After the register address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4113 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4113 discontinues transmission. S T A R T SDA Slave Address S T A R T Word Address(n) S Slave Address Data(n) S Data(n+x) T O P Data(n+1) S A C K P A C K A C K A C K A C K Figure 40. RANDOM READ MS0349-E-02 2005/08 - 36 - ASAHI KASEI [AK4113] Register Map Addr 01H Register Name CLK & Power Down Control Format & De-em Control 02H Input/ Output Control 0 00H D7 D6 D5 D4 D3 D2 D1 D0 CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 0 0 XTL1 XTL0 UCE TXE OPS2 OPS1 OPS0 EFH1 EFH0 IPS2 IPS1 IPS0 03H Input/ Output Control 1 FAST XMCK DIV 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MV0 MSTC0 MAUD0 MPAR0 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MV1 MSTC1 MAUD1 MPAR1 06H DAT Mask & DTS Detect DTS14 MDAT1 MDAT0 07H 0 0 0 DCNT DTS16 Receiver status 0 QINT AUTO CINT UNLCK V STC AUDION PAR 08H Receiver status 1 FS3 FS2 FS1 FS0 PEM DAT DTSCD NPCM 09H Receiver status 2 0 0 0 0 0 0 QCRC CCRC 0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 0BH RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0CH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0DH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0EH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 13H Q-subcode Address/Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 14H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 15H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 16H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 17H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 19H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 Note: When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is “0”. For addresses from 1DH to 1FH, data must not write. MS0349-E-02 2005/08 - 37 - ASAHI KASEI [AK4113] Register Definitions Reset & Initialize Addr Register Name 00H CLK & Power Down Control R/W Default D7 CS12 R/W 0 D6 BCU R/W 0 D5 CM1 R/W 0 D4 CM0 R/W 0 D3 D2 OCKS1 OCKS0 R/W R/W 0 0 D1 PWN R/W 1 D0 RSTN R/W 1 RSTN: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation (Default) PWN: Power Down 0: Power Down 1: Normal Operation (Default) OCKS1-0: Master Clock Frequency Select (See Table 2) CM1-0: Master Clock Operation Mode Select (See Table 1) BCU: Block start (B) , C, U Output Mode (See Table 12) 0: Disable (Default) 1: Enable CS12: Channel Status Select 0: Channel 1 (Default) 1: Channel 2 Select which channel status is used to derive C-bit buffer, AUDION, PEM, FS3-0, Pc and Pd. The de-emphasis filter is controlled by channel 1 in the parallel control mode. Format & De-emphasis Control Addr Register Name 01H Format & De-em Control R/W Default D7 V/TX R/W 0 D6 DIF2 R/W 1 D5 DIF1 R/W 1 D4 DIF0 R/W 0 D3 DEAU R/W 1 D2 DEM1 R/W 0 D1 DEM0 R/W 1 D0 0 RD 0 DEM1-0: 32, 44.1, 48kHz De-emphasis Control (See Table 9) DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable (Default) DIF2-0: Audio Data Format Control (See Table 16; Default: “110”) V/TX: V/TX Output Select 0: Validity Flag Output. (Default) This output is updated every fs cycle. 1: TX MS0349-E-02 2005/08 - 38 - ASAHI KASEI [AK4113] Input/Output Control Addr Register Name 02H Input/ Output Control 0 R/W Default D7 0 RD 0 D6 XTL1 R/W 0 D5 XTL0 R/W 0 D4 UCE R/W 0 D3 TXE R/W 1 D2 OPS2 R/W 0 D1 OPS1 R/W 0 D0 OPS0 R/W 0 D2 IPS2 R/W 0 D1 IPS1 R/W 0 D0 IPS0 R/W 0 OPS2-0: Output Through Data Select for TX pin (See Table 13; Default: “000”) TXE: TX pin Output Enable 0: Disable. TX pin outputs “L”. 1: Enable (Default) UCE: C-bit, U-bit output setting (See Table 12, Default: “0”) XTL1-0: Reference X’tal frequency Select (See Table 4, Default: 00) Addr Register Name 03H Input/ Output Control 1 R/W Default D7 EFH1 R/W 0 D6 EFH0 R/W 1 D5 FAST R/W 0 D4 D3 XMCK DIV R/W 0 R/W 0 IPS2-0: Input Recovery Data Select (See Table 10; Default: “000”) DIV: MCKO2 Output Frequency Select at X’tal Mode (See Table 3) 0: x 1 (Default) 1: x 1/2 XMCK: MCKO2 pit output select (See Table 3) 0: Depends on CM1-0 bits and OCKS1-0 bits (Default) 1: Fixed to X’tal Mode FAST: PLL Lock Time Select 0: ≤ (15ms + 384/fs) (Default) 1: ≤ (15ms + 1/fs) EFH1-0: INT0 pin Hold Time Select 00: 512/fs 01: 1024/fs (Default) 10: 2048/fs 11: 4096/fs MS0349-E-02 2005/08 - 39 - ASAHI KASEI [AK4113] Mask Control for INT0 Addr Register Name 04H INT0 MASK R/W Default D7 D6 D5 D4 MQIT0 MAUT0 MCIT0 MULK0 R/W R/W R/W R/W 1 1 1 0 D3 MV0 R/W 1 D2 D1 D0 MSTC0 MAUD0 MPAR0 R/W R/W R/W 1 1 0 MPAR0: Mask enable for PAR bit 0: Mask disable (Default) 1: Mask enable MAUD0:Mask enable for AUDION bit 0: Mask disable 1: Mask enable (Default) MSTC0: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MV0: Mask enable for V bit 0: Mask disable 1: Mask enable (Default) MULK0:Mask enable for UNLCK bit 0: Mask disable (Default) 1: Mask enable MCIT0: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT0: Mask enable for AUTO bit 0: Mask disable 1: Mask enable (Default) MQIT0: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT0 pin operation. MS0349-E-02 2005/08 - 40 - ASAHI KASEI [AK4113] Mask Control for INT1 Addr Register Name 05H INT1 MASK R/W Default D7 D6 D5 D4 MQIT1 MAUT1 MCIT1 MULK1 R/W R/W R/W R/W 1 0 1 1 D3 MV1 R/W 1 D2 D1 D0 MSTC1 MAUD MPAR1 R/W R/W R/W 1 0 1 MPAR1: Mask enable for PAR bit 0: Mask disable 1: Mask enable (Default) MAUD1: Mask enable for AUDION bit 0: Mask disable (Default) 1: Mask enable MSTC1: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MV1: Mask enable for V bit 0: Mask disable 1: Mask enable (Default) MULK1: Mask enable for UNLCK bit 0: Mask disable 1: Mask enable (Default) MCIT1: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT1: Mask enable for AUTO bit 0: Mask disable (Default) 1: Mask enable MQIT1: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT1 pin operation. DAT Mask & DTS Detect Addr Register Name 06H DAT Mask & DTS Detect R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 DCNT R/W 1 D3 DTS16 R/W 1 D2 D1 D0 DTS14 MDAT1 MDAT0 R/W R/W R/W 1 1 1 MDAT0: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, DAT event does not affect INT0 pin operation. MDAT1: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, DAT event does not affect INT1 pin operation. DTS14: DTS-CD 14bit Sync Word Detect 0: Disable 1: Enable (Default) DTS16: DTS-CD 16bit Sync Word Detect 0: Disable 1: Enable (Default) DCNT: DAT Start ID Counter 0: Disable 1: Enable (Default) MS0349-E-02 2005/08 - 41 - ASAHI KASEI [AK4113] Receiver Status 0 Addr Register Name 07H Receiver status 0 R/W Default D7 QINT RD 0 D6 AUTO RD 0 D5 CINT RD 0 D4 UNLCK RD 0 D3 V RD 0 D2 STC RD 0 D1 AUDION RD 0 D0 PAR RD 0 PAR: Parity Error or Bi-phase Error Status 0: No Error 1: Error This bit goes to “1”, if a Parity Error or Biphase Error is detected in the sub-frame. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. STC: Sampling Frequency or Pre-emphasis Information Change Detection 0: No detect 1: Detect This bit goes to “1” when either the FS3-0 or PEM bit changes. V: Validity of channel status 0: Valid 1: Invalid UNLCK: PLL Lock Status 0: Lock 1: Unlock CINT: Channel Status Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when C-bit stored in register addresses 0AH to 0EH changes. AUTO: Non-PCM Auto Detect 0: No detect 1: Detect QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when Q-subcode stored in register addresses 13H to 1CH changes. STC, QINT, CINT and PAR bits are initialized when 07H is read. MS0349-E-02 2005/08 - 42 - ASAHI KASEI [AK4113] Receiver Status 1 Addr Register Name 08H Receiver status 1 R/W Default D7 FS3 RD 0 D6 FS2 RD 0 D5 FS1 RD 0 D4 FS0 RD 1 D3 PEM RD 0 D2 DAT RD 0 D1 DTSCD RD 0 D0 NPCM RD 0 D3 0 RD 0 D2 0 RD 0 D1 QCRC RD 0 D0 CCRC RD 0 NPCM: Non-PCM Bit Stream Auto Detection 0: No detect 1: Detect DTSCD: DTS-CD Bit Stream Auto Detection 0: No detect 1: Detect DAT: DAT Start ID Detect 0: No detect 1: Detect DAT bit is initialized when 08H is read. PEM: Pre-emphasis Detect 0: OFF 1: ON This bit is made by encoding channel status bits. FS3-0: Sampling Frequency detection (See Table 5) Receiver Status 1 Addr Register Name 09H Receiver status 1 R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 CCRC: Cyclic Redundancy Check for Channel Status 0: No error 1: Error This bit is enabled only in professional mode and only for the channel selected by the CS12 bit. QCRC: Cyclic Redundancy Check for Q-subcode 0: No error 1: Error MS0349-E-02 2005/08 - 43 - ASAHI KASEI [AK4113] Receiver Channel Status Addr 0AH 0BH 0CH 0DH 0EH Register Name RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 R/W Default D7 CR7 CR15 CR23 CR31 CR39 D6 CR6 CR14 CR22 CR30 CR38 D5 CR5 CR13 CR21 CR29 CR37 D4 CR4 CR12 CR20 CR28 CR36 D3 CR3 CR11 CR19 CR27 CR35 D2 CR2 CR10 CR18 CR26 CR34 D1 CR1 CR9 CR17 CR25 CR33 D0 CR0 CR8 CR16 CR24 CR32 D2 PC2 PC10 PD2 PD10 D1 PC1 PC9 PD1 PD9 D0 PC0 PC8 PD0 PD8 D2 Q4 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76 D1 Q3 Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75 D0 Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74 RD Not initialized CR39-0: Receiver Channel Status Byte 4-0 All 40 bits are updated at the same time every bock (192 frames) cycle. Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams Addr 0FH 10H 11H 12H Register Name Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 R/W Default D7 PC7 PC15 PD7 PD15 D6 PC6 PC14 PD6 PD14 D5 PC5 PC13 PD5 PD13 D4 PC4 PC12 PD4 PD12 D3 PC3 PC11 PD3 PD11 RD Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1 Q-subcode Buffer Addr 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH Register Name Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame R/W Default D7 Q9 Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 Q81 D6 Q8 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80 D5 Q7 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79 D4 Q6 Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78 D3 Q5 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77 RD Not initialized Q2-81: Q-subcode (Figure 20 and Figure 21 ) All 80 bits are updated at the same time every sync code cycle for Q-subcode. MS0349-E-02 2005/08 - 44 - ASAHI KASEI [AK4113] Burst Preambles in non-PCM Bitstreams sub-frame of IEC60958 0 3 4 preamble 7 8 Aux. 11 12 27 28 29 30 31 LSB MSB V U C P 16 bits of bitstream 0 Pa Pb Pc Pd 15 Burst_payload stuffing repetition time of the burst Figure 41. Data structure in IEC60958 Preamble word Pa Pb Pc Pd Bits of Pc Value 0-4 5, 6 7 8-12 13-15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 0 0 1 0 Length of field Contents 16 bits sync word 1 16 bits sync word 2 16 bits Burst info 16 bits Length code Table 17. Burst preamble words Contents Value 0xF872 0x4E1F see Table 18 numbers of bits Repetition time of burst in IEC60958 frames data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved reserved, shall be set to “0” error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors data type dependent info bit stream number, shall be set to “0” Table 18. Fields of burst info Pc MS0349-E-02 ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 2005/08 - 45 - ASAHI KASEI [AK4113] Non-PCM Bitstream timing 1) When Non-PCM preamble is not coming within 4096 frames. PDN pin Bit stream Pa Pb Pc1 Pd1 Pa Pb Pc2 Pd2 Repetition time Pa Pb Pc3 Pd3 >4096 frames AUTO bit Pc Register “0” Pd Register “0” Pc1 Pc2 Pd1 Pc3 Pd2 Pd3 Figure 42. Timing Example 1 2) When Non-PCM bitstream stops (When MULK0 bit = “0”) INT0 pin INT0 hold time PLL Lock Time Bit stream Pa Pb Pc1 Pd1 Stop Pa Pb Pcn Pdn 2~3 Syncs (B,M or W) AUTO bit Pc Register Pd Register <Repetition time Pc0 Pc1 Pd0 Pcn Pd1 Pdn Figure 43. Timing Example 2 MS0349-E-02 2005/08 - 46 - ASAHI KASEI [AK4113] SYSTEM DESIGN Figure 44 shows the example of system connection diagram for serial control mode. 3.3V Supply 10u 0.1u + DVDD 2 DVSS CDTI 29 3 TVDD CCLK 28 CDTO 3.3~5V Supply + 0.1u 10u 4 V/TX CSN 27 5 XTI MCKO1 26 6 XTO MCKO2 25 7 PDN DAUX 24 C C 15k±5% 3.3V Supply 10u + 0.1u (see Figure 15,16) 30 1 AK4113 8 R BICK 23 9 AVDD SDTO 22 10 AVSS LRCK 21 11 RX1 INT0 20 12 RX2 I2C 19 13 RX3 P/SN 18 14 RX4 INT1 17 15 RX5 RX6 16 Microcontroller DSP and AD/DA Figure 44. Typical Connection Diagram (4-wire serial control mode) Notes: - For setting of XTL1-0 bits, refer to Table 4. - “C” depends on the crystal oscillator - AVSS and DVSS must be connected the same ground plane. - Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance. MS0349-E-02 2005/08 - 47 - ASAHI KASEI [AK4113] PACKAGE 30pin VSOP (Unit: mm) 1.5MAX *9.7±0.1 0.3 30 16 15 1 0.22±0.1 7.6±0.2 5.6±0.1 A 0.15 +0.10 -0.05 0.65 0.12 M 0.45±0.2 +0.10 0.08 0.10 -0.05 1.2±0.10 Detail A NOTE: Dimension "*" does not include mold flash. Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb Free) plate MS0349-E-02 2005/08 - 48 - ASAHI KASEI [AK4113] MARKING AKM AK4113VF XXXBYYYYC XXXBYYYYC: XXXB: YYYYC: Date code identifier Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number C : Alpha character) Revision History Date (YY/MM/DD) 04/10/20 05/03/08 05/08/10 Revision 00 01 02 Reason First Edition Error Correct Error Correct Page Contents 3, 4, 7 4 Pin Name: #14; RX4/IPS2 Æ RX4/DIF2 I/O of INT0 pin: “I” Æ “O” IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0349-E-02 2005/08 - 49 -