[AK7752] AK7752 Audio/Hands Free DSP with Stereo CODEC GENERAL DESCRIPTION The AK7752 is a digital signal processor with an integrated stereo CODEC. The digital signal processor (DSP) can execute a high-quality hands-free algorithm, using only internal memory. Fine tuning is available for improving voice quality of the hands-free function in actual user environments. The AK7752 includes delay RAM, an integrated PLL, four digital audio input and eight digital audio output ports. The AK7752 can perform pre and post processing for speech recognition, volume control adjustment and parametric equalization, executed by programs downloaded via the microprocessor interface. FEATURES [ADC Block] Sampling rate: 8kHz ~ 48kHz 24-bit stereo S/(N+D): 86dB DR, S/N: 89dB (fs=8 kHz), 91dB (fs=48kHz) Integrated DC offset canceling High Pass Filter [DAC Block] Sampling rate: 8kHz ~ 48kHz 18-bit stereo S/(N+D): 90dB (fs =8kHz), 88dB (fs=48kHz) DR, S/N: 95dB (fs =8kHz), 95dB (fs=48kHz) [Input/Output Digital Interface] 4-channel Serial Data Input 8-channel Serial Output [General] Integrated PLL EEPROM (AK6514C) Interface Microprocessor Interface: I²C BUS or AKM original mode Power Supply: Single 3.3V ±0.3V Operating Temperature Range: -40°C~85°C 64pin LQFP MS0578-E-01-PB 2007/09 - 1 - [AK7752] BLOCK DIAGRAM ALINE_IN ANE_IN VREFL VCOM VREFH ANE_OUT pull down ALINE_OUT 2 AVDD Hi-z Open drain REF ADC DAC ctrl reg sw 2 BVSS 5 DVDD Lch:ANE_OUT Rch:ALINE_OUT 5 DVSS SELA2A Lch:ALINE_IN / Rch:ANE_IN SWG0 SDOUTA GPO0 SDOUT3 SDINA SDIN1 DEXT3_OUT SDIN2 DEXT_IN / JX3 AVSS SDATA_DA SDATA_AD DLINE_IN 2 SWG1 OUTEX2_N DEXT2_OUT SDOUT2 HF(DSP) GPO1 JX2_E JX2 JX1_E JX1 JX0_E JX0 JX2 JX1 DEXT1_OUT OUTLE_N DLINE_OUT SDOUT1 JX3 JX3_E OUTEX1_N WDT CRC STO CRC_E MICIF I2CSEL RQ_N/CAD1 SI/CAD0 JX0 SCL/SCLK SDA SO SO RDY EESEL EESEL RSTO_N TESTI1 TESTI2 CONT INIT_RESET_N SEL_EEST EEST EEST/RSTO_N EESI EECK EEPIF EECS_N EESO S_RESET_N CK_RESET_N CKM[3:0] 4 CKM[3:0] (Master="L", Slave="H") XTI CLK XTO SMODE CLKO1 CLKO1E BE LE TESTO1 SYNC_O BITCLK_O SYNC_I LFLT BITCLK_I Figure 1. Block Diagram * Figure 1 shows a simplified diagram of the AK7752, which isn’t the perfect same as the actual circuit diagram. MS0578-E-01-PB 2007/09 - 2 - [AK7752] Ordering Guide -40 ∼ +85°C 64pin LQFP Evaluation Board for AK7752 AK7752VQ AKD7752 EESEL BVSS DVDD DVSS XTI XTO DVSS DVDD SYNC_O BITCLK_O DLINE_OUT DEXT1_OUT DEXT2_OUT EEST/RSTO_N DEXT3_OUT 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 47 Pin Layout I2CSEL TESTI2 49 32 CLKO1 CKM[1] 50 31 CKM[2] CKM[0] 51 30 CKM[3] TESTI1 52 29 S_RESET_N LFLT 53 28 CK_RESET_N AVSS 54 27 INIT_RESET_N AVDD 55 26 SYNC_I ANE_IN 56 25 BITCLK_I 24 DVSS 64pin LQFP (TOP VIEW) VREFL 61 20 JX2 AVSS 62 19 DEXT_IN/JX3 ALINE_OUT 63 18 DLINE_IN ANE_OUT 64 17 STO 16 JX1 15 21 14 60 13 VCOM 12 JX0 11 22 10 59 9 VREFH 8 DVDD 7 23 6 58 5 AVDD 4 57 1 ALINE_IN 3 ■ 2 ■ TESTO1 SDA SCLK/SCL DVDD DVSS SI/CAD0 SO RDY RQ_N/CAD1 DVDD DVSS BVSS EESI EECK EECS_N EESO Input Output I/O Power Note) XXXX is internal pull-down pin. XXXX is the pin name. MS0578-E-01-PB 2007/09 - 3 - [AK7752] PIN/FUNCTION No. Pin Name I/O Function Classification EEPIF 1 EECS_N O EEPROM Chip Select Pin Connect to the C_N pin of the AK6514C (EEPROM).The output is Hi-Z when EESEL pin= “L”. 2 EESO I EEPROM Serial Data Receive Pin ( Internal pull-down ) Connect to the SO pin of the AK6514C (EEPROM). Connect to DVSS or leave open when a EEPROM is not use. 3 EECK 4 EESI 5 BVSS 6 7 DVSS DVDD 8 RQ_N CAD0 EEPROM Serial Data Output Clock Pin Connect to the SCK pin of the AK6514C (EEPROM). The output is Hi-Z when EESEL pin = “L”. EEPROM Serial Data Output Pin O Connect to the SI pin of the AK6514C. The output is Hi-Z when EESEL pin= “L”. Analog Power Silicon Substrate Potential 0V Connect to AVSS. Supply - Ground Pin for Digital Section 0.0V Digital - Power Supply Pin for Digital Section (3.3V typical) Power Supply Microprocessor Interface Write Request Pin (I2CSEL pin = “L”) Microprocessor I When initial reset state and Microcomputer interface are not in use, leave RQ_N Interface. pin= “H”. 2 I I C Bus Address Setting Pin 1 (I2CSEL pin = “H”) I2C Microprocessor O Data Write Ready Output Pin for Microprocessor Interface Interface Serial Data Output Pin for Microprocessor Interface O When RQ_N pin = “H”, SO pin= Hi-Z Serial Data Input Pin for Microprocessor Interface (I2CSEL pin = “L”) I When SI is not used, tie the SI pin = “L”. I2C I I2CSEL= “H” I2C Bus Address Pin 0 12 DVSS - Ground Pin for Digital Section 0.0V 13 DVDD - Power Supply Pin for Digital Section (3.3V typical) 14 SCLK CAD1 9 RDY 10 SO 11 SI SCL 15 SDA SDA 16 TESTO1 17 STO O Serial Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”) When SCLK is not used, tie the SCLK pin = “H”. 2 I I C Bus Data Clock Pin (I2CSEL pin = “H”) Test Pin (I2CSEL pin = “L”) I/O Leave open. SDA goes “L”. 2 I/O I C Bus Data Clock Pin (I2CSEL pin = “H”) Test Output Pin O Leave open. Normally TESTO1 goes “L”. I O Status Output Pin Digital Power Supply Microprocessor Interface I2C TEST I2C TEST Status MS0578-E-01-PB 2007/09 - 4 - [AK7752] No. Pin Name 18 DLINE_IN 19 DEXT_IN/ JX3 20 JX2 21 JX1 22 JX0 23 24 DVDD DVSS I/O Function Classification Digital Section HF Serial Data Input Pin ( Internal pull-down ) I Compatible with MSB / LSB justified 24, 20 and 16 bits. Normally connected Serial Input to Bluetooth line (receiving). Data Digital Section Serial Input HF Serial Data Input Pin ( Internal pull-down ) I Compatible with MSB / LSB justified 24, 20 and 16 bits. This pin changes to Data / Conditional a conditional jump pin (JX3) by setting control register (JX3_E) to “1”. Input Conditional Jump Pin2 (Internal pull-down) Conditional I A conditional jump pin (JX2) is available by setting control register (JX2_E) Input to “1”. Conditional Jump Pin1 (Internal pull-down) I A conditional jump pin (JX1) is available by setting control register (JX1_E) to “1”. Conditional Jump Pin0 (Internal pull-down) I A conditional jump pin (JX2) is available by setting control register (JX0_E) to “1”. - Power Supply for Digital Section (3.3V typical) - Ground Pin for Digital Section 0V Serial Bit Clock Input Pin 25 BITCLK_I I Normally connected to the Bluetooth Data Clock line (256kHz/512kHz). SYNC Input Pin 26 SYNC_I I Normally connected to the Bluetooth Sync Clock line (8kHz). Reset Pin (for initialization) 27 INIT_RESET_N I Use to initialize the AK7752. When changing CKM [3:0] and changing XTI or BITCLK_I input frequency, it is necessary to set this pin. Clock Reset Pin When changing CKM[3:0] and XTI or BITCLK_I input frequency without 28 CK_RESET_N I using INIT_RESET_N, it is necessary to set this pin. The control register CKRST has the same function. 29 S_RESET_N I System Reset N Pin 30 CKM[3] I Clock Mode Select Pin 3 31 CKM[2] I Clock Mode Select Pin 2 Clock Output Pin 1 32 CLKO1 O The output frequency is selected by a control register. MS0578-E-01-PB Digital Power Supply System Clock Reset Mode Select Clock Output 2007/09 - 5 - [AK7752] No. Pin Name I/O 33 DEXT3_OUT O 34 EEST /RSTO_N Function HF Serial Data Output Pin The data format is MSB justified. EES Output Pin / Internal Reset Monitor Pin Set by control resistor SEL_EEST. O SEL_EEST bit= “0”: EEST pin SEL_EEST bit= “1”: RSTO_N Monitor internal reset process. RSTO_N pin =“L”: Reset mode, RSTO_N pin =“H”: Exit reset mode. 35 DEXT2_OUT O 36 DEXT1_OUT O 37 DLINE_OUT O 38 BITCLK_O O 39 SYNC_O O 40 41 DVDD DVSS - 42 XTO O 43 XTI I 44 45 DVSS DVDD - 46 BVSS - 47 EESEL I 48 I2CSEL I 49 TESTI2 I HF Serial Data Output Pin Compatible with MSB / LSB justified 24, 20 and 16 bits. HF Serial Data Input Pin Compatible with MSB / LSB justified 24, 20 and 16 bits. HF Serial Data Output Pin Compatible with MSB / LSB justified 24, 20 and 16 bits. Normally connected to Bluetooth line (sending). Serial Bit Clock Output Pin Normally goes “L” by control register setting. Master Mode: Outputs 64fs or 32fs clock. Slave Mode: Outputs BITCLK_I clock. SYNC Output Pin Normally goes “L” by control register setting. Master Mode: Outputs 64fs or 32fs clock. Slave Mode: Outputs SYNC_I clock. Power Supply for Digital Section (3.3V typical) Ground Pin for Digital Section 0V Crystal oscillator output pin When a crystal oscillator is used, connect it between XTI and XTO. When an external clock is used, leave this pin open. Crystal oscillator input pin Connect a crystal oscillator between this pin and the XTO pin, or input an external CMOS clock to the XTI pin. Ground Pin for Digital Section 0V Power Supply for Digital Section (3.3V typical) Silicon Substrate Potential 0V Connect to AVSS. Control Mode select pin (Internal pull-down) EESEL pin = “L” : Normal mode EESEL pin = “H”: In self-boot up mode using an AKM EEPROM, AK6514C I2C BUS Select Pin (Internal pull-down) I2CSEL pin = “L”: Normal serial interface I2CSEL pin = “H”: I2CBus selected mode. SCL and SDA are active. I2CSEL should be connected to “L” (DVSS) or “H” (DVDD). TEST pin (Internal pull-down) Connect to DVSS. MS0578-E-01-PB Classification TEST EEPIF/ Monitor Digital Section Serial Input Data System Clock Digital Power Supply System Clock Digital Power Supply Analog Power Supply EEPIF I2C Select TEST 2007/09 - 6 - [AK7752] No. 50 51 52 53 54 55 56 57 58 Pin Name CKM[1] CKM[0] I/O Function I Clock Mode Select Pin 1 I Clock Mode Select Pin 0 TEST pin (Internal pull-down) TESTI1 I Connect to DVSS. PLL RC component connect pin LFLT O Connect a series resistor and capacitor pair to this pin. AVSS - Analog ground Pin 0V (Silicon substrate potential) AVDD - Power Supply Pin for Analog Section (3.3V typical) ADC Analog Input Pin (ANE_IN) ANE_IN I Normally connected to the microphone amplifier. ADC Analog Input Pin (ALINE_IN) ALINE_IN I Normally the receiving analog phone voice signal is input. AVDD Classification Mode Select TEST Analog Output Analog Power Supply Analog Input Analog Power Supply - Analog Power Supply Pin (3.3V typical) Analog Reference Voltage Input Pin Connect this pin to AVDD. Connect capacitors of 0.1 uF and 10 uF between this Analog Input pin and AVSS. Analog Common Voltage Output pin 60 VCOM O Connect capacitors of 0.1 uF and 10 uF between this pin and AVSS. No external Analog Output circuits should be connected to this pin. Analog Reference Voltage Input pin 61 VREFL I Analog Input Connect this pin to AVSS. Analog 62 AVSS - Analog ground Pin 0V (Silicon substrate potential) Power Supply DAC Analog Output Pin (ALINE_OUT) 63 ALINE_OUT O Normally the sending analog phone voice signal is output. Analog Output DAC Analog Output Pin (ANE_OUT) 64 ANE_OUT O Normally connected to the speaker amplifier. 59 VREFH I Note 1. Do NOT leave digital input pins open except for pins that indicate “Internal pull down”, BITCLK_I and SYNC_I at master mode. (Internal pull down pins except TEST1 and TEST2 pins leave them open or connect them to DVSS. Connect TEST1 and TEST2 pins to DVSS). Note 2. When analog input pins (ALINE_IN, ANE_IN) are not used, leave them open. Note 3. Connect I2CSEL to “L” (DVSS) or “H” (DVDD). Relationship between I2CSEL and SDA uP I/F I2CSEL Normal Serial Interface I2C Bus Mode INIT_RESET_N L H L H L L H H MS0578-E-01-PB SDA L L “Hi-Z” → pull-up function 2007/09 - 7 - [AK7752] ABSOLUTE MAXIMUM RATINGS (AVSS, BVSS, DVSS=0V: All voltages are with respect to ground) Parameter Symbol min Power Supply Voltage Analog (AVDD) VA -0.3 Digital (DVDD) VD -0.3 |AVSS(BVSS) – DVSS| (Note 4) ΔGND Input Current (except for power supply pin ) IIN Analog Input Voltage VINA -0.3 ALINE_IN, ANE_IN Digital Input Voltage VIND -0.3 Operating Ambient Temperature Ta -40 Storage Temperature Tstg -65 Note 4. AVSS, BVSS and DVSS must be connected to the same ground plane.. max Units 4.6 4.6 0.3 ±10 V V V mA VA+0.3 V VD+0.3 85 150 V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, BVSS, DVSS=0V: All voltages indicated are relative to the ground) Parameter Symbol min typ max Power Supply Voltage AVDD VA 3.0 3.3 3.6 DVDD VD 3.0 3.3 3.6 Reference Voltage (VREF) VREFH (Note 5) VRH VA VREFL (Note 6) VRL 0.0 Units V V V V Note 5. VREFH is normally connected to AVDD. Note 6. VREFL is normally connected to AVSS Note: The analog input voltage and output voltage are proportional to the VREFH-VREFL voltages. When using the AK6514C, the same voltage as used for the digital section of the AK7752 is recommended. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0578-E-01-PB 2007/09 - 8 - [AK7752] ELECTRIC CHARACTERISTICS (1) Analog Characteristics 1) fs=8kHz (Ta = 25°C; AVDD, DVDD = 3.3V; VREFH = AVDD, VREFL = AVSS; BITCLK = 64fs; Signal frequency 1kHz; Measurement frequency = 20Hz to 3.4 kHz; fs = 8kHz; CKM Mode 0 (CKM[3:0]=LLLL) Unless otherwise specified.) Parameter min typ max Resolution 24 ADC Section Dynamic Characteristics S/(N+D) (-1dBFS) 76 86 Dynamic Range (Note 7) 81 89 S/N 81 89 Inter-Channel Isolation (f=1kHz) (Note 8.) 90 105 DC accuracy Channel Gain Mismatch 0.2 0.5 Analog Input Input Voltage (Note 9) 1.78 1.98 2.18 Input Impedance 40 60 Resolution 18 DAC Section Dynamic Characteristics S/(N+D) (0dB) 80 90 Dynamic Range (Note 7) 87 95 S/N 87 95 Inter-Channel Isolation (f=1kHz) (Note 10) 85 100 DC accuracy Channel Gain Mismatch 0.2 0.5 Analog Output Output Voltage (Note 11) 1.85 2.00 2.15 Load Resistance 10 Load Capacitance 50 Units Bits dB dB dB dB dB Vp-p kΩ Bits dB dB dB dB dB Vp-p kΩ pF Note 7. S/(N+D) when -60dB signal is applied. Note 8. Inter-channel isolation between ALINE_IN and ANE_IN at –1dB FS signal input. Note 9. The full scale for analog input voltage is FS = (VREFH-VREFL) ∗ 0.6. Note 10. Between ANE_OUT and ALINE_OUT. Note 11. Full scale output voltage when VREFH = AVDD, VREFL = AVSS. MS0578-E-01-PB 2007/09 - 9 - [AK7752] 2) fs=48kHz (Ta = 25°C; AVDD, DVDD = 3.3V; VREFH = AVDD, VREFL = AVSS; BITCLK = 64fs; Signal frequency 1kHz; Measurement frequency = 20Hz to 3.4kHz; fs = 48kHz; CKM Mode 0 (CKM [3:0]=LLLL) Unless otherwise specified. ) Parameter min typ Resolution ADC Section Dynamic Characteristics S/(N+D) (-1dBFS) 76 86 Dynamic Range (A-weighted) (Note 12) 83 91 S/N (A-weighted) 83 91 Inter-Channel Isolation (f=1kHz) (Note 13) 90 110 DC accuracy Channel Gain Mismatch 0.2 Analog Input Input Voltage (Note 14) 1.80 2.00 Input Impedance 35 50 Resolution DAC Section Dynamic Characteristics S/(N+D) (0 dB) 78 88 Dynamic Range (A-weighted) (Note 12) 87 95 S/N (A-weighted) 87 95 Inter-Channel Isolation (f=1kHz) (Note 15) 85 100 DC Accuracy Channel Gain Mismatch 0.2 Analog input Output Voltage (Note 16) 1.85 2.00 Load Resistance 10 Load Capacitance max 24 Units Bits dB dB dB dB 0.5 dB 2.20 Vp-p kΩ Bits 18 dB dB dB dB 0.5 dB 2.15 Vp-p kΩ pF 50 Note 12. S/(N+D) when -60dB signal is applied. Note 13. Inter-channel isolation between ALINE_IN and ANE_IN at –1 dB FS signal input. Note 14. The full scale for analog input voltage is FS=(VREFH-VREFL)×0.606. Note 15. Between ANE_OUT and ALINE_OUT. Note 16. Full scale output voltage when VREFH=AVDD, VREFL=AVSS. MS0578-E-01-PB 2007/09 - 10 - [AK7752] (2) DC Characteristics (Ta=-40°C ~ 85°C; AVDD, DVDD=3.0 ~ 3.6V) Parameter High Level Input Voltage (Note 17) Low Level Input Voltage (Note 17) SCL, SDA High Level Input Voltage SCL, SDA Low Level Input Voltage High Level Output Voltage Iout=-100μA (Note 18) Low Level Output Voltage Iout=100μA SDA Low Level Output Voltage Iout=3mA Input Leak Current (Note 19) Input Leak Current (pull-down pin) (Note 20) Input Leak Current (XTI pin) Symbol min VIH VIL VIH VIL VOH VOL VOL Iin Iid Iix 80%VDD typ max Units 20%VDD 70%VDD 30%VDD VDD-0.5 0.5 0.4 ±10 22 26 V V V V V V V μA μA μA Note 17. SCL and SDA pins are not included. (SI, SCLK pins are included) Note 18. SDA pin is not included. Note 19. Pull-down pins and XTI pin are not included. Note 20. EESO, DLINE_IN, DEXT_IN / JX3, JX2, JX1, JX0, EESEL, I2CSEL, TESTI2 and TESTI1 (Typ150kΩ) (3) Current Consumption (Ta=25°C; AVDD, DVDD=3.0~3.6V (typ = 3.3V, max = 3.6V) Parameter min Power Supply Current (Note 21) AVDD DVDD AVDD + DVDD typ 10 90 100 max Units 165 mA mA mA Note 21. The current of DVDD changes depending on the system frequency and contents of the DSP program. MS0578-E-01-PB 2007/09 - 11 - [AK7752] (4) Digital Filter Characteristics 1) ADC Section: (Ta= 25°C; AVDD, DVDD=3.0 ~ 3.6V; fs = 8kHz; Note 22) Parameter Symbol min Passband (±0.1dB) (Note 23) PB 0 (-1.0dB) (-3.0dB) Stopband SB 4.66 Passband Ripple (Note 23) PR Stopband Attenuation (Note 24, Note 25) SA 65 Group Delay Distortion GD Group Delay (Ts=1/fs) GD typ max 3.15 3.63 3.83 ±0.1 0 16.3 Units kHz kHz kHz kHz dB dB μs Ts Note 22. HPF response is not included. Note 23. The passband is from DC to 3.15kHz when fs = 8kHz. Note 24. The stopband is from 4.66kHz to 507.34kHz when fs = 8kHz. Note 25. When fs = 8 kHz, the analog modulator samples the analog input at 512kHz 2) DAC Section: (Ta=25°C; AVDD, DVDD=3.0~3.6V; fs=8kHz) Parameter Symbol Digital Filter Passband (±0.1dB) (Note 26) PB (-6.0dB) Stopband (Note 26) SB Passband Ripple PR Stopband Attenuation SA Group Delay (Ts=1/fs) (Note 27) GD Digital Filter + SCF Amplitude Characteristics 0~3.5kHz min typ max Units 0 4.57 4.0 3.5 - 15 kHz kHz kHz dB dB Ts ±0.5 dB ±0.01 59 - Note 26. The pass band and stop band frequencies are proportional to “fs” (system sampling rate), and represents PB=0.4292fs (@-0.06dB) and SB=0.571fs, respectively. Note 27. The digital filter’s delay is calculated as the time from setting 18 Bit data into the input register until an analog signal is output. MS0578-E-01-PB 2007/09 - 12 - [AK7752] (5) Switching Characteristcis 1) System Clock (Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V) Parameter Symbol XTI CKM Mode 0-6 a) with a Crystal Oscillator: Frequency (CKM Mode 0/2) fXTI Frequency (CKM Mode 1/3) b) with an External Clock Duty Cycle Frequency (CKM Mode 0/2) Frequency (CKM Mode 1/3) Clock Rise Time Clock Fall Time SYNC_I Frequency (Note 28) fXTI Clock rise time Clock fall time BITCLK_I Frequency High Level Width Low Level Width Clock Rise Time Clock Fall Time a) CKM Mode 2/3 (Note 29) Duty Cycle Frequency (CKM Mode 2/3) b) CKM Mode 4 (Note 30) Duty Cycle Frequency (CKM Mode 4) c) CKM Mode 5/6 (Note 31) Duty Cycle Frequency (CKM Mode 5) Frequency (CKM Mode 6) tLR tLF fXTI fXTI tCR tCF Fs tBCLKH tBCLKL tBR tBF fBCLK fBCLK fBCLK fBCLK fBCLK fBCLK min typ max Units - 11.2896 12.288 24.576 - MHz - MHz 40 11.0 22 50 7.35 8 60 12.4 24.8 6 6 48 % MHz MHz ns ns kHz 6 6 ns ns 6 6 64 60 3.2 60 258 60 516 3.1 ns ns ns ns fs % MHz fs % kHz fs % kHz MHz - 120 120 32 40 0.23 40 230 40 460 2.75 50 32 50 256 64 50 512 3.072 Note 28. SYNC_I frequency and sampling rate (fs) should be the same. Note 29. When BITCLK_I is 32fs, I/O interface format has some limitation. Note 30. When BITCLK_I is a source of master clock, it should be 32 times fs correctly. Note 31. When BITCLK_I uses as a source of master clock, it should be 64 times fs correctly. MS0578-E-01-PB 2007/09 - 13 - [AK7752] 2) Reset (Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V) Parameter Symbol min typ max Units INIT_RESET_N (Note 32) tRST 600 ns CK_RESET_N tRST 600 ns S_RESET_N tRST 600 ns Note 32. The AK7752 can be powered up when INIT_RESET_N pin = “L”. The power supply must be ON and the master clock must be input before the INIT_RESET_N pin transitions “H”. 3) Audio interface (Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V; CL=20pF) Parameter Symbol Slave Mode (CKM Mode 2-4) Delay Time from BITCLK_I “↑” to SYNC_I (Note 33) tBLRD Delay Time from SYNC_I to BITCLK_I “↑” (Note 33) tLRBD Delay Time from SYNC_I,_O to Serial Data Output tLRD Delay Time from BITCLK_I,_O to Serial Data Output tBSOD Serial Data Output Latch Setup Time tBSIDS Serial Data Input Latch Hold Time tBSIDH Master Mode (CKM Mode 0-1) BITCLK_O Frequency (BIT32FS bit = “0”) fBCLK BITCLK_O Frequency (BIT32FS bit = “1”) BITCLK_O Duty Factor Delay Time from BITCLK_O “↑” to SYNC_O (Note 34) tBLRD Delay Time from SYNC_O to BITCLK_O “↑” (Note 34) tLRBD Delay Time from SYNC_O to Serial Data Output tLRD Delay Time from BITCLK_O to Serial Data Output tBSOD Serial Data Output Latch Setup Time tBSIDS Serial Data Input Latch Hold Time tBSIDH min typ max Units 80 80 Ns Ns ns ns ns ns 60 60 80 80 64 32 50 60 60 80 80 80 80 fs fs % ns ns ns ns Ns ns Note 33. BITCLK_I “↑“ must not occur at the same time as SYNC_I edge. Note 34. BITCLK_O “↑“ must not occur at the same time as SYNC_O edge. (When control register SEL_BCK bit = “0”. The edge reverses when SEL_BCK bit = “1”.) MS0578-E-01-PB 2007/09 - 14 - [AK7752] 4) Microprocessor Interface (Ta=-40ºC~85ºC; AVDD, DVDD=3.0~3.6V; CL=20pF) Parameter Microprocessor Interface Signal RQ_N Fall Time RQ_N Rise Time SCLK Fall Time SCLK Rise Time SCLK Frequency SCLK Low Level Width SCLK High Level Width Microprocessor to AK7752 Time from S_RESET_N “↓” to RQ_N “↓” Time from RQ_N “↑” to S_RESET_N “↑” RQ_N High Level Width Time from RQ_N “↓” to SCLK “↓” Time from SCLK “↑” to RQ_N “↑” SI Latch Setup Time SI Latch Hold Time Delay Time from SCLK “↓“ to SO Output Hold Time from SCLK “↑“ to SO Output Time from RQ_N “↓” to SO Hi-Z Release (Iout=±360μA) RQ_N “↑” to SO Hi-Z set (Iout=±360μA) Symbol tWRF tWRR tSF tSR fSCLK tSCLKL tSCLKH tREW tWRE tWRQH tWSC tSCW tSIS tSIH tSOS tSOH MS0578-E-01-PB min typ max Units 30 30 30 30 2.1 ns ns ns ns MHz ns ns 200 200 500 500 500 500 800 200 200 200 200 ns ns ns ns ns ns ns ns ns tRQHR 600 ns tRQHS 600 ns 2007/09 - 15 - [AK7752] 5) I2CBUS Interface (Ta=-40ºC~85ºC; AVDD, DVDD=3.0~3.6V) Parameter I2C Timing SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first Clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed By Input Filter Capacitive Load on Bus Symbol min fSCL tBUF tHD:STA 1.3 0.6 tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP typ 1.3 0.6 0.6 0 0.1 max Units 400 KHz μs μs 50 μs μs μs μs μs μs μs μs ns 400 pF max Units 0.9 0.3 0.3 0.6 0 Cb Note 35. I2C is a registered trademark of Philips Semiconductors. 6) EEPROM Interface (Ta=-40ºC ~ 85ºC; AVDD, DVDD=3.0 ~ 3.6V; CL=20pF) Parameter Symbol EEPROM→AK7752 EESO Latch Setup Time (EESEL pin = “H”) tEESOS EESO Latch Hold Time (EESEL pin = “H”) tEESOH Time from EESEL “↑” to EECS_N, EECK, EESI tESLHR Hi-Z release (Iout=±360μA) Time from EESEL “↓” to EECS_N, EECK, EESI tESLHS Hi-Z set (Iout=±360μA) MS0578-E-01-PB min typ 160 160 ns ns 600 ns 600 ns 2007/09 - 16 - [AK7752] (6) Timing Diagram 1/fXTI 1/fXTI tXTI=1/fXTI XTI VIH VIL tCR tCF 1/fs ts=1/fs 1/fs SYNC_I VIH VIL tLR 1/fBCLK tLF tBCLK=1/fBCLK 1/fBCLK VIH BITCLK_I VIL tBR tBF tBCLKH tBCLKL Figure 2. System Clock INIT_RESET_N CK_RESET_N tRST S_RESET_N VIL Figure 3. Reset MS0578-E-01-PB 2007/09 - 17 - [AK7752] SYNC_I SYNC_O 50%DVDD tBLRD tLRBD 50%DVDD BITCLK_I BITCLK_O DLINE_OUT DEXT1_OUT DEXT2_OUT DEXT3_OUT tLRD tBSOD 50%DVDD tBSIDH tBSIDS 50%DVDD DLINE_IN DEXT_IN Figure 4. Audio Interface VIH VIL RQ_N tWRF tWRR Figure 5. Microprocessor Interface Signal 1 tSF tSR VIH VIL SCLK tSCLKH tSCLKL 1/fSCLK 1/fSCLK Figure 6. Microprocessor Interface Signal 2 MS0578-E-01-PB 2007/09 - 18 - [AK7752] VIH tWRQH RQ_N VIL VIH SI VIL tSIS tSIH VIH SCLK VIL tWSC tSCW tWSC tSCW VIH SO VIL tSOS tSOH Figure 7. Microprocessor Æ AK7752 VIH RQ_N VIL tRQHR tRQHS VOH SO VOL Figure 8. Microprocessor Æ AK7752 MS0578-E-01-PB 2007/09 - 19 - [AK7752] VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start Figure 9. I2C Bus Interface EECK 50%DVDD EESO 50%DVDD tEESOS tEESOH Figure 10. EEPROM Interface 1 VIH EESEL VIL tESLHR tESLHS VOH EECS_N, EECK, EESI VOL Figure 11. EEPROM Interface 2 MS0578-E-01-PB 2007/09 - 20 - [AK7752] PACKAGE 64pin LQFP (Unit: mm) 12.0±0.3 Max 1.70 1.40 10.0 0.10±0.10 48 33 32 1 17 16 12.0±0.3 49 64 0.5 0.17±0.05 0.21±0.05 0.10 M 1.0 0°~10° 0.45 ±0.2 0.10 Material & Lead finish Package: Lead-frame: Lead-finish: Epoxy Copper Soldering plate (Pb free) MS0578-E-01-PB 2007/09 - 21 - [AK7752] MARKING AKM AK7752VT XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX (7 digits) 3) Marking Code: AK7752VT 4) Asahi Kasei Logo IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of As ahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or sy stem containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its fail ure to function or perform may reasonably be expected to result in loss of life or in significant injur y or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0578-E-01-PB 2007/09 22 [AK7752] Thank you for your access to AKEMD product informations. More detail product informations are available, please contact our sales office or authorized distributors. MS0578-E-01-PB 2007/09 23