[AK7734] AK7734 Audio DSP with 2-Channel ADC/SRC GENERAL DESCRIPTION The AK7734 is a highly integrated audio digital signal processor with integrated 2ch 24bit ADC and 2ch SRC. It includes internal memories for digital audio processing, that allows surround effect process, time alignment and parametric equalizing. More over, the AK7734 can process both data and filter coefficients as floating point data so that high accuracy IIR/FIR filter performance can be achieved easily. The internal SRC has various sampling rate converting modes, corresponds many sampling rates without changing the DSP operating sampling frequency. The AK7734 can operate a hands-free software by AKM, as well as sound processing, by programs downloaded via the microprocessor interface. FEATURES [DSP Block] - Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point) - Processing Speed: 13.6 ns (1536step/fs; fs = 48kHz) - Multiplication: 20 x 24 → 44-bit Double precision arithmetic available - Divider 20 / 20 → 20bit - ALU: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic and logic operation - Program RAM: 3072 x 24bit - Coefficient RAM: 2048 x 24bit (F24 floating point) - Data RAM: 2048 x 24-bit (F24 floating point) - Offset Register: 64 x 13bit - Delay RAM1: 3072 x 24-bit - Delay RAM2: 2048 x 24-bit - Sampling rate: fs= 7.35k ~ 48kHz - Master Clock: 1536fs (generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL) - Master/Slave Operation [ADC Block] - 64 times Over sampling - 24bit 2ch - Sampling rate: 7.35 ~ 48kHz - S/(N+D): 83dB (fs = 48kHz) - DR, S/N: 96dB (fs = 48kHz) - Integrated DC offset canceling High Pass Filter [SRC Block] - 2ch x 1 system - Support frequency: Fin = 7.35kHz ~ 96kHz → Fout = 7.35kHz ~ 48kHz (FSO/FSI = 0.167~ 6.0) [Digital Interface Input/Output] - 8ch Serial Data Input - 8ch Serial Data Output MS1033-E-02-PB - 1 - 2010/01 [AK7734] [Micro Computer Interface] - I2C Interface or 4-wired Interface [General] - Integrated PLL - Integrated Regulator 3.3V → 1.8V - Power Supply: 3.3V ± 0.3V - Operating Temperature Range: -40˚C ~ 85˚C - 48pin LQFP MS1033-E-02-PB - 2 - 2010/01 [AK7734] ■ Block Diagram VCOM ADC AINR VREF AINL AVDRV LDO SDOUTAD 1 AVDD 4 DVDD CLKOE CLKO 5 VSS BITCLKOE BITCLKO LRCLKOE LRCLKO LFLT XTO Pull Down Open Drain XTI CLKGEN & CONT BITCLKI1 LRCLKI1 INITRSTN CKM[3:0] TESTI1 TESTI2 MICIF MLRCLK0 MBITCLK0 4 4 SELRDY SO RDY MADCLK0 MDSPCLK0 DIN5 SDIN1 DOUT1 JX0 DIN2 DOUT2 GP1 SDIN2 / JX0 JX1E GP0 JX1 SDIN3 / JX1 DIN3 0 1 2 3 CKG SETSRC SRCLFLT SDOUT1 0 1 2 3 SELDO3[1:0] 0 1 2 3 DOUT3 OUT2E OUT3E SDOUT2 SDOUT3 RDYE UNLOCK SRCMCKI SRCBICKI SRCBICKO SRCLRCKI SRCLRCKO STO LOCKE WDTEN WDT SRC DSP SELDI4 SDIN4 / JX2 OUT1E SELDO2[1:0] IRPT BITCLKI2 LRCLKI2 SO / RDY SELDO1[1:0] DIN1 JX0E 0 1 I2CSEL RQN / CAD1 SI / CAD0 SCLK / SCL SDA SRCO SRCI SELDO4 0 1 DIN4 JX2E DOUT4 0 1 OUT4E SDOUT4 JX2 Figure 1. Block Diagram * Figure 1 shows a simplified diagram of the AK7734, which is not the perfect same as the actual circuit diagram. MS1033-E-02-PB - 3 - 2010/01 [AK7734] CP0,CP1 DLP0,DLP1 DP0,DP1 DLRAM1:3072W×24-Bit DRAM 2048w×24-Bit CRAM 2048W×24-Bit OFREG 64w×13-Bit DLRAM2:2048W×24-Bit CBUS(24-Bit) DBUS(24-Bit) MP×24 Micon I/F MP×20 X Control PRAM DEC Y Serial I/F 3072w × 36-Bit Multiply 24×20 → 44-Bit PC Stack: 5level(max) TMP 12×24-Bit 24-Bit 44-Bit PTMP(LIFO) 6×24-Bit MUL DBUS SHIFT 48-Bit 44-Bit A B ALU 48-Bit 2×24(,16)-Bit DIN5 (ADC) 2×24(,16)-Bit DIN4 (SRC) 2×24,20,16-Bit DIN3 2×24,20,16-Bit DIN2 2×24,20,16-Bit DIN1 Overflow Margin: 4-Bit 48-Bit DR0 ∼ 3 48-Bit Over Flow Data Generator Division 20÷20→20 2×24,20,16-Bit DOUT4 2×24,20,16-Bit DOUT3 2×24,20,16-Bit DOUT2 2×24,20,16-Bit DOUT1 Peak Detector Figure 2. Main DSP Block Diagram of The AK7734 MS1033-E-02-PB - 4 - 2010/01 [AK7734] ■ Ordering Guide -40 ∼ +85°C 48pin LQFP Evaluation Board for AK7734 AK7734XQ AKD7734 VSS3 DVDD SCLK/SCL SDA SI/CAD0 RQN/CAD1 JX2/SDIN4 BITCLKI2 LRCLKI2 SO/RDY STO 34 33 32 31 30 29 28 27 26 25 VSS4 35 37 AVDRV SRCLFLT 36 ■ Pin Layout DVDD AINL 44 17 VSS2 AVDD 45 16 SDOUT1 VCOM 46 15 SDOUT2 VSS5 47 14 SDOUT3 LFLT 48 13 SDOUT4 12 18 XTO (TOP VIEW) 11 43 XTI AINR 10 I2CSEL VSS1 19 9 42 DVDD INITRSTN 8 20 TESTI2 48pin LQFP LRCLKI1 41 7 SETSRC BITCLKI1 CKM [0] 6 21 JX1/SDIN3 40 JX0/SDIN2 CKM [3] 5 LRCLKO 4 22 SDIN1 39 3 DVDD CKM [1] BITCLKO CKM [2] 23 2 38 1 CLKO TESTI1 24 Note) XXXX is internal pull-down pin. XXXX is the pin name. MS1033-E-02-PB 5 pin Input Output I/O Power 2010/01 [AK7734] PIN FUNCTION No. Name 1 TESTI1 2 3 4 CKM[2] CKM[1] SDIN1 5 JX0 SDIN2 6 JX1 SDIN3 7 BITCLKI1 8 LRCLKI1 9 DVDD 10 VSS1 11 XTI 12 XTO 13 SDOUT4 14 SDOUT3 15 SDOUT2 16 SDOUT1 17 VSS2 18 DVDD 19 I2CSEL 20 INITRSTN 21 CKM[0] 22 LRCLKO MS1033-E-02-PB I/O Function Classification I Test1 Pin (Internal pull-down) Test This pin must be connected to VSS. I Clock Mode Select Pin2 Mode Select I Clock Mode Select Pin1 Mode Select I Serial Data Input Pin1 Digital Input Conditional Jump Pin0 I A conditional jump pin (JX0) is available by setting control register (JX0E) to Conditional Input “1”. I Serial Data Input Pin2 Digital Input Conditional Jump Pin1 I A conditional jump pin (JX1) is available by setting control register (JX1E) to Conditional Input “1”. I Serial Data Input Pin2 Digital Input Serial Bit Clock Input Pin1 I System Clock Normally connected to the Bluetooth Data Clock line (256kHz/512kHz). LR Channel Select Clock Pin1 I System Clock Normally connected to the Bluetooth LR Clock line (8kHz). Digital - Power Supply for Digital Section 3.0V ~ 3.6V Power Supply - Ground Pin 0V Power Supply Crystal oscillator input pin I Clock Connect a crystal oscillator between this pin and the XTO pin, or input an external clock to the XTI pin. Crystal oscillator output pin When a crystal oscillator is used, connect it between XTI and XTO. When an O Clock external clock is used, leave this pin open. During initial reset, the output of this pin is not determinable. O Serial Data Output Pin4 Digital Output Outputs “L” during initial reset. O Serial Data Output Pin3 Digital Output Outputs “L” during initial reset. O Serial Data Output Pin2 Digital Output Outputs “L” during initial reset. O Serial Data Output Pin1 Digital Output Outputs “L” during initial reset. - Ground Pin 0V Power Supply Digital - Power Supply for Digital Section 3.0V ~ 3.6V Power Supply I2C BUS Select Pin (Internal pull-down) I2CSEL pin = “L”: 4-wired Interface I I2C Select I2CSEL pin = “H”: I2CBus selected mode. SCL and SDA are active. I2CSEL should be connected to “L” (VSS) or “H” (DVDD). Reset Pin (for initialization) I Use to initialize the AK7734. When changing CKM [3:0] and changing XTI Reset or BITCLK input frequency, it is necessary to set this pin. I Clock Mode Select Pin Mode Select O LR Channel Select Clock Pin System Clock Outputs “L” during initial reset in master mode. Output 6 2010/01 [AK7734] No. Name 23 BITCLKO 24 CLKO 25 STO SO 26 RDY I/O Function O Serial Bit Clock Output Pin Outputs “L” during initial reset in master mode. O Clock Output Pin Outputs “L” during initial reset. Status Output Pin O Outputs “H” during initial reset. Serial Data Output Pin for Microprocessor Interface O Outputs “L” during initial reset. Data Write Ready Output Pin for Microprocessor Interface O Outputs RDY when SELRDY bit = “1” 27 LRCLKI2 I LR Channel Select Clock Pin2 (for SRC) 28 BITCLKI2 I Serial Bit Clock Input Pin2 (for SRC) JX2 29 SDIN4 30 RQN CAD1 31 SI CAD0 32 SDA 33 SCLK SCL 34 DVDD 35 VSS3 36 AVDRV 37 SRCLFLT 38 VSS4 39 DVDD 40 CKM[3] 41 SETSRC 42 TESTI2 43 AINR MS1033-E-02-PB Classification System Clock Output Clock Output Status Microprocessor Interface Microprocessor Interface System Clock Input System Clock Input I Conditional Jump Pin2 A conditional jump pin (JX2) is available by setting control register (JX2E) Conditional Input to “1”. Serial Data Input Pin4 I Digital Input Normally used for SRC serial data input pin. Microprocessor Interface Write Request Pin (I2CSEL pin = “L”) Microprocessor I When initial reset state and Microcomputer interface are not in use, leave Interface RQN pin= “H”. 2 I2C I I C Bus Address Setting Pin 1 (I2CSEL pin = “H”) I Serial Data Input Pin for Microprocessor Interface (I2CSEL pin = “L”) Microprocessor When SI is not used, tie the SI pin = “L”. Interface I2C I I2C Bus Address Setting Pin 0 (I2CSEL pin = “H”) O I2CSEL pin = “L” Open Leave this pin Open. SDA outputs “L”. 2 I/O I C Bus Data Clock Pin (I2CSEL pin = “H”) I2C Outputs “Hi-z” during initial reset. I Serial Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”) Microprocessor When SCLK is not used, tie the SCLK pin = “H”. Interface I2C I I2C Bus Data Clock Pin (I2CSEL pin = “H”) Digital Power Supply for Digital Section 3.0V ~ 3.6V Power Supply - Ground Pin 0V Power Supply O AVDRV Pin Connect a 1μF capacitor between this pin and No.35 pin (VSS3). No Analog Output external circuits should be connected to this pin. This pin outputs “L” during initial reset. O SRC, PLL RC component connect pin Connect a 1μF capacitor between this pin and VSS4. This pin outputs “L” Analog Output during initial reset. - Ground Pin 0V Power Supply Digital Power Supply for Digital Section 3.0V ~ 3.6V Power Supply I Clock Mode Select Pin3 Mode Select I PLL Reference Clock Select Pin for SRC Mode Select I Test2 Pin (Internal pull-down) Test This pin must be connected to VSS. I ADC Single-ended Input Pin for Rch Analog Input 7 2010/01 [AK7734] No. Name 44 AINL I/O Function I ADC Single-ended Input Pin for Lch 45 AVDD Classification Analog Input Analog Power Supply I Analog Ground 0V Analog Common Voltage Output pin Connect 0.1μF and 2.2μF capacitors between this pin and No.47 pin O (VSS5). No external circuits should be connected to this pin. This pin outputs “L” during initial reset. I Ground Pin 0V PLL RC component connect pin Connect C=12nF between this pin and No.47 (VSS5). This pin outputs “L” O during initial reset. 46 VCOM 47 VSS5 48 LFLT Analog Output Power Supply Analog Output Note: • Do NOT leave digital input pins open. • When analog input pins (AINL, AINR) are not used, leave them open. ■ Handling of Unused Pin The following table illustrates recommended states for open pins: Classification Analog Digital Pin Name AINL, AINR SDOUT1-4, CLKO, LRCLKO, BITCLKO, STO, SO/RDY, XTO TESTI1, TESTI2, SDIN1, JX0-2/SDIN2-4, XTI, BITCLKI1-2, LRCLKI1-2 MS1033-E-02-PB 8 Setting Leave Open. Leave Open. Connect to VSS. 2010/01 [AK7734] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4=VSS5=0V: Note 1) Parameter Symbol min Power Supply Voltage Analog AVDD -0.3 Digital DVDD -0.3 Input Current (except for power supply pin ) IIN – Analog Input Voltage VINA -0.3 AINL pin, AINR pin Digital Input Voltage VIND -0.3 Operating Ambient Temperature Ta -40 Storage Temperature Tstg -65 Note 1. All indicated voltages are with respect to ground. Note 2. VSS1-5 must be connected to the same ground plane. max Units 4.3 4.3 ±10 V V mA AVDD+0.3 V DVDD+0.3 85 150 V ºC ºC WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4=VSS5=0V: Note 1) Parameter Symbol min typ max Units Power Supply Voltage Analog AVDD 3.0 3.3 3.6 V Digital DVDD 3.0 3.3 3.6 V Note 3. The power supply sequence for AVDD and DVDD is not critical but all power supplies must be On before start operating the AK7734. Note 4. Do not turn off the power supply of the AK7734 with the power supply of the surrounding device turned on. DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and SCL pins.) WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet. MS1033-E-02-PB 9 2010/01 [AK7734] ELECTRIC CHARACTERISTICS (1) Analog Characteristics 1) ADC 1-1) fs=8kHz (Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~3.4kHz @fs=8kHz; CKM mode0(CKM[3:0]=LLLL) Unless otherwise specified.) Parameter min typ max Units Resolution 24 Bits ADC Section Dynamic Characteristics S/(N+D) (-1dBFS) 76 84 dB Dynamic Range (Note 5) 84 92 dB S/N 84 92 dB Inter-Channel Isolation (fin=1kHz) (Note 6) 90 110 dB DC accuracy Channel Gain Mismatch 0.1 0.3 dB Analog Input Input Voltage (Note 7) 1.85 2.00 2.15 Vp-p Input Impedance 38 58 kΩ Note 5. - S/(N+D) when -60dB FS signal is applied. Note 6. Inter-channel isolation between AINR and AINL at –1dB FS signal input. Note 7. Full scale output voltage is FS=AVDD×2.0/3.3. 1-2) fs=48kHz (Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency =20Hz~20kHz @fs=48kHz; CKM mode0(CKM[3:0]=LLLL) Unless otherwise specified.) Parameter min typ max Units Resolution 24 Bits ADC Section Dynamic Characteristics S/(N+D) (-1dBFS) 75 83 dB Dynamic Range (Filter A) (Note 8) 87 96 dB S/N (Filter A) 87 96 dB Inter-Channel Isolation (fin=1kHz) (Note 9) 90 110 dB DC accuracy Channel Gain Mismatch 0.1 0.3 dB Analog Input Input Voltage (Note 10) 1.85 2.00 2.15 Vp-p Input Impedance 23 35 kΩ Note 8. - S/(N+D) when -60dBFS signal is applied. Note 9. Inter-channel isolation between AINR and AINL at –1dB FS signal input. Note 10. Full scale output voltage is FS=AVDD×2.0/3.3. MS1033-E-02-PB 10 2010/01 [AK7734] (2) SRC (Ta=25ºC; AVDD = DVDD=3.3V; VSS=0V, data = 24bit; measurement bandwidth = 20Hz~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units Resolution 24 Bits Input Sample Rate FSI 7.35 96 kHz Output Sample Rate FSO 7.35 48 kHz THD+N (Input= 1kHz, 0dBFS) FSO/FSI=44.1kHz/48kHz -112 dB FSO/FSI=44.1kHz/96kHz -104 dB FSO/FSI=48kHz/44.1kHz -112 dB FSO/FSI=48kHz/96kHz -112 dB FSO/FSI=48kHz/8kHz -111 -103 dB FSO/FSI=8kHz/48kHz -113 dB FSO/FSI=8kHz/44.1kHz -78 dB Dynamic Range (Input= 1kHz, -60dBFS) FSO/FSI=44.1kHz/48kHz 113 dB FSO/FSI=44.1kHz/96kHz 113 dB FSO/FSI=48kHz/44.1kHz 113 dB FSO/FSI=48kHz/96kHz 113 dB FSO/FSI=48kHz/8kHz 109 112 dB FSO/FSI=8kHz/48kHz 113 dB FSO/FSI=8kHz/44.1kHz 113 dB Dynamic Range (Input= 1kHz, -60dBFS, A-weighted FSO/FSI=44.1kHz/48kHz 115 dB Ratio between Input and Output Sample Rate FSO/FSI 0.167 6 - (3) DC Characteristics (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V) Parameter High Level Input Voltage (Note 11) Low Level Input Voltage (Note 11) SCL,SDA High Level Input Voltage SCL,SDA Low Level Input Voltage High Level Output Voltage Iout=-100μA Low Level Output Voltage Iout=100μA (Note 12) SDA Low Level Output Voltage Iout=3mA Input Leak Current (Note 13) Input Leak Current (pull-down pin) (Note 14) Input Leak Current (XTI pin) Symbol VIH VIL VIH VIL VOH VOL VOL Iin Iid Iix min 80%DVDD typ max 20%DVDD 70%DVDD 30%DVDD DVDD-0.5 0.5 0.4 ±10 22 26 Units V V V V V V V μA μA μA Note 11. SCL and SDA pins are not included. (SCLK pins are included) Note 12. SDA pin is not included. Note 13. Pull-down pins, and the XTI pin is not included. Note 14. TESTI1 and TESTI2 pins are internal pulled-down pin. (Typ150kΩ) MS1033-E-02-PB 11 2010/01 [AK7734] (4) Current Consumption (Ta=25ºC; AVDD=DVDD=3.0~3.6V (when typ=3.3V, max=3.6V)) Parameter min typ max Units Power Supply Current (Note 15) 21 AVDD mA 65 DVDD mA 86 AVDD+DVDD 120 mA 2 INITRSTN pin= “L” (reference) (Note 16) mA Note 15. The current of DVDD changes depending on the system frequency and contents of the DSP program. Note 16. This is a reference value when using a crystal oscillator. Since most of the supply current at the initial reset state are in the oscillator section, the value may vary according to the crystal type and the external circuit. This is a “reference data” only. MS1033-E-02-PB 12 2010/01 [AK7734] DIGITAL FILTER CHARACTERISTICS ■ ADC Section 1. fs=8kHz (Ta=-40ºC ~85ºC, AVDD=DVDD=3.0~3.6V, fs=8kHz; Note 17) Parameter Symbol min typ max Units Passband (±0.1dB) (Note 18) PB 0 3.15 kHz (-1.0dB) 3.63 kHz (-3.0dB) 3.83 kHz Stopband SB 4.66 kHz Passband Ripple (Note 18) PR ±0.1 dB Stopband Attenuation (Note 19, Note 20) SA 68 dB Group Delay Distortion ΔGD 0 μs Group Delay (Ts=1/fs) GD 16 Ts Note 17. Frequency of each amplitude characteristic is in proportion to fs (sampling rate). The characteristic of the high pass filter is not included. Note 18. The passband is from DC to 3.15kHz when fs=8kHz. Note 19. The stopband is 4.66kHz to 507.34kHz when fs=8kHz. Note 20. When fs = 8kHz, the analog modulator samples the input signal at 512kHz. There is no attenuation of an input signal in band (n x 512kHz ±4.66kHz; n=0, 1, 2, 3…) of integer times of the sampling frequency by the digital filter. 2. fs=48kHz (Ta=-40ºC~85ºC, AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17) Parameter Symbol min typ max Units Passband (±0.1dB) (Note 21) PB 0 18.9 kHz (-1.0dB) 20.0 kHz (-3.0dB) 23.0 kHz Stopband SB 28 kHz Passband Ripple (Note 21) PR ±0.04 dB Stopband Attenuation (Note 22,Note 23) SA 68 dB Group Delay Distortion ΔGD 0 μs Group Delay (Ts=1/fs) GD 16 Ts Note 21. The passband is from DC to 18.9kHz when fs=48kHz. Note 22. The stopband is 28kHz to 3.044MHz when fs=48kHz. Note 23. When fs = 48kHz, the analog modulator samples the input signal at 512kHz. There is no attenuation of an input signal in band (n x 3.072MHz ±28kHz; n=0, 1, 2, 3…) of integer times of the sampling frequency by the digital filter. MS1033-E-02-PB 13 2010/01 [AK7734] SWITCHING CHARACTERISTICS ■ System Clock (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V) Parameter Symbol XTI CKM[3:0]=0000, 0001, 0010 a) with a Crystal Oscillator: fXTI CKM[3:0]=0000 fs=44.1kHz fs=48kHz fXTI CKM[3:0]=0001 fs=44.1kHz fs=48kHz b) with an External Clock Duty Cycle fXTI CKM[3:0]=0000, 0010 fs=44.1kHz fs=48kHz fXTI CKM[3:0]=0001 fs=44.1kHz fs-48kHz LRCLKI1 Frequency (Note 24) fs min typ max Units - 11.2896 12.288 16.9344 18.432 - MHz - MHz 50 11.2896 12.288 16.9344 18.432 60 % MHz - 40 11.0 16.5 7.35 12.4 18.6 48 MHz kHz BITCLKI1 Frequency 64 a) CKM[3:0]=0010 High Level Width tBCLKH 64 Low Level Width tBCLKL 64 Frequency 0.46 3.072 3.1 fBCLK b) CKM[3:0]=0011 (Note 25) 64 Duty Cycle 40 50 60 Frequency fBCLK 2.75 3.072 3.1 c) CKM[3:0]=0100 (Note 26) 32 Duty Cycle 40 50 60 Frequency fBCLK 230 256 258 d) CKM[3:0]=0101 (Note 25) 64 Duty Cycle 40 50 60 Frequency fBCLK 460 512 516 e) CKM[3:0]=1001 (Note 27) 48 Duty Cycle 40 50 60 Frequency fBCLK 2.06 2.304 2.32 f) CKM[3:0]=1010 (Note 27) 48 Duty Cycle 40 50 60 Frequency fBCLK 345 384 387 LRCLKI2 Frequency (Note 24) fs 7.35 48 BITCLKI2 Frequency a) CKM[3:0]=1011 (Note 25) 64 Duty Cycle 40 50 60 Frequency fBCLK 2.75 3.072 3.1 b) CKM[3:0]=1100 (Note 26) 32 Duty Cycle 40 50 60 Frequency fBCLK 230 256 258 c) CKM[3:0]=1101 (Note 25) 64 Duty Cycle 40 50 60 Frequency fBCLK 460 512 516 Note 24. LRCK frequency and sampling rate (fs) should be the same. Note 25. When BITCLK is a source of master clock, it should be 64 times fs correctly. (64fs fixed) Note 26. When BITCLK is a source of master clock, it should be 32 times fs correctly. (32fs fixed) Note 27. When BITCLK is a source of master clock, it should be 48 times fs correctly. (48fs fixed) MS1033-E-02-PB 14 fs ns ns MHz fs % MHz fs % kHz fs % kHz fs % MHz fs % kHz kHz fs % MHz fs % kHz fs % kHz 2010/01 [AK7734] ■ SRC Input Clock (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; VSS=0V) Parameter Symbol fs LRCLKI2 Frequency min 7.35 typ max 96 Units kHz BITCLKI2 Frequency Frequency High Level Width Low Level Width fBCLK tBCLKH tBCLKL 0.23 32 32 3.072 6.144 MHz ns ns (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V) Parameter Symbol INITRSTN (Note 28) tRST Note 28. It must be “L” when power-up the AK7734. min 600 typ max Units ns ■ Reset MS1033-E-02-PB 15 2010/01 [AK7734] ■ Audio Interface (SDIN1-4, SDOUT1-4) (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, CL=20pF) Parameter Symbol min typ max Units DSP Section Input SDIN1-4 (Note 29) Delay Time from BICLKI1 “↑” to LRCLKI1 (Note 30, Note 31) tBLRD 20 ns Delay Time from LRCLKI1 to BITCLKI1 “↑” (Note 30, Note 31) tLRBD 20 ns Serial Data Input Latch Setup Time tBSIDS 80 ns Serial Data Input Latch Hold Time tBSIDH 80 ns SRC Section Input SDIN4 (Note 32) Delay Time from BICLKI2 “↑” to LRCLKI2 (Note 33) tBLRD 20 ns Delay Time from LRCLKI2 to BITCLKI2 “↑” (Note 33) tLRBD 20 ns Serial Data Input Latch Setup Time tBSIDS 40 ns Serial Data Input Latch Hold Time tBSIDH 40 ns Output SDOUT1-4 (Note 29) BITCLKO Frequency fBCLK 64 fs BITCLKO Duty Factor 50 % Delay Time from BITCLKO “↓” to LRCLKO (Note 34) tBLRD -20 40 ns Delay Time from LRCLKI1 to Serial Data Output (Note 35) tLRD 80 ns Delay Time from BITCLKI1 to Serial Data Output (Note 31) tBSOD 80 ns Delay Time from LRCLKO to Serial Data Output (Note 35) tLRD 80 ns Delay Time from BITCLKO to Serial Data Output (Note 31) tBSOD 80 ns SDINn →SDOUTn (n=1-4) (Note 36) Delay Time from SDINn to SDOUTn Output tIOD 60 ns Note 29. In CKM modeB/C/D, LRCLKI2=LRCLKI1, BITCLKI2=BITCLKI1. Note 30. BITCLKI1 edge must not occur at the same time as LRCLKI1 edge. Note 31. In PCM mode 0/2, BITCLKI1 is polarity reversal. Note 32. Except CKM mode B/C/D. Note 33. BITCLKI2 edge must not occur at the same time as LRCLKI2 edge. When BIEDGE bit= “1”, this value is for BITCLKI2 “↓” since BITCLK2 is polarity reversal. Note 34. When SELBCK bit= “1”, this value is for BITCLKO “↑” since BITCLKO is polarity reversal. Note 35. Except I2S. Note 36. When SDIN1 → SDOUT1: Control Register Setting SELDO1[1:0] bit= “01”, OUT1E bit= “1” SDIN2 → SDOUT2: Control Register Setting SELDO2[1:0] bit = “01”, OUT2E bit= “1” SDIN3 → SDOUT3: Control Register Setting SELDO3[1:0] bit= “01”, OUT3E bit= “1” SDIN4 → SDOUT4: Control Register Setting SELDO4 bit= “1”, OUT4E bit= “1” MS1033-E-02-PB 16 2010/01 [AK7734] ■ Microprocessor Interface (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; VSS=0V; CL=20pF) Parameter Symbol Microprocessor Interface Signal RQN Fall Time tWRF RQN Rise Time tWRR SCLK Fall Time tSF SCLK Rise Time tSR SCLK Frequency fSCLK SCLK Low Level Width tSCLKL SCLK High Level Width tSCLKH Microprocessor → AK7734 RQN High Level Width tWRQH From RQN “↓” to SCLK “↓” tWSC From SCLK “↑” to RQN “↑” tSCW SI Latch Setup Time tSIS SI Latch Hold Time tSIH AK7734 → Microprocessor Deley Time from SCLK “↓”to SO Output tSOS Hold Time from SCLK “↑” to SO Output (Note 37) tSOH Note 37. Except for, when writing to 8th bit of command code. min typ max Units 30 30 30 30 2.1 200 200 ns ns ns ns MHz ns ns 500 500 800 200 200 ns ns ns ns ns 200 ns ns 200 ■ I2C BUS Interface (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V) Parameter I2C Timing SCL clock frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first Clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus Note 38. I2C-bus is a trademark of NXP B.V. MS1033-E-02-PB Symbol min typ max Unit 400 fSCL tBUF 1.3 kHz μs tHD:STA 0.6 μs tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO 1.3 0.6 0.6 0 0.1 μs μs μs μs μs μs μs μs tSP 0.3 0.3 0.6 0 Cb 17 0.9 50 ns 400 pF 2010/01 [AK7734] ■ Timing Diagram 1/fXTI 1/fXTI tXTI=1/fXTI XTI VIH VIL 1/fs ts=1/fs 1/fs LRCLKI1,2 VIH VIL 1/fBCLK 1/fBCLK tBCLK=1/fBCLK VIH BITCLKI1,2 VIL tBCLKH tBCLKL Figure 3. System Clock INITRSTN tRST VIL Figure 4. Reset Note 39. The INITRSTN pin must be “L” when power-up/power-down the AK7734. MS1033-E-02-PB - 18 - 2010/01 [AK7734] VIH VIL LRCLKI1,2 tBLRD tLRBD VIH VIL BITCLKI1,2 tBSIDS tBSIDH VIH VIL SDINn n=1,2,3,4 Figure 5. Audio Interface (DSP Section Slave Mode Input) VIH VIL LRCLKI2 tBLRD tLRBD VIH VIL BITCLKI2 tBSIDS tBSIDH VIH VIL SDIN4 Figure 6. Audio Interface (SRC Section Input) VIH VIL LRCLKI1,2 tLRD VIH VIL BITCLKI1,2 tLRD tBSOD SDOUTn n=1,2,3,4 tBSOD 50%DVDD Figure 7. Audio Interface (Slave Mode Output) MS1033-E-02-PB - 19 - 2010/01 [AK7734] LRCLKO 50%DVDD tMBL tMBL BITCLKO 50%DVDD tBSIDS tBSIDH VIH VIL SDINn n=1,2,3,4 Figure 8. Audio Interface (Master Mode Input) LRCLKO 50%DVDD tLRD BITCLKO 50%DVDD tBSOD tLRD tBSOD SDOUTn n=1,2,3,4 50%DVDD Figure 9. Audio Interface (Master Mode Output) VIH VIL RQN tWRF tWRR tSF tSR VIH VIL SCLK tSCLKL tSCLKH 1/fSCLK 1/fSCLK Figure 10. Microprocessor Interface MS1033-E-02-PB - 20 - 2010/01 [AK7734] RQN VIH VIL tWRQH VIH SI VIL tSIS tSIH VIH VIL SCLK tWSC tSCW tWSC tSCW Figure 11. Microprocessor Interface (Microprocessor → AK7734) VIH VIL SCLK VOH SO VOL tSOH tSOS Figure 12. Microprocessor Interface (AK7734 → Microprocessor) VIH SDA tBUF tLOW tR tHIGH VIL tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start Figure 13. I2C Bus Interface MS1033-E-02-PB - 21 - 2010/01 [AK7734] PACKAGE 48pin LQFP (Unit: mm) 1.60MAX 9.00 ± 0.20 0.10 ± 0.07 7.00 1.4TYP 25 24 48 13 7.00 37 9.00 ± 0.20 36 12 0.17 ± 0.05 0.50 0.19 ± 0.05 0.10 M 1.00 0˚ ~ 10˚ 0.10 S 0.50 ± 0.20 ■ Materials and Lead Specification Package: Lead frame: Lead-finish: MS1033-E-02-PB Epoxy Copper Soldering (Pb free) plate - 22 - 2010/01 [AK7734] MARKING AKM AK7734XQ XXXXXXX 1 1) 2) 3) 4) Pin #1 indication Date Code: XXXXXXX(7digits) Marking Code: AK7734XQ Asahi Kasei Logo REVISION HISTORY Date (YY/MM/DD) 09/03/24 09/11/16 10/01/06 MS1033-E-02-PB Revision 00 01 Reason First Edition Description Change Error Correction Page Contents 6, 7 Digital Ground 0V → Ground 0V Analog Ground 0V → Ground 0V DIGITAL FILTER CHARACTERISTICS Note 20: “n x 512kHz ±3.665kHz” → “n x 512kHz ±4.66kHz” Note 23: “n x 3.072MHz ±21.99kHz” → “n x 3.072MHz ±28kHz” 13 02 - 23 - 2010/01 [AK7734] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to r esult, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system conta ining it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of s afety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to func tion or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Thank you for your access to AKM product information. More detail product information is available, please contact our sales office or authorized distributors. MS1033-E-02-PB - 24 - 2010/01