Data Sheet

[AK7736A]
AK7736A
Audio/HF DSP with 2Ch SRC
GENERAL DESCRIPTION
The AK7736A is a highly integrated audio digital signal processor with integrated 2ch SRC. It includes
internal memories for digital audio processing, that allows surround effect process, time alignment and
parametric equalizing. More over, the AK7736A can process both data and filter coefficients as floating
point data so that high accuracy IIR/FIR filter performance can be achieved easily. The AK7736A can
operate a hands-free software by AKM as well as sound processing, by programs downloaded via the
microprocessor interface.
FEATURES
□ DSP Block
□
□
□
- Word length: 24-bit
- Machine Cycle: 8.1 ns (2560step/fs; fs = 48kHz)
- Step
fs=48kHz: Maximum 2560 step
fs=8kHz: Maximum 15360step
fs=16kHz: Maximum 7680step
- Multiplication: 20 x 24 → 44-bit (Double precision arithmetic available)
- Divider 20 / 20 → 20-bit (floating point normalization function)
- ALU: 48-bit arithmetic and logic operation (overflow margin 4-bit)
- Shift: Multiple DBUS ±15bit Shift with indirect shifting function
- Program RAM (PRAM): 6144word x 36-bit
- Coefficient RAM (CRAM): 4096word x 24-bit
- Data RAM (DRAM): 4096 x 24-bit (Variable Bank Size)
- Offset Register (OFREG): 32word x 15-bit
- Delay RAM (DLRAM): 16384word x 24-bit (Variable Bank Size)
- Register: 48-bit × 4 (ACC) [ALU]
24-bit × 12 (TMP) [DBUS connection]
24-bit × 6 level stack (PTMP) [DBUS connection]
Stereo 24-bit SRC
-SRC: FSI=8kHz~96kHz / FSO=8kHz~96kHz (FSO/FSI = 0.167~6.0)
Mono 24-bit Simple SRC
-FSCONV: FSI=44.1kHz~48kHz / FSO=8kHz~16kHz
Digital Interface Input/Output
- 8ch Serial Data Inputs
- 8ch Serial Data Outputs
- Sampling Frequency: 8~96kHZ
Microcontroller Interface: SPI, I2CBUS (400kHz Fast-Mode)
□
□ PLL
□ Power Supply:
-VDD 3.0~3.6V typ 3.3V (Internal Regulator)
-TVDD 1.7~3.6V (1~8pin)
Operating Temperature Range: -40°C ~ 85°C
□
□ Package: 48pin LQFP
MS1484-E-00-PB
2012/12
-1-
[AK7736A]
■ Block Diagram
Figure 1. Block Diagram
Note 1. Refer to the section “4. When Using N/W Converter” for N/W CONV block.
MS1484-E-00-PB
2012/12
-2-
[AK7736A]
Pointer
CP0, CP1
DP0, DP1
Data RAM
Coefficient RAM
4096w x 24-Bit
4096w x 24-Bit
OFREG
32w x 15-Bit
DLP0, DLP1
Delay RAM
16384w x 24-Bit(20.4f)
CBUS(24-Bit)
DBUS(24-Bit)
MPX24
Micon I/F
MPX20
X
Control
DEC
Y
Serial I/F
PRAM
6144w x 36-Bit
Multiply
24 x 20 → 44-Bit
PC
Stack: 5level(max)
TMP
24-Bit
44-Bit
12 x 24-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
2 x 16/20/24-Bit
SHIFT
48-Bit
2 x 16/20/24-Bit DIN3
44-Bit
A
DIN4
2 x 16/20/24-Bit
DIN2
2 x 16/20/24-Bit DIN1
B
ALU
2 x 16/20/24-Bit
DOUT4
48-Bit
2 x 16/20/24-Bit
DOUT3
2 x 16/20/24-Bit
DOUT2
2 x 16/20/24-Bit
DOUT1
Overflow Margin: 4-Bit
48-Bit
DR0 ∼ 3
48-Bit
Accelerator
Over Flow Data
Generator
Division 20÷20→20
Peak Detector
Figure 2. AK7736A Main DSP Block Diagram
MS1484-E-00-PB
2012/12
-3-
[AK7736A]
■ Ordering Guide
AK7736AVQ
AKD7736A
-40 ∼ +85°C
48pin LQFP (0.5mm pitch)
Evaluation Board for AK7736A
AVDRV
VSS
VDD
SCLK/SCL
SDA
SI/CAD0
CSN/CAD1
SDIN4
BITCLKI2/JX1
LRCLKI2/JX2
SO
STO
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
BITCLKI3
40
21
SDIN2A
LRCLKI3
41
48pin LQFP
20
PDN
SDIN2C
42
(TOP VIEW )
19
I2CSEL
JX0
43
18
VDD
EXPDN
44
17
VSS
VDD
45
16
RDY
TESTI2
46
15
SDOUT2A
VSS
47
14
SDOUT3
LFLT
48
13
SDOUT4
MS1484-E-00-PB
XTO
XTI
VSS
TVDD
LRCLK1
BITCLK1
TESTI3
SDIN2B
SDIN1
SDOUT1
SDOUT2B
TESTI1
Note) **** is an Internal pull-down pin.
12
LRCLKO
11
22
10
39
9
VDD
8
BITCLKO
7
23
6
38
5
VSS
4
CLKO
3
24
2
37
1
SDIN3
PIN
Input
Output
I/O
Power
***: Pin Name
2012/12
-4-
[AK7736A]
PIN/FUNCTION
No
Name
1 TESTI1
2
3
4
5
6
SDOUT2B
SDOUT1
SDIN1
SDIN2B
TESTI3
7
8
9
10
11
BITCLK1
LRCLK1
TVDD
VSS
XTI
12 XTO
13
14
15
16
17
18
19
SDOUT4
SDOUT3
SDOUT2A
RDY
VSS
VDD
I2CSEL
20 PDN
21
22
23
24
25
26
SDIN2A
LRCLKO
BITCLKO
CLKO
STO
SO
27 LRCLKI2
JX2
28 BITCLKI2
JX1
29 SDIN4
I/O
Function
Classification
I Test Pin (Internal pull-down)
Test
This pin must be connected to VSS.
O Serial Data2 B Output Pin
Serial Data
O Serial Data1 Output Pin
I Serial Data1 Input Pin
Serial Data
I Serial Data2 B Input Pin
I Test Pin (Internal pull-down)
Test
This pin must be connected to VSS
I/O Serial Bit Clock Pin 1 (Internal pull-down)
System Clock
I/O LR Channel Select Clock Pin 1 (Internal pull-down)
- Power Supply Pin for 1pin-8pin I/O 1.7~3.6V
Power Supply
- Ground Pin 0V
I Crystal Oscillator Input Pin
System Clock
Connect a crystal oscillator between this pin and the XTO pin, or input an
external clock to the XTI pin.
O Crystal Oscillator Output Pin
When a crystal oscillator is used, connect it between XTI and XTO. When
an external clock is used, leave this pin open.
O Serial Data4 Output Pin
Serial Data
O Serial Data3 Output Pin
O Serial Data2 A Output Pin
O RDY Pin
Status
- Ground Pin 0V
Power Supply
- Power Supply Pin 3.0~3.6V (typ. 3.3V)
I I2C BUS Select Pin
I 2C
I2CSEL= “L”: SPI Interface
I2CSEL= “H”: I2CBUS Interface
I2CSEL should be connected to “L” (VSS) or “H” (VDD).
I Power Down N Pin
Power Down
The AK7736A is powered-down by this pin.
This pin must be set to “L” when power-up the AK7736A
I Serial Data2 A Input Pin
Serial Data
O LR Channel Select Clock Pin
System Clock
O Serial Bit Clock Output Pin
O Clock Output Pin
Clock Output
O Status Output Pin
Status
O Control Data Output Pin for Microprocessor Interface
Microprocessor
Hi-Z output when the CSN pin = “H”
Interface
I LR Channel Select Clock Pin 2 (for FSCONV)
System Clock
I External Conditional Jump Pin 2
Conditional Input
I Serial Bit Clock Input Pin 2 (for FSCONV)
System Clock
External Conditional Jump Pin 1
Conditional Input
I Serial Data4 Input Pin
Serial Data
MS1484-E-00-PB
2012/12
-5-
[AK7736A]
30 CSN
I
Microprocessor Interface Request N Pin (I2CSEL pin= “L”)
Set this pin to “H” when not interfacing to a microprocessor or during
power-down.
CAD1
I I2CBUS Address Pin 1 (I2CSEL pin= “H”)
31 SI
I Serial Data Input Pin for Microprocessor Interface
Set this pin to “L” when not using.
CAD0
I I2C BUS Address Pin 0 (I2CSEL pin= “H”)
32 SDA
O Control Data Input /Output Pin (I2CSEL pin= “L”)
“Hi-Z” Output. This pin must be open when the I2CSEL pin = “L”.
I/O Control Data Input /Output Pin (I2CSEL pin= “H”)
SDA: I2C BUS Interface
33 SCLK
I Control Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”)
Set this pin to “H” when no clock is input.
SCL
I Control Data Clock Pin (I2CSEL pin= “H”)
SCL: I2C BUS Interface
34 VDD
- Power Supply Pin 3.0~3.6V (typ. 3.3V)
35 VSS
- Ground Pin 0V
36 AVDRV
AVDRV pin
Connect a 1μF capacitor between this pin and the VSS pin (No. 35). No
external circuits should be connected to this pin.
37 SDIN3
I Serial Data3 Input Pin
38 VSS
- Ground Pin 0V
39 VDD
- Power Supply Pin 3.0~3.6V (typ. 3.3V)
40 BITCLKI3 I Serial Bit Clock Input Pin 3 (for SRC)
41 LRCLKI3
I LR Channel Select Clock Pin 3 (for SRC)
42 SDIN2C
I Serial Data2 C Input Pin
43 JX0
I External Conditional Jump Pin 0
44 EXPDN
O Power Down Signal Output Pin
45 VDD
- Power Supply Pin 3.0~3.6V (typ. 3.3V)
TESTI2
I Test Pin (internal pull-down)
46
This pin must be connected to VSS.
47 VSS
- Ground Pin 0V
LFLT
O PLL RC Component Connect Pin
48
Connect C=12nF between this pin and No.47 (VSS) pin.
Note 2. All digital input pins must not be allowed to float
Note 3. The I2CSEL pin must be fixed to “L” (VSS) or “H” (TVDD).
Microprocessor
Interface
I 2C
Microprocessor
Interface
I 2C
Open
I 2C
Microprocessor
Interface
I 2C
Power Supply
Analog Output
Serial Data
Power Supply
System Clock
Serial Data
Conditional Input
Power Down
Power Supply
Test
Power Supply
Analog Output
■ Handling of Unused Pin
Unused I/O pins must be connected appropriately:
Pin Name
Setting
Output Pins
Leave Open
Input/Output Pins
SDA
Leave Open
LRCLK1
Connect to VSS
BITCLK1
Connect to VSS
Input Pins
Connect to VSS
MS1484-E-00-PB
2012/12
-6-
[AK7736A]
■ Output pin Status in Power-down Mode (PDN pin = “L”)
No
2
3
7
8
12
13
14
15
16
Pin Name
I/O
SDOUT2B O
SDOUT1
O
BITCLK1 I/O
LRCLK1
I/O
XTO
O
SDOUT4
O
SDOUT3
O
SDOUT2A O
RDY
O
Power-down Status
“L” Output
“L” Output
Input
Input
“H” Output
“L” Output
“L” Output
“L” Output
“L” Output
No
22
23
24
25
26
32
44
48
Pin Name
LRCLKO
BITCLKO
CLKO
STO
SO
SDA
EXPDN
LFLT
I/O
O
O
O
O
O
I/O
O
O
Power-down Status
“L” Output
“L” Output
“L” Output
“L” Output
“Hi-Z” Output
“Hi-Z” Output
“L” Output
“L” Output
■ Relationship between the I2CSEL Pin and the SDA Pin
SPI
Interface
I2CBUS support
I2CSEL
L
L
H
H
PDN
L
H
L
H
SDA
Hi-Z
Hi-Z
“Hi-Z” → pull-up
function
ABUSOLUTE MAXIMUM RATINGS
(VSS=0V: All voltages are with respect to ground)
Parameter
Symbol
min
max
Power Supply
TVDD
TVDD
-0.3
4.3
VDD
VDD
-0.3
4.3
Input Current (except for power supply pin )
IIN
–
±10
Digital Input Voltage (1pin-8pin)
VINDT
-0.3
(TVDD+0.3)
Digital Input Voltage (except 1pin-8pin)
VIND
-0.3
(VDD+0.3)
Operating Ambient Temperature
Ta
-40
85
Storage Temperature
Tstg
-65
150
Unit
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATION CONDITION
(VSS=0V: All voltages are with respect to ground.)
Parameter
Symbol
min
typ
max
Unit
Power Supply
TVDD
TVDD
1.7
1.8
3.6
V
VDD
VDD
3.0
3.3
3.6
V
Note 4. The TVDD pin is the power supply pin for pin number 1 ~ 8 pins.
Note 5. The power-up sequence with VDD and TVDD is not critical. The PDN pin should be held “L” when power is
supplied. The PDN pin is allowed to be “H” after all power supplies are applied and settled.
Note 6. Do not turn off the power supply of the AK7736A with the power supply of the surrounding device turned on.
VDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for VDD in the SDA and SCL
pins.)
MS1484-E-00-PB
2012/12
-7-
[AK7736A]
ELECTRIC CHARACTERISTICS
■ SRC Characteristics
1) SRC
(Ta= -40°C~85°C; TVDD=1.8V, VDD=3.3V; VSS=0V; data = 24bit; measurement bandwidth = 20Hz~FSO/2; unless
otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
8
96
kHz
Output Sample Rate
FSO
8
96
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
-112
dB
FSO/FSI=44.1kHz/96kHz
-111
dB
FSO/FSI=48kHz/44.1kHz
-112
dB
FSO/FSI=48kHz/96kHz
-113
dB
FSO/FSI=48kHz/8kHz
-111
-103
dB
FSO/FSI=16kHz/48kHz
-113
dB
FSO/FSI=16kHz/44.1kHz
-100
dB
FSO/FSI=8kHz/48kHz
-113
dB
FSO/FSI=8kHz/44.1kHz
-95
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
113
dB
FSO/FSI=44.1kHz/96kHz
113
dB
FSO/FSI=48kHz/44.1kHz
113
dB
FSO/FSI=48kHz/96kHz
113
dB
FSO/FSI=48kHz/8kHz
108
113
dB
FSO/FSI=16kHz/48kHz
113
dB
FSO/FSI=16kHz/44.1kHz
113
dB
FSO/FSI=8kHz/48kHz
111
dB
FSO/FSI=8kHz/44.1kHz
114
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted)
FSO/FSI=44.1kHz/48kHz
115
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
2) FSCONV
(Ta= -40°C ~85°C; TVDD=1.8V, VDD=3.3V; VSS=0V; data = 24bit; measurement bandwidth = 20Hz~FSO/2; unless
otherwise specified.)
Parameter
Symbol
min
typ
max
Unit
Resolution
24
Bits
Input Sample Rate
FSI
44.1
48
kHz
Output Sample Rate
FSO
8
16
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=16kHz/48kHz
-114
dB
FSO/FSI=16kHz/44.1kHz
-95
dB
FSO/FSI=8kHz/48kHz
-115
dB
FSO/FSI=8kHz/44.1kHz
-97
dB
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=16kHz/48kHz
114
dB
FSO/FSI=16kHz/44.1kHz
114
dB
FSO/FSI=8kHz/48kHz
114
dB
FSO/FSI=8kHz/44.1kHz
114
dB
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted)
FSO/FSI=8kHz/48kHz
117
dB
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
0.363
Note 7. Input signal frequency bandwidth of FSCONV must be attenuated more than 4kHz when the output sampling rate
is 8kHz, or must be attenuated more than 8kHz when the output sampling rate is 16kHz.
MS1484-E-00-PB
2012/12
-8-
[AK7736A]
■ DC Characteristics
(Ta= -40°C ~85°C, VSS=0V, VDD=3.0~3.6V, TVDD=1.7~3.6V)
Parameter
Symbol
High Level Input Voltage 1 (Note 8)
VIH1
Low Level Input Voltage 1 (Note 8)
VIL1
High Level Input Voltage 2 (Note 9)
VIH2
Low Level Input Voltage 2 (Note 9)
VIL2
SCL, SDA High Level Input Voltage
VIH3
SCL, SDA Low Level Input Voltage
VIL3
High Level Output Voltage 1 Iout= -100μA (Note 8)
VOH1
1.7 ≤ TVDD < 3.0
3.0 ≤ TVDD ≤ 3.6
VOH1
Low Level Output Voltage 1 Iout=100μA (Note 8)
VOL1
1.7 ≤ TVDD < 3.0
3.0 ≤ TVDD ≤ 3.6
VOL1
High Level Output Voltage 2 Iout= -100μA (Note 9)
VOH2
Low Level Output Voltage 2 Iout=100μA (Note 9)
VOL2
min
80%TVDD
typ
max
Unit
V
V
V
V
V
V
20%TVDD
80%VDD
20%VDD
70%VDD
30%VDD
TVDD-0.3
TVDD-0.5
V
0.3
0.5
V
VDD-0.5
V
0.5
V
SDA Low Level Output Voltage Iout=3mA
VOL3
0.4
Input Leak Current
(Note 10)
Iin
±10
Input Leak Current with pulled-down (Note 11)
Iid
81
Note 8. TESTI1, SDOUT2B, SDOUT1, SDIN1, SDIN2B, TESTI3, BITCLK1 and LRCLK1 pins. 1pin-8pin.
Note 9. Except 1pin-8pin, SDA and SCL pins
Note 10. Pull-down pins, and the XTI pin is not included.
Note 11. LRCLK1, BITCLK1, TESTI1, TESTI2 and TESTI3 pins are internal pulled-down pin. (typ. 40.7kΩ)
V
μA
μA
■ Current Consumption
(Ta=25°C, VSS=0V, VDD=3.0~3.6V(typ=3.3V, max=3.6V), TVDD=1.7~3.6V(typ=1.8V, max=3.6V))
Parameter
min
typ
max
Unit
Normal Operation Mode (Note 12) TVDD
0.3
mA
0.5
VDD
31
mA
50
Power-down Mode
TVDD
0.01
μA
(PDN = L)
VDD
1
μA
Note 12. The current consumption changes depending on the system frequency and contents of the DSP program.
MS1484-E-00-PB
2012/12
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[AK7736A]
DIGITAL FILTER CARACTERISTICS
■ SRC Block
(Ta= -40°C~85°C, VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS =0V)
Parameter
Symbol
min
typ
max
Unit
Passband -0.01dB
0.980≤FSO/FSI≤6.000
PB
0
0.4583FSI
kHz
0.900≤FSO/FSI<0.990
PB
0
0.4167FSI
kHz
0.533≤FSO/FSI<0.909
PB
0
0.2182FSI
kHz
0.490≤FSO/FSI<0.539
PB
0
0.2177FSI
kHz
0.450≤FSO/FSI<0.495
PB
0
0.1948FSI
kHz
0.225≤FSO/FSI<0.455
PB
0
0.1312FSI
kHz
Passband -0.50dB
0.167≤FSO/FSI<0.227
PB
0
0.0658FSI
kHz
Stopband
0.980≤FSO/FSI≤6.000
SB
0.5417FSI
kHz
0.900≤FSO/FSI<0.990
SB
0.5021FSI
kHz
0.533≤FSO/FSI<0.909
SB
0.2974FSI
kHz
0.490≤FSO/FSI<0.539
SB
0.2812FSI
kHz
0.450≤FSO/FSI<0.495
SB
0.2604FSI
kHz
0.225≤FSO/FSI<0.455
SB
0.1802FSI
kHz
0.167≤FSO/FSI<0.227
SB
0.0970FSI
kHz
Passband Ripple
0.225≤FSO/FSI≤6.000
PR
±0.01
dB
0.167≤FSO/FSI<0.227
PR
±0.50
dB
Stopband Attenuation
0.450≤FSO/FSI≤6.000
SA
95.2
dB
0.167≤FSO/FSI<0.455
SA
90.0
dB
Group Delay (Ts=1/fs) (Note 13)
GD
63
Ts
Note 13. This delay is the a period from the rising edge of LRCLKI3, just after the data is input, to the rising edge of
LRCLKO, just before the data is output, when there is no phase difference between Input and Output signals.
■ FSCONV Block
(Ta= -40°C~85°C, VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS =0V)
Parameter
Symbol
min
typ
max
Unit
Passband -0.01dB
0.167≤FSO/FSI≤0.363
PB
0
0.1814FSI
kHz
Stopband
0.167≤FSO/FSI≤0.363
SB
0.8185FSI
kHz
Passband Ripple
0.167≤FSO/FSI≤0.363
PR
±0.005
dB
Stopband Attenuation
0.167≤FSO/FSI≤0.363
SA
94.0
dB
Group Delay (Ts=1/fsi) (Note 14)
GD
9
Ts
Note 7. Input signal frequency bandwidth of FSCONV must be attenuated more than 4kHz when the output sampling rate
is 8kHz, or must be attenuated more than 8kHz when the output sampling rate is 16kHz.
Note 14. This delay is the a period from the rising edge of LRCLKI2, just after the data is input, to the rising edge of
LRCLKO, just before the data is output, when there is no phase difference between Input and Output signals.
MS1484-E-00-PB
2012/12
- 10 -
[AK7736A]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta= -40°C~85°C; VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS =0V; CL=20pF)
Parameter
Symbol
a) with a Crystal Oscillator
CKM[2:0]bits=0h
fXTI
CKM[2:0]bits=1h
fXTI
b) with an External Clock
Duty Cycle
CKM[2:0]bits=0h,2h
fXTI
40
11.0
CKM[2:0]bits=1h
fXTI
16.5
fs
8
LRCLK1 Frequency
(Note 15)
min
typ
11.2896
12.288
16.9344
18.432
50
11.2896
12.288
16.9344
18.432
max
MHz
MHz
60
12.4
%
MHz
18.6
MHz
96
kHz
BITCLK1 Frequency
(Note 16)
32,48,64
fs
High Level Width
tBCLKH
64
ns
Low Level Width
tBCLKL
64
ns
Frequency
fBCLK
0.23
3.072
6.2
MHz
LRCLKI2 Frequency (FSCONV)
(Note 17) fs
44.1
48
kHz
BITCLKI2 Frequency (FSCONV)
(Note 18)
32,48,64,128
fs
High Level Width
tBCLKH
64
ns
Low Level Width
tBCLKL
64
ns
Frequency
fBCLK
1.25
3.072
6.2
MHz
LRCLKI3 Frequency (SRC)
fs
8
96
kHz
BITCLKI3 Frequency (SRC)
32,48,64,128
fs
High Level Width
tBCLKH
32
ns
Low Level Width
tBCLKL
32
ns
Frequency
fBCLK
0.23
3.072
12.4
MHz
Note 15. LRCLK1 frequency and sampling rate (fs) should be the same.
Note 16. When BITCLK1 is used as a master clock reference clock, it should be synchronized with LRCLK1, and its
frequency should be fixed.
Note 17. fs=8~48kHz in CKM mode 4.
Note 18. 128fs is inhibited in CKM mode 4.
■ Power Down
(Ta= -40°C~85°C; VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS =0V)
Parameter
Symbol
PDN
(Note 19)
tRST
Note 19. The PDN pin must be “L” when power up the AK7736A.
MS1484-E-00-PB
min
600
typ
max
Unit
ns
2012/12
- 11 -
[AK7736A]
■ Serial Data Interface
(Ta= -40°C ~85°C; VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS =0V; CL=20pF)
Parameter
Symbol
min
DSP Section Input SDIN1, 2A, 2B, 2C, 3, 4
(Note 20)
Delay Time from BITCLK1 “↑” to LRCLK1
(Note 21) tBLRD
20
Delay Time from LRCLK1 to BITCLK1 “↑”
(Note 21) tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
80
Serial Data Input Latch Hold Time
tBSIDH
80
SRC Section Input SDIN3
Delay Time from BITCLKI3 “↑” to LRCLKI3
(Note 22)
tBLRD
20
Delay Time from LRCLKI3 to BITCLKI3 “↑”
(Note 22)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
FSCONV Section Input SDIN4
(Note 23)
Delay Time from BITCLKI2 “↑” to LRCLKI2
(Note 24)
tBLRD
20
Delay Time from LRCLKI2 to BITCLKI2 “↑”
(Note 24)
tLRBD
20
Serial Data Input Latch Setup Time
tBSIDS
40
Serial Data Input Latch Hold Time
tBSIDH
40
Output SDOUT1, SDOUT2, SDOUT3, SDOUT4
BITCLKO Frequency
(Note 25)
fBCLK
BITCLKO Duty Factor
(Note 25)
Delay Time from BITCLKO “↓” to LRCLKO
(Note 26) tMBL
-20
Delay Time from LRCLK1 to Serial Data Output
(Note 27) tLRD
Delay Time from BITCLK1“↓” to Serial Data Output (Note 28) tBSOD
Delay Time from LRCLKO to Serial Data Output
(Note 27) tLRD
Delay Time from BITCLKO “↓” to Serial Data Output (Note 29) tBSOD
SDINn → SDOUTn (n=1, 2A, 2B, 2C, 3, 4)
Delay Time from SDINn to SDOUTn Output
tIOD
Note 20. In CKM mode 4, these are the time from LRCKLI2 or BITCLKI2.
Note 21. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↓”.
Note 22. When BITCLKI3 polarity is inverted, delay time is from BITCLKI3 “↓”.
Note 23. Except CKM mode 4.
Note 24. When BITCLKI2 polarity is inverted, delay time is from BITCLKI2 “↓”.
Note 25. Except slave mode.
Note 26. When BCKOP bit = “1”, delay time is from BITCLKO “↑”.
Note 27. Except I2S compatible mode.
Note 28. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↑”.
Note 29. When BITCLKO polarity is inverted, delay time is from BITCLKO “↑”.
MS1484-E-00-PB
typ
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
64
50
40
80
80
80
80
60
fs
%
ns
ns
ns
ns
2012/12
- 12 -
[AK7736A]
■ Microprocessor Interface
(Ta= -40°C ~85°C; VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
Microprocessor Interface Signal
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
SCLK High Level Width
tSCLKH
Microprocessor → AK7736A
CSN High Level Width
tWRQH
From CSN “↑” to PDN “↑”
tRST
From PDN “↑” to CSN “↓”
tIRRQ
From CSN “↓” to SCLK “↓”
tWSC
From SCLK “↑” to CSN “↑”
tSCW
SI Latch Setup Time
tSIS
SI Latch Hold Time
tSIH
AK7736A → Microprocessor
Delay Time from SCLK “↓” to SO Output
tSOS
Hold Time from SCLK “↑” to SO Output (Note 30) tSOH
Note 30. Except when input the eighth bit of the command code.
min
typ
max
Unit
2.1
200
200
MHz
ns
ns
500
600
1
500
800
200
200
ns
ns
ms
ns
ns
ns
ns
200
200
ns
ns
■ I2C-BUS Interface
(Ta= -40°C ~85°C; VDD=3.0~3.6V, TVDD=1.7~3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
I2C Timing
SCL clock frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
SDA Hold Time from SCL Falling
tHD:DAT
SDA Setup Time from SCL Rising
tSU:DAT
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
Pulse Width of Spike Noise Suppressed By Input Filter
tSP
Capacitive load on bus
Cb
MS1484-E-00-PB
min
1.3
0.6
1.3
0.6
0.6
0
0.1
typ
max
Unit
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
0.9
0.3
0.3
0.6
0
50
400
2012/12
- 13 -
[AK7736A]
■ Timing Diagram
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH2
VIL2
1/fs
ts=1/fs
1/fs
LRCLK1(I)
LRCLKI2
VIH1,2
LRCLKI3
VIL1,2
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
BITCLK1(I)
VIH1,2
BITCLKI2
VIL1,2
BITCLKI3
tBCLKH
tBCLKL
Figure 3. System Clock
PDN
tRST
VIL2
Figure 4. Power-down
MS1484-E-00-PB
2012/12
- 14 -
[AK7736A]
VIH1
VIL1
LRCLK1(I)
tBLRD
tLRBD
VIH1
VIL1
BITCLK1(I)
tBSIDS
tBSIDH
VIH1,2
VIL1,2
SDINn
n=1,2A,2B,2C,3,4
VIH2
VIL2
LRCLKI3
tBLRD
tLRBD
VIH2
VIL2
BITCLKI3
tBSIDS
tBSIDH
SDIN3
VIH2
VIL2
LRCLKI2
VIH2
VIL2
tBLRD
tLRBD
VIH2
VIL2
BITCLKI2
tBSIDS
tBSIDH
VIH2
VIL2
SDIN4
Figure 5. Slave Mode Input Interface
50%VDD
LRCLKO
tMBL
tMBL
50%VDD
BITCLKO
tBSIDS
tBSIDH
VIH1, 2
VIL1, 2
SDINn
n=1, 2A, 2B, 2C, 3, 4
Figure 6. Master Mode Input Interface
MS1484-E-00-PB
2012/12
- 15 -
[AK7736A]
VIH1
VIL1
LRCLK1(I)
tLRD
VIH1
VIL1
BITCLK1(I)
tLRD
tBSOD
tBSOD
SDOUTn
n=1,2A,2B,3,4
50%VDD, TVDD
Figure 7. Slave Mode Output Interface
LRCLKO
LRCLK1(O)
50%VDD
tLRD
BITCLKO
BITCLK1(O)
50%VDD
tLRD
tBSOD
SDOUTn
n=1,2A,2B,3,4
tBSOD
50%VDD,TVDD
Figure 8. Master Mode Output Interface
MS1484-E-00-PB
2012/12
- 16 -
[AK7736A]
VIH3
VIL3
CSN
tWRF
tWRR
tSF
tSR
VIH3
VIL3
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
VIH3
PDN
VIL3
VIH3
CSN
VIL3
tRST
tIRRQ
Figure 9. Microprocessor Interface Signal
VIH3
VIL3
tWRQH
CSN
VIH3
SI
VIL3
tSIS
tSIH
VIH3
VIL3
SCLK
tW SC
tSCW
tWSC
tSCW
Figure 10. Microprocessor → AK7736A
MS1484-E-00-PB
2012/12
- 17 -
[AK7736A]
SCLK
VIH3
VIL3
SO
50%VDD
tSOH
tSOS
Figure 11. AK7736A → Microprocessor
VIH3
SDA
tBUF
tLOW tR
tHIGH
VIL3,VOL3
tF
tSP
VIH3
SCL
VIL3
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 12. I2C-BUS Interface
MS1484-E-00-PB
2012/12
- 18 -
[AK7736A]
PACKAGE
48pin LQFP (Unit mm)
■ Materials and Lead Specification
Package: Epoxy
Lead frame: Copper
Lead-finish: Soldering (Pb free) plate
MS1484-E-00-PB
2012/12
- 19 -
[AK7736A]
MARKING
AKM
AK7736AVQ
XXXXXXX
48
1
1) pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK7736AVQ
4) Asahi Kasei Logo
REVISION HISTORY
Date (Y/M/D)
12/12/17
Revision
00
Reason
First Edition
Page
Contents
MS1484-E-00-PB
2012/12
- 20 -
CONFIDENTIAL
[AK7719]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
Thank you for your access to AKM product information.
More detail product information is available, please contact our
sales office or authorized distributors.
MS1484-E-00-PB
2012/12
- 21 -