AMCC 440GP

Part Number 440GP
Revision 1.07 – October 4, 2007
440GP
Data Sheet
Power PC 440GP Embedded Processor
Features
• PowerPC® 440 processor core operating up to
500MHz with 32KB I- and D-caches
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are MII
and RMII.
• On-chip 8 KB SRAM
• Selectable processor:bus clock ratios of 3:1, 4:1,
5:1, 5:2, 7:2
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT)
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) 32/64-bit interface operating up to
133MHz
• Two serial ports (16750 compatible UART)
• External Peripheral Bus for up to eight devices
with external mastering
• General Purpose I/O (GPIO) interface available
• DMA support for external peripherals, internal
UART and memory
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI V2.2
• Two IIC interfaces
• JTAG interface for board level testing
• Internal Processor Local Bus (PLB) runs at DDR
SDRAM interface frequency
• Processor can boot from PCI memory
• Available in ceramic (RoHs and non-RoHS
compliant versions) and plastic packages.
Description
Technology: CMOS SA-27E, 0.18μm (0.11 Leff)
Designed specifically to address high-end embedded
applications, the PowerPC 440GP (PPC440GP)
provides a high-performance, low power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation.
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA) in standard
or RoHS compliant versions
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,8KB SRAM,
PCI-X bus interface, Ethernet interfaces, control for
external ROM and peripherals, DMA with scattergather support, serial ports, IIC interface, and general
purpose I/O.
Supply voltages required: 3.3V, 2.5V, 1.8V
AMCC
Power (estimated): Less than:
4.0W in normal mode
1.0 W in sleep mode
1
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Heat Sink Mounting Information (Ceramic Package Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Figures
PPC440GP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
25mm, 552-Ball Ceramic (CBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
25mm, 552-Ball Plastic (FC-PBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Heat Sink Attached With Spring Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Heat Sink Attached With Adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DDR SDRAM MemClkOut0 and Read Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DDR SDRAM Read Cycle Timing—Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DDR SDRAM Read Cycle Timing—Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DDR SDRAM Read Cycle Timing—Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Tables
Order Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O Specifications—400, 466, and 500MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O Timing—DDR SDRAM TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O Timing—DDR SDRAM TSK, TSA, and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O Timing—DDR SDRAM TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O Timing—DDR SDRAM TSIN and TDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
AMCC
3
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local AMCC sales office.
Order Part Numbers
Product
Name
Order Part Number
(See Notes and Key drawing)
Processor
Frequency
Package
Rev
Level
PVR Value
JTAG ID
PPC440GP
PPC440GP-3CC333C
333MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC400C
400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC400CZ
400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC400E
400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC400EZ
400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC466C
466MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC466CZ
466MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC500C
500MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3CC500CZ
500MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3FC400C
400MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC333C
333MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC400C
400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC400CZ
400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC400E
400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC466C
466MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC466CZ
466MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC500C
500MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP
PPC440GP-3RC500CZ
500MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
Notes:
1.
2.
3.
4.
Package code: C = leaded ceramic, F = plastic, R = reduced-lead ceramic (RoHS compliant),.
Case Temperature Range code: C = -40 °C to +85 °C, E = -40 °C to +105 °C for C package and -40 °C to +100 °C for F package.
Z at the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray.
Revision code: C = rev 2.1.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. Refer to the PPC440GP User’s Manual for details on accessing these
registers.
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Order Part Number Key
PPC440GP-3CC500Ex
Shipping Package
Part Number
Grade 3 Reliability
Package
AMCC
Case Temperature Range
Processor Speed
Revision Level
5
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
PPC440GP Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
PPC440
DCR Bus
Processor Core
45 internal
13 external
GP
Timers
GPIO
UART
x2
IIC
x2
Trace
JTAG
32KB
D-Cache
32KB
I-Cache
On-chip Peripheral Bus (OPB)
Arb
SRAM
8KB
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
MAL
DDR SDRAM
Controller
133MHz max
13-bit addr
32/64-bit data
PCI-X
Bridge
Ethernet
x2
External
External
Bus Master
Bus
Controller
Controller
1 MII
or
2 RMII
66MHz max
32-bit addr
32-bit data
133MHz max
The PPC440GP is designed using the IBM® Microelectronics Blue Logic™ methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus™ Architecture.
Note: IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 133.33MHz
• 32-bit OPB interfaces up to 66.66MHz, 266MB/s
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GP processor through the use of mtdcr and mfdcr instructions.
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
System Memory Address Map
(Sheet 1 of 2)
Function
Sub Function
Start Address
End Address
Size
DDR SDRAM
0 0000 0000
0 7FFF FFFF
2GB
SRAM
0 8000 0000
0 8000 1FFF
8KB
Reserve
0 8000 2000
0 FFFF FFFF
EBC
1 0000 0000
1 3FFF FFFF
Reserved
1 4000 0000
1 4000 01FF
UART0
1 4000 0200
1 4000 0207
Reserved
1 4000 0208
1 4000 02FF
UART1
1 4000 0300
1 4000 0307
Reserved
1 4000 0308
1 4000 03FF
IIC0
1 4000 0400
1 4000 041F
Reserved
1 4000 0420
1 4000 04FF
IIC1
1 4000 0500
1 4000 051F
Reserved
1 4000 0520
1 4000 05FF
OPB Arbiter
1 4000 0600
1 4000 063F
Reserved
1 4000 0640
1 4000 06FF
GPIO Controller
1 4000 0700
1 4000 077F
128B
Ethernet PHY ZMII
1 4000 0780
1 4000 078F
16B
Ethernet PHY GMII
1 4000 0790
1 4000 079F
16B
Reserved
1 4000 0790
1 4000 07FF
Ethernet 0 Controller
1 4000 0800
1 4000 08FF
256B
Ethernet 1 Controller
1 4000 0900
1 4000 09FF
256B
General Purpose Timer
1 4000 0A00
1 4000 0AFF
256B
Reserved
1 4000 0B00
1 EFFF FFFF
Expansion ROM2
1 F000 0000
1 FFDF FFFF
254MB
Boot ROM2, 3
1 FFE0 0000
1 FFFF FFFF
2MB
Local Memory1
1GB
8B
8B
32B
32B
64B
Internal Peripherals
AMCC
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440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
System Memory Address Map
Function
PCI-X
(Sheet 2 of 2)
Sub Function
Start Address
End Address
Size
Reserved
2 0000 0000
2 07FF FFFF
PCI-X I/O
2 0800 0000
2 0BFF FFFF
Reserved
2 0C00 0000
2 0EBF FFFF
PCI-X External Configuration Registers
2 0EC0 0000
2 0EC0 0007
Reserved
2 0EC0 0008
2 0EC7 FFFF
PCI-X Bridge Core Configuration Registers
2 0EC8 0000
2 0EC8 00FF
Reserved
2 0EC8 0100
2 0EC8 00FF
PCI-X Special Cycle
2 0ED0 0000
2 0EDF FFFF
1MB
PCI-X Memory
2 0EE0 0000
F FFFF FFFF
55.76 GB
64MB
8B
256B
Notes:
1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.
2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating
volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.
3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 2 FFFE 0000 (128 KB).
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DCR Address Map 4KB of Device Configuration Registers
Function
Start Address
End Address
Size
000
3FF
1KW (4KB)1
Reserved
000
00F
16W
Memory Controller
010
011
2W
External Bus Controller
012
013
2W
External Bus Master I/F
014
015
2W
PLB Performance Monitor
016
01F
10W
SRAM
020
02F
16W
Reserved
030
07F
80W
PLB
080
08F
16W
PLB to OPB Bridge Out
090
09F
16W
Reserved
0A0
0A7
8W
OPB to PLB Bridge In
0A8
0AF
8W
Power Management
0B0
0B7
8W
Reserved
0B8
0BF
8W
Interrupt Controller 0
0C0
0CF
16W
Interrupt Controller 1
0D0
0DF
16W
Clock, Control, and Reset
0E0
0EF
16W
Reserved
0F0
0FF
16W
DMA Controller
100
13F
64W
Reserved
140
17F
64W
Ethernet MAL
180
1FF
128W
Reserved
200
3FF
512W
Total DCR Address Space1
By function:
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register. One kiloword (1024W) equals 4KB (4096 bytes).
AMCC
9
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, routers, switches,
printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded architecture
and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
• Up to 500MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• 3 execution pipelines
• Dynamic branch prediction
• Memory management unit
- 64-entry, full associative, unified TLB
- Separate instruction and data micro-TLBs
- Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
• Debug facilities
- Multiple instruction and data range breakpoints
- Data value compare
- Single step, branch, and trap events
- Non-invasive real-time trace interface
• 24 DSP instructions
- Single-cycle multiply and multiply-accumulate
- 32 x 32 integer multiply
- 16 x 16 -> 32-bit MAC
Internal Buses
The PowerPC 440GP features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip
Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores
such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to
the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for
passing status and control information between the processor core and the other on-chip cores.
Features include:
• PLB
- 128-bit implementation of the PLB architecture
- Separate and simultaneous read and write data paths
- 36-bit address
- Simultaneous control, address, and data phases
- Four levels of pipelining
- Byte enable capability supporting unaligned transfers
- 32- and 64-byte burst transfers
10
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
- 133MHz, maximum 4.2GB/s (simultaneous read and write)
- Processor:bus clock ratios of 3:1, 4:1, 5:1, 5:2, and 7:2
• OPB
- Dynamic bus sizing 32-, 16-, and 8-bit data path
- Separate and simultaneous read and write data paths
- 36-bit address
- 66.66MHz, maximum 266MB/s
• DCR
- 32-bit data path
- 10 bit address
On-Chip SRAM
Features include:
• One physical bank of 8KB
• Memory cycles supported:
- Single beat read and write, 1 to 16 bytes
- 32- and 64-byte burst transfers
- Guarded memory accesses
• Sustainable 2.1GB/s peak bandwidth at 133MHz
PCI-X Interface
The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory.
This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit PCI-X buses. PCI
32/64-bit conventional mode, compatible with PCI Version 2.2, is also supported.
Reference Specifications:
• PowerPC CoreConnect Bus (PLB) version PLB4
• PCI Specification Version 2.2
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• PCI-X 1.0a
- Split transactions
- Frequency to 133MHz
- 32- and 64-bit bus
• PCI 2.2 backward compatibility
- Frequency to 66MHz
- 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
• Support for Message Signaled Interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
AMCC
11
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
• Ability to boot from PCI-X bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
- Single beat I/O reads and writes
- Single beat and burst memory reads and writes
- Single beat configuration reads and writes (type 0 and type 1)
- Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs and other
discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global memory timings,
address and bank sizes, and memory addressing modes are programmable.
Features include:
• Registered and non-registered industry standard DIMMs and other discrete devices
• 32- or 64-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 2.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• PC200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)
External Peripheral Bus Controller (EBC)
Features include:
• Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation (266MB/s)
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus
• 32-bit address, 4GB address space
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
12
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
• External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
Ethernet Controller Interface
Ethernet support provided by the PPC440GP interfaces to the physical layer, but the PHY is not included on the
chip.
Features include:
• One or two interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s
- One full Media Independent Interface (MII) with 4-bit parallel data transfer
- Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer
DMA Controller
Features include:
• Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 64-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
Serial Port
Features include:
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with 16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
AMCC
13
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
IIC Bus Interface
Features include:
• Two IIC interfaces provided
•
•
•
•
•
•
•
•
Support for Philips® Semiconductors I2C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed VDD IIC interface
•
•
•
•
•
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocols
Programmable error recovery
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor
core.
• 32-bit Time Base Counter driven by the OPB bus clock
• Five 32-bit compare timers
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
accesses.
• 31 of the 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose.
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
14
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Universal Interrupt Controller (UIC)
TwoUniversal Interrupt Controllers (UIC) are available. They provide control, status, and communications
necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
• 13 external interrupts
• 45 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
JTAG
Features include:
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)
AMCC
15
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
25mm, 552-Ball Ceramic (CBGA) Package
Top View
Chip
AAAAAAAA
Lot Number
PPC440GP–3xxfffx
A1 Corner
Part Number
Capacitor
Notes: 1. All dimensions are in mm.
2. RoHS compliant reduced-lead package available.
3. Reduced-lead package dimensions are in parentheses (dimension).
Bottom View
25.0 ± 0.2
23.0
AD
AC
AB
AA
Y
W
V
U
T
R
25.0 ± 0.2 P N
M
L
K
J
H
G
F
E
D
C
B
A
1.00 TYP
8.04
1 3 5 7 9 11 13 15 17 19 21 23
2 4 6 8 10 12 14 16 18 20 22 24
0.8 ± 0.04 SOLDERBALL x 552
(0.7 ± 0.1)
16
1.95 MAX
(1.98)
1.65 MIN
(1.62)
0.8 TYP
(0.5 ± 0.1)
3.80 MAX
(3.488)
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
25mm, 552-Ball Plastic (FC-PBGA) Package
Top View
A1 Corner
24
1
A
®
PPC440GP
Part Number
3xCfffx
Lot Number
AAAAAAAA
AD
Note: All dimensions are in mm.
Bottom View
25.0
23.0
25.0
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1.00 TYP
1 ± 0.3
7.75
1 3 5 7 9 11 13 15 17 19 21 23
2 4 6 8 10 12 14 16 18 20 22 24
0.66 ± 0.1 SOLDERBALL x 552
AMCC
1.214 REF
0.5 ± 0.1
23.0
0.508 REF
3.191 ± 0.17
17
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the
signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the
alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each
signal name on the ball. The page number listed gives the page in “Signal Functional Description” on page 48
where the signals in the indicated interface group begin. In cases where signals in the same interface group (for
example, Ethernet) have different names to distinguish variations in the mode of operation, the names are
separated by a comma with the primary name appearing first. These signals are listed only once, and appear
alphabetically by the primary name.
Signals Listed Alphabetically
Signal Name
18
(Sheet 1 of 22)
Ball
AGND
J01
AGND
J24
AGND
AA11
AMVDD
Interface Group
Page
Power—Analog ground
54
AB11
Power—MemClkOut PLL analog voltage
54
APVDD
G01
Power—PCI-X PLL analog voltage
54
ASVDD
G24
Power—SysClk PLL analog voltage
54
BA0
AA16
DDR SDRAM
49
BA1
AD09
BankSel0
AB15
BankSel1
W14
DDR SDRAM
49
BankSel2
AD11
BankSel3
AD05
PCI-X
48
[BE0]PCIXC0
F14
[BE1]PCIXC1
E16
[BE2]PCIXC2
C19
[BE3]PCIXC3
F20
[BE4]PCIXC4
C08
[BE5]PCIXC5
C03
[BE6]PCIXC6
G09
[BE7]PCIXC7
F09
BusReq
AA24
External Master Peripheral
51
CAS
AB05
DDR SDRAM
49
ClkEn0
AD17
ClkEn1
AB10
DDR SDRAM
49
ClkEn2
Y09
ClkEn3
W09
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 2 of 22)
Ball
DM0
T16
DM1
AA18
DM2
AB14
DM3
P13
DM4
AA09
DM5
AA07
DM6
Y03
DM7
V03
DM8
AC05
DMAAck0
N05
DMAAck1
P07
DMAAck2
P06
DMAAck3
P11
DMAReq0
R03
DMAReq1
M11
DMAReq2
N11
DMAReq3
P01
DQS0
AC20
DQS1
AC16
DQS2
AC14
DQS3
AB13
DQS4
AC11
DQS5
AC09
DQS6
Y04
DQS7
T01
DQS8
AA05
Interface Group
Page
DDR SDRAM
49
External Slave Peripheral
50
External Slave Peripheral
50
DDR SDRAM
49
DrvrInh1
L07
System
53
DrvrInh2
A05
System
53
AMCC
19
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
Ball
ECC0
AB07
ECC1
AB06
ECC2
AD06
ECC3
W07
ECC4
U09
ECC5
AC03
ECC6
AB04
ECC7
AD04
Interface Group
Page
DDR SDRAM
49
EMCCD, EMC1RxErr
J07
Ethernet
49
EMCCrS, EMC0CrSDV
K07
Ethernet
49
EMCMDClk
J08
Ethernet
49
EMCMDIO
L05
Ethernet
49
EMCRxClk
J02
Ethernet
49
EMCRxD0, EMC0RxD0
G03
EMCRxD1, EMC0RxD1
E01
Ethernet
49
EMCRxD2, EMC1RxD0
A07
EMCRxD3, EMC1RxD1
H09
EMCRxDV, EMC1CrSDV
K01
Ethernet
49
EMCRxErr, EMC0RxErr
K03
Ethernet
49
EMCTxClk, EMCRefClk
J06
Ethernet
49
EMCTxD0, EMC0TxD0
L09
EMCTxD1, EMC0TxD1
K05
Ethernet
49
EMCTxD2, EMC1TxD0
J04
EMCTxD3, EMC1TxD1
J03
EMCTxEn, EMC0TxEn
L06
Ethernet
49
EMCTxErr, EMC1TxEn
C05
Ethernet
49
EOT0/TC0
R16
EOT1/TC1
P15
External Slave Peripheral
50
EOT2/TC2
P16
EOT3/TC3
M16
ExtAck
AA22
External Master Peripheral
51
ExtReq
AB23
External Master Peripheral
51
T17
External Master Peripheral
51
ExtReset
20
(Sheet 3 of 22)
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 4 of 22)
Ball
GND
B06
GND
B10
GND
B13
GND
B17
GND
B21
GND
D04
GND
D08
GND
D12
GND
D15
GND
D19
GND
D23
GND
F02
GND
F06
GND
F10
GND
F13
GND
F17
GND
F21
GND
H04
GND
H08
GND
H12
GND
H15
GND
H19
GND
H23
GND
K02
GND
K06
GND
K10
GND
K13
GND
K17
GND
K21
GND
M04
Interface Group
Power
AMCC
Page
54
21
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signals Listed Alphabetically
Signal Name
22
(Sheet 5 of 22)
Ball
GND
M08
GND
M12
GND
M15
GND
M19
GND
M23
GND
N02
GND
N06
GND
N10
GND
N13
GND
N17
GND
N21
GND
R04
GND
R08
GND
R12
GND
R15
GND
R19
GND
R23
GND
U02
GND
U06
GND
U10
GND
U13
GND
U17
GND
U21
GND
W04
GND
W08
GND
W12
GND
W15
GND
W19
GND
W23
Interface Group
Power
Page
54
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 6 of 22)
Ball
GND
AA02
GND
AA06
GND
AA10
GND
AA13
GND
AA17
GND
AA21
GND
AC04
GND
AC08
GND
AC12
GND
AC15
GND
AC19
AMCC
Interface Group
Power
Page
54
23
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
24
(Sheet 7 of 22)
Ball
[GPIO00]IRQ00
N18
[GPIO01]IRQ01
L20
[GPIO02]IRQ02
P20
[GPIO03]IRQ03
L18
[GPIO04]IRQ04
N14
[GPIO05]IRQ05
M20
[GPIO06]IRQ06
M14
[GPIO07]IRQ07
P18
[GPIO08]IRQ08
N20
[GPIO09]IRQ09
P22
[GPIO10]IRQ10
V18
GPIO11
P14
[GPIO12]UART1_Rx
C18
[GPIO13]UART1_Tx
J16
[GPIO14]UART1_DSR/CTS
G06
[GPIO15]UART1_RTS/DTR
E05
[GPIO16]IIC1SClk
H11
[GPIO17]IIC1SDA
H14
[GPIO18]TrcBS0
N16
[GPIO19]TrcBS1
P17
[GPIO20]TrcBS2
T20
[GPIO21]TrcES0
T21
[GPIO22]TrcES1
P23
[GPIO23]TrcES2
N09
[GPIO24]TrcES3
P08
[GPIO25]TrcES4
T05
[GPIO26]TrcTS0
T04
[GPIO27]TrcTS1
P03
[GPIO28]TrcTS2
R07
[GPIO29]TrcTS3
P09
[GPIO30]TrcTS4
R09
[GPIO31]TrcTS5
T06
Halt
HoldAck
Interface Group
Page
System
53
V05
System
53
Y21
External Master Peripheral
51
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 8 of 22)
Ball
Interface Group
Page
HoldReq
Y23
External Master Peripheral
51
IIC0SClk
G11
IIC Peripheral
52
IIC0SDA
G13
IIC Peripheral
52
IIC1SClk[GPIO16]
H11
IIC Peripheral
52
IIC1SDA[GPIO17]
H14
IIC Peripheral
52
IRQ00[GPIO00]
N18
IRQ01[GPIO01]
L20
IRQ02[GPIO02]
P20
IRQ03[GPIO03]
L18
IRQ04[GPIO04]
N14
IRQ05[GPIO05]
M20
IRQ06[GPIO06]
M14
IRQ07[GPIO07]
P18
IRQ08[GPIO08]
N20
Interrupts
52
IRQ09[GPIO09]
P22
IRQ10[GPIO10]
V18
[IRQ11]PCIReq1
E21
[IRQ12]PCIGnt1
C22
MemAddr00
Y19
MemAddr01
AD20
MemAddr02
Y20
MemAddr03
AB20
MemAddr04
AD18
MemAddr05
AD16
MemAddr06
AB18
DDR SDRAM
49
MemAddr07
Y14
MemAddr08
V13
MemAddr09
V11
MemAddr10
W16
MemAddr11
Y11
MemAddr12
V10
MemClkOut0
V09
DDR SDRAM
49
MemClkOut0
V08
AMCC
25
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 9 of 22)
Ball
MemData00
AD21
MemData01
AB21
MemData02
AC22
MemData03
AA20
MemData04
U16
MemData05
V17
MemData06
AD19
MemData07
AB19
MemData08
W18
MemData09
V16
MemData10
Y17
MemData11
AB16
MemData12
AC18
MemData13
Y18
MemData14
R14
MemData15
AB17
MemData16
AA14
MemData17
AD15
MemData18
T15
MemData19
V15
MemData20
Y16
MemData21
U14
MemData22
T13
MemData23
Y15
MemData24
AD13
MemData25
AD14
MemData26
V14
MemData27
Y13
MemData28
P12
MemData29
AB12
MemData30
Y12
MemData31
V12
Interface Group
DDR SDRAM
26
Page
49
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 10 of 22)
Ball
MemData32
W11
MemData33
AD12
MemData34
Y10
MemData35
T12
MemData36
U11
MemData37
T11
MemData38
T10
MemData39
AD10
MemData40
AB08
MemData41
AD08
MemData42
R11
MemData43
Y07
MemData44
AC07
MemData45
AB09
MemData46
Y06
MemData47
Y08
MemData48
AA01
MemData49
AA03
MemData50
AB02
MemData51
Y01
MemData52
AB03
MemData53
Y02
MemData54
V07
MemData55
V01
MemData56
T08
MemData57
U07
MemData58
W01
MemData59
W03
MemData60
V06
MemData61
T07
MemData62
W05
MemData63
U05
MemVRef1
T14
MemVRef2
T09
AMCC
Interface Group
Page
DDR SDRAM
49
DDR SDRAM
49
27
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 11 of 22)
Ball
No ball
A01
No ball
A02
No ball
A03
No ball
A22
No ball
A23
No ball
A24
No ball
B01
No ball
B02
No ball
B23
No ball
B24
No ball
C01
No ball
C24
No ball
AB01
No ball
AB24
No ball
AC01
No ball
AC02
No ball
AC23
No ball
AC24
No ball
AD01
No ball
AD02
No ball
AD03
No ball
AD22
No ball
AD23
No ball
AD24
Interface Group
A physical ball does not exist at these ball coordinates.
28
Page
NA
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 12 of 22)
Ball
OVDD
B04
OVDD
B12
OVDD
B19
OVDD
D02
OVDD
D10
OVDD
D17
OVDD
F08
OVDD
F15
OVDD
F23
OVDD
H06
OVDD
H10
OVDD
H13
OVDD
H21
OVDD
K04
OVDD
K08
OVDD
K19
OVDD
M02
OVDD
M17
OVDD
N08
OVDD
N23
OVDD
R06
OVDD
R17
OVDD
R21
OVDD
U04
OVDD
U19
OVDD
W02
OVDD
AA23
PCIX133Cap
PCIXAck64
AMCC
Interface Group
Page
Power
54
G08
PCI-X
48
D09
PCI-X
48
29
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 13 of 22)
Ball
PCIXAD00
C17
PCIXAD01
B09
PCIXAD02
G10
PCIXAD03
E10
PCIXAD04
C10
PCIXAD05
A10
PCIXAD06
F11
PCIXAD07
G12
PCIXAD08
G14
PCIXAD09
A15
PCIXAD10
C15
PCIXAD11
E15
PCIXAD12
G15
PCIXAD13
B16
PCIXAD14
C16
PCIXAD15
D16
PCIXAD16
E18
PCIXAD17
E19
PCIXAD18
F18
PCIXAD19
G18
PCIXAD20
D20
PCIXAD21
A20
PCIXAD22
A21
PCIXAD23
C21
PCIXAD24
F22
PCIXAD25
B22
PCIXAD26
G21
PCIXAD27
E23
PCIXAD28
C23
PCIXAD29
F24
PCIXAD30
D22
PCIXAD31
D24
Interface Group
PCI-X
30
Page
48
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 14 of 22)
Ball
PCIXAD32
H03
PCIXAD33
H01
PCIXAD34
L08
PCIXAD35
F01
PCIXAD36
D01
PCIXAD37
J05
PCIXAD38
H05
PCIXAD39
G02
PCIXAD40
E02
PCIXAD41
C02
PCIXAD42
A08
PCIXAD43
G05
PCIXAD44
F03
PCIXAD45
D03
PCIXAD46
B03
PCIXAD47
H07
PCIXAD48
G04
PCIXAD49
E04
PCIXAD50
C04
PCIXAD51
A04
PCIXAD52
F05
PCIXAD53
D05
PCIXAD54
B05
PCIXAD55
C09
PCIXAD56
E06
PCIXAD57
C06
PCIXAD58
A06
PCIXAD59
F07
PCIXAD60
E07
PCIXAD61
D07
PCIXAD62
B07
PCIXAD63
E08
Interface Group
PCI-X
AMCC
Page
48
31
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signals Listed Alphabetically
Signal Name
32
(Sheet 15 of 22)
Ball
PCIXC0[BE0]
F14
PCIXC1[BE1]
E16
PCIXC2[BE2]
C19
PCIXC3[BE3]
F20
PCIXC4[BE4]
C08
PCIXC5[BE5]
C03
PCIXC6[BE6]
G09
PCIXC7[BE7]
F09
PCIXCap
Interface Group
Page
PCI-X
48
L23
PCI-X
48
PCIXClk
E03
PCI-X
48
PCIXDevSel
E13
PCI-X
48
PCIXFrame
A11
PCI-X
48
PCIXGnt0
E22
PCIXGnt1[IRQ12]
C22
PCIXGnt2
N22
PCI-X
48
PCIXGnt3
M18
PCIXGnt4
R22
PCIXGnt5
P19
PCIXIDSel
G07
PCI-X
48
PCIXINT
M07
PCI-X
48
PCIXIRDY
E12
PCI-X
48
PCIXM66En
A14
PCI-X
48
PCIXParHigh
L04
PCI-X
48
PCIXParLow
F16
PCI-X
48
PCIXPErr
A17
PCI-X
48
PCIXReq0
E24
PCIXReq1[IRQ11]
E21
PCIXReq2
E20
PCI-X
48
PCIXReq3
R20
PCIXReq4
G23
PCIXReq5
R18
PCIXReq64
E09
PCI-X
48
PCIXReset
M24
PCI-X
48
PCIXSErr
A18
PCI-X
48
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 16 of 22)
Ball
Interface Group
Page
PCIXStop
L12
PCI-X
48
PCIXTRDY
C12
PCI-X
48
PerAddr00
D11
PerAddr01
C11
PerAddr02
B11
PerAddr03
A12
PerAddr04
A19
PerAddr05
D18
PerAddr06
E11
PerAddr07
M03
PerAddr08
N01
PerAddr09
E14
PerAddr10
C20
PerAddr11
A16
PerAddr12
A13
PerAddr13
B14
PerAddr14
C14
PerAddr15
D14
50
PerAddr16
B20
External Slave Peripheral
Note: PerAddr00 is the most significant bit (msb) on this bus.
PerAddr17
L15
PerAddr18
L21
PerAddr19
L22
PerAddr20
M22
PerAddr21
M01
PerAddr22
L24
PerAddr23
P24
PerAddr24
T19
PerAddr25
R24
PerAddr26
U22
PerAddr27
U24
PerAddr28
N03
PerAddr29
V20
PerAddr30
V23
PerAddr31
V21
AMCC
33
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
34
(Sheet 17 of 22)
Ball
Interface Group
Page
PerBLast
C07
External Slave Peripheral
50
PerClk
U18
External Master Peripheral
51
PerCS0
E17
PerCS1
L10
PerCS2
V04
PerCS3
T24
External Slave Peripheral
50
PerCS4
L03
PerCS5
T03
PerCS6
L13
PerCS7
U03
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 18 of 22)
Ball
PerData00
H24
PerData01
H22
PerData02
H20
PerData03
G20
PerData04
G19
PerData05
H18
PerData06
J23
PerData07
J22
PerData08
J21
PerData09
J20
PerData10
J19
PerData11
J18
PerData12
J17
PerData13
J15
PerData14
J14
PerData15
J13
PerData16
J12
PerData17
J11
PerData18
J10
PerData19
J09
PerData20
L14
PerData21
K24
PerData22
K22
PerData23
K20
PerData24
K18
PerData25
K16
PerData26
K14
PerData27
K11
PerData28
K09
PerData29
L19
PerData30
L17
PerData31
L16
PerErr
PerOE
AMCC
Interface Group
Page
External Slave Peripheral
Note: PerData00 is the most significant bit (msb) on this bus.
50
P21
External Master Peripheral
51
M09
External Slave Peripheral
50
35
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
Ball
PerPar0
T23
PerPar1
T22
PerPar2
W20
PerPar3
U20
PerReady[RcvrInh]
Interface Group
Page
External Slave Peripheral
50
N07
External Slave Peripheral
50
PerR/W
P05
External Slave Peripheral
50
PerWBE0
T18
PerWBE1
V19
External Slave Peripheral
50
PerWBE2
W22
PerWBE3
W24
PerWE
P02
External Slave Peripheral
50
DDR SDRAM
49
RAS
36
(Sheet 19 of 22)
AD07
[RcvrInh]PerReady
N07
System
53
RefVEn
L02
System
53
Reserved
L01
Reserved
54
Reserved
P04
SVDD
U12
SVDD
U15
SVDD
W10
SVDD
W17
SVDD
AA08
Power
54
SVDD
AA15
SVDD
AC06
SVDD
AC13
SVDD
AC21
SysClk
G22
System
53
SysErr
T02
System
53
SysReset
P10
System
53
TCK
V22
JTAG
52
TDI
Y24
JTAG
52
TDO
Y22
JTAG
52
TestEn
M05
System
53
TmrClk
U01
System
53
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
TMS
(Sheet 20 of 22)
Ball
AB22
Interface Group
Page
JTAG
52
Trace
54
Trace
54
Trace
54
TrcBS0[GPIO18]
N16
TrcBS1[GPIO19]
P17
TrcBS2[GPIO20]
T20
TrcClk
R05
TrcES0[GPIO21]
T21
TrcES1[GPIO22]
P23
TrcES2[GPIO23]
N09
TrcES3[GPIO24]
P08
TrcES4[GPIO25]
T05
TrcTS0[GPIO26]
T04
Trace
54
TrcTS1[GPIO27]
P03
Trace
54
TrcTS2[GPIO28]
R07
Trace
54
TrcTS3[GPIO29]
P09
Trace
54
TrcTS4[GPIO30]
R09
Trace
54
TrcTS5[GPIO31]
T06
Trace
54
TrcTS6
R01
Trace
54
TRST
N24
JTAG
52
UART0_CTS
C13
UART Peripheral
51
UART0_DCD
V24
UART Peripheral
Note: Used as initialization strapping input.
51
UART0_DSR
V02
UART Peripheral
Note: Used as initialization strapping input.
51
UART0_DTR
B18
UART Peripheral
51
UART0_RI
H16
UART Peripheral
51
UART0_RTS
G16
UART Peripheral
51
UART0_Rx
G17
UART Peripheral
51
UART0_Tx
L11
UART Peripheral
51
UART1_DSR/CTS[GPIO14]
G06
UART Peripheral
51
UART1_RTS/DTR[GPIO15]
E05
UART Peripheral
51
UART1_Rx[GPIO12]
C18
UART Peripheral
51
UART1_Tx[GPIO13]
J16
UART Peripheral
51
AMCC
37
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signals Listed Alphabetically
Signal Name
38
(Sheet 21 of 22)
Ball
UARTSerClk
A09
VDD
B08
VDD
B15
VDD
D06
VDD
D13
VDD
D21
VDD
F04
VDD
F12
VDD
F19
VDD
H02
VDD
H17
VDD
K12
VDD
K15
VDD
K23
VDD
M06
VDD
M10
VDD
M13
VDD
M21
VDD
N04
VDD
N12
VDD
N15
Interface Group
Page
UART Peripheral
51
Power
54
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically
Signal Name
(Sheet 22 of 22)
Ball
VDD
N19
VDD
R02
VDD
R10
VDD
R13
VDD
U08
VDD
U23
VDD
W06
VDD
W13
VDD
W21
VDD
AA04
VDD
AA12
VDD
AA19
VDD
AC10
VDD
AC17
WE
Y05
AMCC
Interface Group
Page
Power
54
DDR SDRAM
49
39
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction
signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look
up the primary signal name in “Signals Listed Alphabetically” on page 18.
Signals Listed by Ball Assignment
Ball
40
Signal Name
Ball
(Sheet 1 of 6)
Signal Name
Ball
Signal Name
Ball
Signal Name
A01
No ball
B01
No ball
C01
No ball
D01
PCIXAD36
A02
No ball
B02
No ball
C02
PCIXAD41
D02
OVDD
A03
No ball
B03
PCIXAD46
C03
PCIXC5 *
D03
PCIXAD45
A04
PCIXAD51
B04
OVDD
C04
PCIXAD50
D04
GND
A05
DrvrInh2
B05
PCIXAD54
C05
EMCTxErr *
D05
PCIXAD53
A06
PCIXAD58
B06
GND
C06
PCIXAD57
D06
VDD
A07
EMCRxD2 *
B07
PCIXAD62
C07
PerBLast
D07
PCIXAD61
A08
PCIXAD42
B08
VDD
C08
PCIXC4 *
D08
GND
A09
UARTSerClk
B09
PCIXAD01
C09
PCIXAD55
D09
PCIXAck64
A10
PCIXAD05
B10
GND
C10
PCIXAD04
D10
OVDD
A11
PCIXFrame
B11
PerAddr02
C11
PerAddr01
D11
PerAddr00
A12
PerAddr03
B12
OVDD
C12
PCIXTRDY
D12
GND
A13
PerAddr12
B13
GND
C13
UART0_CTS
D13
VDD
A14
PCIXM66En
B14
PerAddr13
C14
PerAddr14
D14
PerAddr15
A15
PCIXAD09
B15
VDD
C15
PCIXAD10
D15
GND
A16
PerAddr11
B16
PCIXAD13
C16
PCIXAD14
D16
PCIXAD15
A17
PCIXPErr
B17
GND
C17
PCIXAD00
D17
OVDD
A18
PCIXSErr
B18
UART0_DTR
C18
UART1_Rx *
D18
PerAddr05
A19
PerAddr04
B19
OVDD
C19
PCIXC2 *
D19
GND
A20
PCIXAD21
B20
PerAddr16
C20
PerAddr10
D20
PCIXAD20
A21
PCIXAD22
B21
GND
C21
PCIXAD23
D21
VDD
A22
No ball
B22
PCIXAD25
C22
PCIXGnt1 *
D22
PCIXAD30
A23
No ball
B23
No ball
C23
PCIXAD28
D23
GND
A24
No ball
B24
No ball
C24
No ball
D24
PCIXAD31
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment
Ball
Signal Name
Ball
(Sheet 2 of 6)
Signal Name
Ball
Signal Name
Ball
Signal Name
E01
EMCRxD1 *
F01
PCIXAD35
G01
APVDD for PCI PLL
H01
PCIXAD33
E02
PCIXAD40
F02
GND
G02
PCIXAD39
H02
VDD
E03
PCIXClk
F03
PCIXAD44
G03
EMCRxD0 *
H03
PCIXAD32
E04
PCIXAD49
F04
VDD
G04
PCIXAD48
H04
GND
E05
UART1_RTS/DTR *
F05
PCIXAD52
G05
PCIXAD43
H05
PCIXAD38
E06
PCIXAD56
F06
GND
G06
UART1_DSR/CTS *
H06
OVDD
E07
PCIXAD60
F07
PCIXAD59
G07
PCIXIDSel
H07
PCIXAD47
E08
PCIXAD63
F08
OVDD
G08
PCIX133Cap
H08
GND
E09
PCIXReq64
F09
PCIXC7 *
G09
PCIXC6 *
H09
EMCRxD3 *
E10
PCIXAD03
F10
GND
G10
PCIXAD02
H10
OVDD
E11
PerAddr06
F11
PCIXAD06
G11
IIC0SClk
H11
IIC1SClk *
E12
PCIXIRDY
F12
VDD
G12
PCIXAD07
H12
GND
E13
PCIXDevSel
F13
GND
G13
IIC0SDA
H13
OVDD
E14
PerAdd09
F14
PCIXC0 *
G14
PCIXAD08
H14
IIC1SDA *
E15
PCIXAD11
F15
OVDD
G15
PCIXAD12
H15
GND
E16
PCIXC1 *
F16
PCIXParLow
G16
UART0_RTS
H16
UART0_RI
E17
PerCS0
F17
GND
G17
UART0_Rx
H17
VDD
E18
PCIXAD16
F18
PCIXAD18
G18
PCIXAD19
H18
PerData05
E19
PCIXAD17
F19
VDD
G19
PerData04
H19
GND
E20
PCIXReq2
F20
PCIXC3 *
G20
PerData03
H20
PerData02
E21
PCIXReq1 *
F21
GND
G21
PCIXAD26
H21
OVDD
E22
PCIXGnt0
F22
PCIXAD24
G22
SysClk
H22
PerData01
E23
PCIXAD27
F23
OVDD
G23
PCIXReq4
H23
GND
E24
PCIXReq0
F24
PCIXAD29
G24
ASVDD for SysClk PLL
H24
PerData00
AMCC
41
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment
Ball
42
Signal Name
Ball
(Sheet 3 of 6)
Signal Name
Ball
Signal Name
Ball
Signal Name
J01
AGND
K01
EMCRxDV *
L01
Reserved
M01
PerAddr21
J02
EMCRxClk
K02
GND
L02
RefVEn
M02
OVDD
J03
EMCTxD3 *
K03
EMCRxErr *
L03
PerCS4
M03
PerAddr07
J04
EMCTxD2 *
K04
OVDD
L04
PCIXParHigh
M04
GND
J05
PCIXAD37
K05
EMCTxD1 *
L05
EMCMDIO
M05
TestEn
J06
EMCTxClk *
K06
GND
L06
EMCTxEn *
M06
VDD
J07
EMCCD *
K07
EMCCrS *
L07
DrvrInh1
M07
PCIXINT
J08
EMCMDClk
K08
OVDD
L08
PCIXAD34
M08
GND
J09
PerData19
K09
PerData28
L09
EMCTxD0 *
M09
PerOE
J10
PerData18
K10
GND
L10
PerCS1
M10
VDD
J11
PerData17
K11
PerData27
L11
UART0_Tx
M11
DMAReq1
J12
PerData16
K12
VDD
L12
PCIXStop
M12
GND
J13
PerData15
K13
GND
L13
PerCS6
M13
VDD
J14
PerData14
K14
PerData26
L14
PerData20
M14
IRQ06 *
J15
PerData13
K15
VDD
L15
PerAddr17
M15
GND
J16
UART1_Tx *
K16
PerData25
L16
PerData31
M16
EOT3/TC3
J17
PerData12
K17
GND
L17
PerData30
M17
OVDD
J18
PerData11
K18
PerData24
L18
IRQ03 *
M18
PCIXGnt3
J19
PerData10
K19
OVDD
L19
PerData29
M19
GND
J20
PerData9
K20
PerData23
L20
IRQ01 *
M20
IRQ05 *
J21
PerData8
K21
GND
L21
PerAddr18
M21
VDD
J22
PerData7
K22
PerData22
L22
PerAddr19
M22
PerAddr20
J23
PerData6
K23
VDD
L23
PCIXCap
M23
GND
J24
AGND
K24
PerData21
L24
PerAddr22
M24
PCIXReset
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment
Ball
Signal Name
Ball
(Sheet 4 of 6)
Signal Name
Ball
Signal Name
Ball
Signal Name
N01
PerAddr08
P01
DMAReq3
R01
TrcTS6
T01
DQS7
N02
GND
P02
PerWE
R02
VDD
T02
SysErr
N03
PerAddr28
P03
TrcTS1 *
R03
DMAReq0
T03
PerCS5
N04
VDD
P04
Reserved
R04
GND
T04
TrcTS0 *
N05
DMAAck0
P05
PerR/W
R05
TrcClk
T05
TrcES4 *
N06
GND
P06
DMAAck2
R06
OVDD
T06
TrcTS5 *
N07
PerReady *
P07
DMAAck1
R07
TrcTS2 *
T07
MemData61
N08
OVDD
P08
TrcES3 *
R08
GND
T08
MemData56
N09
TrcES2 *
P09
TrcTS3 *
R09
TrcTS4 *
T09
MemVRef2
N10
GND
P10
SysReset
R10
VDD
T10
MemData38
N11
DMAReq2
P11
DMAAck3
R11
MemData42
T11
MemData37
N12
VDD
P12
MemData28
R12
GND
T12
MemData35
N13
GND
P13
DM3
R13
VDD
T13
MemData22
N14
IRQ04 *
P14
GPIO11
R14
MemData14
T14
MemVRef1
N15
VDD
P15
EOT1/TC1
R15
GND
T15
MemData18
N16
TrcBS0 *
P16
EOT2/TC2
R16
EOT0/TC0
T16
DM0
N17
GND
P17
TrcBS1 *
R17
OVDD
T17
ExtReset
N18
IRQ00 *
P18
IRQ07 *
R18
PCIXReq5
T18
PerWBE0
N19
VDD
P19
PCIXGnt5
R19
GND
T19
PerAddr24
N20
IRQ08 *
P20
IRQ02 *
R20
PCIXReq3
T20
TrcBS2 *
N21
GND
P21
PerErr
R21
OVDD
T21
TrcES0 *
N22
PCIXGnt2
P22
IRQ09 *
R22
PCIXGnt4
T22
PerPar1
N23
OVDD
P23
TrcES1 *
R23
GND
T23
PerPar0
N24
TRST
P24
PerAddr23
R24
PerAddr25
T24
PerCS3
AMCC
43
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment
Ball
44
Signal Name
Ball
(Sheet 5 of 6)
Signal Name
Ball
Signal Name
Ball
Signal Name
U01
TmrClk
V01
MemData55
W01
MemData58
Y01
MemData51
U02
GND
V02
UART0_DSR
W02
OVDD
Y02
MemData53
U03
PerCS7
V03
DM7
W03
MemData59
Y03
DM6
U04
OVDD
V04
PerCS2
W04
GND
Y04
DQS6
U05
MemData63
V05
Halt
W05
MemData62
Y05
WE
U06
GND
V06
MemData60
W06
VDD
Y06
MemData46
U07
MemData57
V07
MemData54
W07
ECC3
Y07
MemData43
U08
VDD
V08
MemClkOut0
W08
GND
Y08
MemData47
U09
ECC4
V09
MemClkOut0
W09
ClkEn3
Y09
ClkEn2
U10
GND
V10
MemAddr12
W10
SVDD
Y10
MemData34
U11
MemData36
V11
MemAddr9
W11
MemData32
Y11
MemAddr11
U12
SVDD
V12
MemData31
W12
GND
Y12
MemData30
U13
GND
V13
MemAddr8
W13
VDD
Y13
MemData27
U14
MemData21
V14
MemData26
W14
BankSel1
Y14
MemAddr7
U15
SVDD
V15
MemData19
W15
GND
Y15
MemData23
U16
MemData04
V16
MemData09
W16
MemAddr10
Y16
MemData20
U17
GND
V17
MemData05
W17
SVDD
Y17
MemData10
U18
PerClk
V18
IRQ10 *
W18
MemData08
Y18
MemData13
U19
OVDD
V19
PerWBE1
W19
GND
Y19
MemAddr00
U20
PerPar3
V20
PerAddr29
W20
PerPar2
Y20
MemAddr02
U21
GND
V21
PerAddr31
W21
VDD
Y21
HoldAck
U22
PerAddr26
V22
TCK
W22
PerWBE2
Y22
TDO
U23
VDD
V23
PerAddr30
W23
GND
Y23
HoldReq
U24
PerAddr27
V24
UART0_DCD
W24
PerWBE3
Y24
TDI
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment
Ball
Signal Name
Ball
(Sheet 6 of 6)
Signal Name
Ball
Signal Name
Ball
Signal Name
AA01
MemData48
AB01
No ball
AC01
No ball
AD01
No ball
AA02
GND
AB02
MemData50
AC02
No ball
AD02
No ball
AA03
MemData49
AB03
MemData52
AC03
ECC5
AD03
No ball
AA04
VDD
AB04
ECC6
AC04
GND
AD04
ECC7
AA05
DQS8
AB05
CAS
AC05
DM8
AD05
BankSel3
AA06
GND
AB06
ECC1
AC06
SVDD
AD06
ECC2
AA07
DM5
AB07
ECC0
AC07
MemData44
AD07
RAS
AA08
SVDD
AB08
MemData40
AC08
GND
AD08
MemData41
AA09
DM4
AB09
MemData45
AC09
DQS5
AD09
BA1
AA10
GND
AB10
ClkEn1
AC10
VDD
AD10
MemData39
AA11
AGND
AB11
AMVDD for MemClk
PLL
AC11
DQS4
AD11
BankSel2
AA12
VDD
AB12
MemData29
AC12
GND
AD12
MemData33
AA13
GND
AB13
DQS3
AC13
SVDD
AD13
MemData24
AA14
MemData16
AB14
DM2
AC14
DQS2
AD14
MemData25
AA15
SVDD
AB15
BankSel0
AC15
GND
AD15
MemData17
AA16
BA0
AB16
MemData11
AC16
DQS1
AD16
MemAddr5
AA17
GND
AB17
MemData15
AC17
VDD
AD17
ClkEn0
AA18
DM1
AB18
MemAddr6
AC18
MemData12
AD18
MemAddr4
AA19
VDD
AB19
MemData07
AC19
GND
AD19
MemData06
AA20
MemData03
AB20
MemAddr3
AC20
DQS0
AD20
MemAddr01
AA21
GND
AB21
MemData01
AC21
SVDD
AD21
MemData00
AA22
ExtAck
AB22
TMS
AC22
MemData02
AD22
No ball
AA23
OVDD
AB23
ExtReq
AC23
No ball
AD23
No ball
AA24
BusReq
AB24
No ball
AC24
No ball
AD24
No ball
AMCC
45
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Description
The PPC440GP embedded controller is provided in a 552-ball, ball grid array package. The following tables
describe the package level pinout.
Pin Summary
Group
No. of Pins
Signal pins, non-multiplexed
347
Signal pins, multiplexed
57
Total Signal Pins
404
AxVDD
3
AGnd
3
OVDD
27
SVDD
9
VDD
34
Gnd
70
Total Power Pins
146
Reserved
2
Total Pins
552
In the table “Signal Functional Description” on page 48, each I/O signal is listed along with a short description of its
function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed
Alphabetically” on page 18 for the pin (ball) number to which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals
Listed Alphabetically” on page 18. It is expected that in any single application a particular pin will always be
programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin
selection than would otherwise be possible.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr00:31) are used as outputs by the PPC440GP to broadcast an address to external slave devices
when the PPC440GP has control of the external bus. When during the course of normal chip operation an external
master gains ownership of the external bus, these same pins are used as inputs which are driven by the external
master and received by the EBC in the PPC440GP. In this example, the pins are also bidirectional, serving both as
inputs and outputs.
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown.
46
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 80). Note that
these are not multiplexed pins since the function of the pins is not programmable.
AMCC
47
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signal Functional Description
(Sheet 1 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
PCI-X Interface
PCIXAD00:63
Address/Data bus (bidirectional).
I/O
3.3V PCI
PCIXC0:7[BE0:7]
PCI-X Command[Byte Enables].
I/O
3.3V PCI
PCIXCap
Capable of PCI-X operation.
I
5V tolerant
3.3V LVTTL
PCIX133Cap
PCI-X devices are 133 MHz capable.
O
3.3V PCI
PCIXClk
Note: If the PCI-X interface is not being used, drive this pin with a
I
3.3V PCI
5
Provides timing to the PCI interface for PCI transactions.
3.3V clock signal at a frequency between 1 and 66MHz
PCIXDevSel
Indicates the driving device has decoded its address as the target
of the current access.
I/O
3.3V PCI
4
PCIXFrame
Driven by the current master to indicate beginning and duration of
an access.
I/O
3.3V PCI
4
PCIXGnt0
Indicates that the specified agent is granted access to the bus.
I/O
3.3V PCI
4
PCIXGnt1
Indicates that the specified agent is granted access to the bus.
I/O
3.3V PCI
4
PCIXGnt2:5
Indicates that the specified agent is granted access to the bus.
O
3.3V PCI
PCIXIDSel
Used as a chip select during configuration read and write
transactions.
I
3.3V PCI
PCIXINT
Level sensitive PCI interrupt.
O
3.3V PCI
PCIXIRDY
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
I/O
3.3V PCI
4
PCIXM66En
Capable of 66MHz operation.
I
5V tolerant
3.3V LVTTL
5
PCIXParHigh
Even parity across PCIAD32:63 and PCIXC0:3[BE4:7].
I/O
3.3V PCI
PCIXParLow
Even parity across PCIAD0:31 and PCIXC0:3[BE0:3].
I/O
3.3V PCI
PCIXPErr
Reports data parity errors during all PCI transactions except a
Special Cycle.
I/O
3.3V PCI
4
PCIXReq0
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus.
I/O
3.3V PCI
4
PCIXReq1:5
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus.
I
3.3V PCI
4
5
PCIXReq64
Asserted by the current bus master, indicating a 64-bit transfer.
I/O
3.3V PCI
4
PCIXAck64
Indicates the target can transfer data using 64 bits.
I/O
3.3V PCI
4
PCIXReset
Brings PCI device registers and logic to a consistent state.
O
3.3V PCI
PCIXSErr
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
I/O
3.3V PCI
4
PCIXStop
Indicates the current target is requesting the master to stop the
current transaction.
I/O
3.3V PCI
4
PCIXTRDY
Indicates the target agent’s ability to complete the current data
phase of the transaction.
I/O
3.3V PCI
4
48
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description
(Sheet 2 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
DDR SDRAM Interface
BA0:1
Bank Address supporting up to four internal banks.
O
2.5V SSTL_2
BankSel0:3
Selects up to four external DDR SDRAM banks.
O
2.5V SSTL_2
CAS
Column Address Strobe.
O
2.5V SSTL_2
ClkEn0:3
Clock Enable. One for each bank.
O
2.5V SSTL_2
DM0:8
Memory write data byte lane masks. MEMDM8 is the byte lane
mask for the ECC byte lane.
O
2.5V SSTL_2
DQS0:8
Byte lane data strobe. DQS8 is the data strobe for the ECC byte
lane.
I/O
2.5V SSTL_2
ECC0:7
ECC check bits 0:7.
I/O
2.5V SSTL_2
MemAddr00:12
Memory address bus.
O
2.5V SSTL_2
MemClkOut0
MemClkOut0
Subsystem clock.
O
2.5V SSTL_2
MemData00:63
Memory data bus.
I/O
2.5V SSTL_2
MemVRef1:2
Memory reference voltage (SVREF) input.
I
Voltage Ref
Receiver
RAS
Row Address Strobe.
O
2.5V SSTL_2
WE
Write Enable.
O
2.5V SSTL_2
EMCCD,
EMC1RxErr
MII: Collision detection
RMII 1: Receive error
I/O
5V tolerant
3.3V LVTTL
EMCCrS,
EMC0CrSDV
MII: Carrier sense
RMII 0: Carrier sense data valid
I/O
5V tolerant
3.3V LVTTL
EMCMDClk
MII and RMII: Management data clock
O
5V tolerant
3.3V LVTTL
EMCMDIO
MII and RMII: Transfer command and status information between
MII and PHY
I/O
5V tolerant
3.3V LVTTL
EMCRxD0:3,
EMC0RxD0:1,
EMC1RxD0:1
MII: Receive data
RMII 0: Receive data
RMII 1: Receive data
I/O
5V tolerant
3.3V LVTTL
EMCRxDV,
EMC1CrSDV
MII: Receive data valid
RMII 1: Carrier sense data valid
I
5V tolerant
3.3V LVTTL
EMCRxClk
MII: Receive clock
I
5V tolerant
3.3V LVTTL
EMCRxErr,
EMC0RxErr
MII: Receive error
RMII 0: Receive error
I
5V tolerant
3.3V LVTTL
EMCTxClk,
EMCRefClk
MII: Transmit clock
RMII: Reference clock
I
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
Ethernet Interface
EMCTxD0:3,
EMC0TxD0:1,
EMC1TxD0:1
AMCC
MII: Transmit data
RMII 0: Transmit data
RMII 1: Transmit data
5
49
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signal Functional Description
(Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
EMCTxEn,
EMC0TxEn
EMCTxErr,
EMC1TxEn
Description
MII: Transmit data enabled
RMII 0: Transmit data enabled
MII: Transmit error:
RMII: Transmit data enabled
I/O
Type
O
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
Notes
External Slave Peripheral Interface
DMAAck0:3
Used by the PPC440GP to indicate that data transfers have
occurred.
O
5V tolerant
3.3V LVTTL
DMAReq0:3
Used by slave peripherals to indicate they are prepared to transfer
data.
I
5V tolerant
3.3V LVTTL
1, 5
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
5V tolerant
3.3V LVTTL
1, 5
PerAddr00:31
Peripheral address bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note: PerAddr00 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:3
External peripheral data bus byte enables.
I/O
5V tolerant
3.3V LVTTL
1, 2
PerBLast
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory access.
I/O
5V tolerant
3.3V LVTTL
1, 4
PerCS0:7
External peripheral device select.
O
5V tolerant
3.3V LVTTL
2
PerData00:31
Peripheral data bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerOE
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440GP is the
bus master, it enables the selected device to drive the bus.
O
5V tolerant
3.3V LVTTL
2
PerPar0:3
External peripheral data bus byte parity.
I/O
5V tolerant
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
I
5V tolerant
3.3V LVTTL
PerR/W
Used by the PPC440GP when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to indicate
the direction of transfer.
I/O
5V tolerant
3.3V LVTTL
1, 2
PerWE
Write Enable. Low when any of the four PerWBE0:3 signals are
low.
O
5V tolerant
3.3V LVTTL
2
50
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description
(Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Notes
Description
I/O
Type
BusReq
Bus Request. Used when the PPC440GP needs to regain control
of peripheral interface from an external master.
O
5V tolerant
3.3V LVTTL
ExtAck
External Acknowledgement. Used by the PPC440GP to indicate
that a data transfer occurred.
O
5V tolerant
3.3V LVTTL
ExtReq
External Request. Used by an external master to indicate it is
prepared to transfer data.
I
5V tolerant
3.3V LVTTL
ExtReset
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
HoldAck
Hold Acknowledge. Used by the PPC440GP to transfer ownership
of peripheral bus to an external master.
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request. Used by an external master to request ownership
of the peripheral bus.
I
5V tolerant
3.3V LVTTL
PerClk
Peripheral Clock. Used by an external master and by synchronous
peripheral slaves.
O
5V tolerant
3.3V LVTTL
PerErr
External Error. Used as an input to record external master errors
and external slave peripheral errors.
I/O
5V tolerant
3.3V LVTTL
1, 5
UARTSerClk
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory. This input can
be individually connected to either or both UART0 and UART1.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Rx
UART0 Receive data.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Tx
UART0 Transmit data.
O
5V tolerant
3.3V LVTTL
4
UART0_DCD
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
6
UART0_DSR
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
6
UART0_CTS
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_DTR
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
4
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
4
UART0_RI
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL
1, 4
UART1_Rx
UART1 Receive data.
I/O
5V tolerant
3.3V LVTTL
1, 4
UART1_Tx
UART1 Transmit data.
I/O
5V tolerant
3.3V LVTTL
1, 4
UART1_DSR/CTS
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
I/O
5V tolerant
3.3V LVTTL
1, 4
External Master Peripheral Interface
1, 4
1, 5
UART Peripheral Interface
AMCC
51
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signal Functional Description
(Sheet 5 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Description
I/O
Type
Notes
UART1 Request To Send or Data Terminal Ready. The choice is
determined by a DCR register bit setting.
I/O
5V tolerant
3.3V LVTTL
1, 4
IIC0SClk
IIC0 Serial Clock.
I/O
5V tolerant
3.3V LVTTL
1, 2
IIC0SDA
IIC0 Serial Data.
I/O
5V tolerant
3.3V LVTTL
1, 2
IIC1SClk
IIC1 Serial Clock.
I/O
5V tolerant
3.3V LVTTL
1, 2
IIC1SDA
IIC1 Serial Data.
I/O
5V tolerant
3.3V LVTTL
1, 2
1, 5
Signal Name
UART1_RTS/DTR
IIC Peripheral Interface
Interrupts Interface
IRQ00:10
External interrupt Requests 0 through 10.
I
5V tolerant
3.3V LVTTL
IRQ11:12
External interrupt Requests 11 through 12.
I
3.3V PCI
TCK
Test Clock.
I
3.3V CMOS
w/pull-up
1
TDI
Test Data In.
I
3.3V CMOS
w/pull-up
4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V CMOS
w/pull-up
1
TRST
Test Reset. During chip power-up, this signal must be low from the
start of VDD ramp-up until at least 16 SysClk cycles after VDD is
stable in order to initialize the JTAG controller.
I
3.3V CMOS
w/pull-up
5
JTAG Interface
52
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description
(Sheet 6 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Clock
5V tolerant
3.3V LVTTL
Notes
System Interface
SysClk
Main system clock input.
SysErr
Set to 1 when a machine check is generated.
O
5V tolerant
3.3V LVTTL
SysReset
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. The signal is implemented
as an open-drain output (two states; 0 or open circuit).
During chip power-up, this signal must be low from the start of VDD
ramp-up until at least 16 SysClk cycles after VDD is stable.
I/O
5V tolerant
3.3V LVTTL
TmrClk
Processor timer external input clock.
I
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
GPIO00:31
General purpose I/O 0 through 10. To access these functions,
software must set DCR register bits.
I/O
5V tolerant
3.3V LVTTL
TestEn
Test Enable.
I
1.8V CMOS
w/pull-down
RcvrInh
Receiver Inhibit. Active only when TestEn is active.
I
5V tolerant
3.3V LVTTL
RefVEn
Reference Voltage Enable. Do not connect for normal operation.
Pull up for Boundary Scan Description Language (BSDL) testing.
I
1.8V CMOS
w/pull-down
DrvrInh1:2
Driver Inhibit. Used for test purposes only. Tie up for normal
operation
I
5V tolerant
3.3V LVTTL
AMCC
1, 2
1, 4
3
2
53
440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Signal Functional Description
(Sheet 7 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Trace Interface
TrcBS0:2
Trace branch execution status.
I/O
5V tolerant
3.3V LVTTL
TrcClk
Trace data capture clock, runs at 1/4 the frequency of the
processor.
O
5V tolerant
3.3V LVTTL
TrcES0:4
Trace Execution Status is presented every fourth processor clock
cycle.
I/O
5V tolerant
3.3V LVTTL
TrcTS0:6
Additional information on trace execution and branch status.
I/O
5V tolerant
3.3V LVTTL
AGND
PLL (analog) voltage ground.
na
na
GND
Ground.
na
na
AxVDD
1.8V—Filtered voltages input for PLLs (analog circuits)
Note: A separate filter for each of the three voltages is
recommended.
na
na
OVDD
3.3V supply—I/O (except DDR SDRAM)
na
na
SVDD
2.5V supply—DDR SDRAM
na
na
VDD
1.8V supply—Logic voltage.
na
na
Do not connect signals, voltage, or ground to these balls.
na
na
Power Pins
Reserved Pins
Reserved
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Symbol
Value
Unit
VDD
0 to +1.95
V
Supply Voltage (I/O Interface, except DDR SDRAM)
OVDD
0 to +3.6
V
PLL Supply Voltages
AxVDD
0 to +1.95
V
Supply Voltage (DDR SDRAM Logic)
SVDD
0 to +2.7
V
Input Voltage (3.3V LVTTL receivers)
VIN
0 to +3.6
V
Input Voltage (5.0V LVTTL receivers)
VIN
0 to +5.5
V
Storage Temperature Range
TSTG
-55 to +150
°C
Case Temperature under bias
TC
-40 to +120
°C
Supply Voltage (Internal Logic)
Notes
1
2
Notes:
1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440GP. A separate filter, as shown below, is recommended for each voltage:
AxVDD
VDD
L
C
L – SMT ferrite bead chip, Murata BLM31A700S or equivalent.
C – 0.1 μF ceramic
2. This value is not a specification of the operational temperature range; it is a stress rating only.
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Package Thermal Specifications
Thermal resistance values for the CBGA and PBGA packages in a convection environment are as follows:
Parameter
Junction-to-case thermal resistance
Symbol
θJC
Case-to-ambient thermal resistance (w/o heat
sink)
θCA
Junction-to-ball (typical)
θJB
Airflow
ft/min (m/sec)
Package
Unit
Notes
<0.1
°C/W
1
1.2
1.2
°C/W
1, 3
17.7
16.3
°C/W
2
°C/W
2, 3
0 (0)
100 (0.51)
200 (1.02)
Ceramic
<0.1
<0.1
Plastic
1.2
Ceramic
18.9
Plastic
20.8
Ceramic
Plastic
°C/W
8.0
°C/W
3
Notes:
1. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
2. The case-to-ambient thermal resistance is measured in a JEDEC JESD51-6 standard environment; and may not accurately predict
thermal performance in production equipment environments. The operational case temperature must be maintained.
3. Modeled on standard JEDEC 2S2P card, 50x50mm
56
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Heat Sink Mounting Information (Ceramic Package Only)
Proper thermal design is primarily dependent upon multiple system-level effects; that is, the effects of the heat
sink, the air flow, and the thermal interface material. To reduce the die-junction temperature, heat sinks may be
attached to the package by several methods: adhesive, spring clips to the printed-circuit board or package, or a
mounting clip and screw assembly. When attaching heat sinks, it is important to avoid placing excessive
mechanical stress on bonding of the chip to the substrate and the package to the board.
Heat Sink Attached With Spring Clip
Heat sink
Heat sink
Heat sink clip
Heat sink clip
Thermal grease
Thermal grease
CBGA
package
CBGA
package
Printed
circuit
board
Printed
circuit
board
Spring clip to board
Spring clip to package
Static compression (spring force)—2.27kg maximum
Static compression (spring force)—2.27kg maximum1
Note 1: Force is limited by allowable compression on the die.
Allowable package compression force is 4.4kg.
Heat Sink Attached With Adhesive
Heat sink
Adhesive
Printed
circuit
board
CBGA
package
CBGA
package
Printed
circuit
board
Adhesive
Heat sink
Weight
force
Weight
force
Heat sink weight force—60g maximum
Important: All of the guidelines indicated in the above diagrams must be evaluated and adjusted to account for the
shock and vibration effects of any particular application.
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
VDD
+1.7
+1.8
+1.9
V
4
I/O Supply Voltage
OVDD
+3.0
+3.3
+3.6
V
4
DDR SDRAM Supply Voltage (DDR clock up to 166MHz)
SVDD
+2.3
+2.5
+2.7
V
4
PLL Supply Voltages
AxVDD
+1.65
+1.8
+1.95
V
3
DDR SDRAM Reference Voltage
SVREF
+1.15
+1.25
+1.35
V
3
SVREF+0.18
SVDD+0.3
V
2
0.5OVDD
OVDD+0.5
V
1
Input Logic High (3.3V LVTTL, 5V tolerant receiver)
+2.0
+5.5
V
Input Logic Low (2.5V SSTL)
-0.3
SVREF-0.18
V
-0.5
0.35OVDD
V
0
+0.8
V
+1.95
SVDD
V
0.9OVDD
OVDD
V
+2.4
OVDD
V
0
0.55
V
0.1OVDD
V
0
+0.4
V
Logic Supply Voltage
Input Logic High (2.5V SSTL)
Input Logic High (3.3V PCI-X)
VIH
Input Logic Low (3.3V PCI-X)
VIL
Input Logic Low (3.3V LVTTL, 5V tolerant receiver)
Output Logic High (2.5V SSTL)
Output Logic High (3.3V PCI-X)
VOH
Output Logic High (3.3V LVTTL, 5V tolerant receiver)
Output Logic Low (2.5V SSTL)
Output Logic Low (3.3V PCI-X)
VOL
Output Logic Low (3.3V LVTTL, 5V tolerant receiver)
58
1
1
1
Input Leakage Current (No pull-up or pull-down)
IIL1
0
0
μA
Input Leakage Current for Pull-Down
IIL2
0 (LPDL)
200 (MPUL)
μA
5
Input Leakage Current for Pull-Up
IIL3
-150 (LPDL)
0 (MPUL)
μA
5
+5.5
V
Input Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
VIMAO
Input Max Allowable Undershoot (3.3V LVTTL, 5V tolerant
receiver)
VIMAU
Output Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
VOMAO
Output Max Allowable Undershoot (3.3V LVTTL,
5V tolerant receiver)
VOMAU3
-0.6
V
+5.5
-0.6
V
V
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Recommended DC Operating Conditions
(Continued)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Case Temperature rating for C package
TC
Case Temperature rating E for C package
Case Temperature rating E for F package
Typical
Maximum
Unit
Notes
-40
+85
°C
6
TC
-40
+105
°C
6
TC
-40
+100
°C
6
Notes:
1. PCI-X drivers meet PCI-X specifications.
2. SVREF = SVDD/2
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440GP. See “Absolute Maximum Ratings” on page 55.
4. During chip power-up, OVDD should begin to ramp before VDD. External voltage should not be applied to the chip I/O pins before
OVDD is applied to the chip. A power-down cycle should complete (OVDD and VDD should both be below 0.4V) before a new powerup cycle is started.
5. LPDL is least positive down level; MPUL is most positive up level.
6. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
Input Capacitance
Parameter
Symbol
Maximum
Unit
Group 1 (2.5V SSTL I/O)
CIN1
12
pF
Group 2 (5V tolerant LVTTL I/O)
CIN2
12
pF
Group 3 (PCI-X I/O)
CIN3
12
pF
Group 4 (Receivers)
CIN4
9
pF
Notes
DC Power Supply Loads
Parameter
VDD (1.8V) active operating current
Symbol
Minimum
Typical
Maximum
Unit
Notes
IDD
915
mA
2
OVDD (3.3V) active operating current
IODD
125
mA
2
SVDD (2.5V) active operating current
ISDD
560
mA
2
AxVDD (1.8 V) input current
IADD
33
mA
1, 2
Notes:
1. See “Absolute Maximum Ratings” on page 55 for filter recommendations.
2. The current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors including
the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the
power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and power are primarily
dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OVDD (I/O) current and
power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Test Conditions
Clock timing and switching characteristics are specified in accordance with operating
conditions shown in the table “Recommended DC Operating Conditions.” AC
specifications are characterized with VDD = 1.8V, TC = rated temperature and a 50pF
test load as shown in the figure to the right.
Output
Pin
C
50pF
Clocking Specifications
Symbol
Parameter
Minimum
Maximum
Units
33.33
66.66
MHz
Notes
SysClk Input
FC
Frequency
TC
Period
15
30
ns
TCS
Edge stability (cycle-to-cycle jitter)
–
±0.15
ns
TCH
High time
40% of nominal period
60% of nominal period
ns
TCL
Low time
40% of nominal period
60% of nominal period
ns
500
1000
MHz
1
2
ns
Note: Input slew rate ≥ 1V/ns
PLL VCO
FC
Frequency
TC
Period
Processor Clock (CPU Clock)
FC
Frequency
–
500
MHz
TC
Period
2
–
ns
1
MemClkOut
FC
Frequency
100
133.33
MHz
TC
Period
7.5
10
ns
TCH
High time
35% of nominal period
65% of nominal period
ns
Notes:
1. The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information”
on page 4).
Timing Waveform
2.0V
1.5V
0.8V
TCH
TCL
TC
60
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440GP. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC440GP the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC440GP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed 40kHz.
In some cases, on-board PPC440GP peripherals impose more stringent requirements.
• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
modulation.
• Use the DDR SDRAM MemClkOut since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Important: It is up to the system designer to ensure that any SSCG used with the PPC440GP meets the above
requirements and does not adversely affect other aspects of the system.
AMCC
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440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
Notes
–
133.33
MHz
2
7.5
–
ns
PCIXClk input high time
40% of nominal period
60% of nominal period
ns
PCIXClk input low time
40% of nominal period
60% of nominal period
ns
–
2.5
MHz
EMCMDClk period
400
–
ns
EMCMDClk output high time
160
–
ns
EMCMDClk output low time
160
–
ns
EMCTxClk input frequency MII(RMII)
2.5(5)
25(50)
MHz
EMCTxClk period MII(RMII)
40(20)
400(200)
ns
EMCTxClk input high time
35% of nominal period
–
ns
EMCTxClk input low time
35% of nominal period
–
ns
EMCRxClk input frequency MII(RMII)
2.5(5)
25(50)
MHz
EMCRxClk period MII(RMII)
40(20)
400(200)
ns
EMCRxClk input high time
35% of nominal period
–
ns
EMCRxClk input low time
35% of nominal period
–
ns
EMCRefClk input frequency
–
50
MHz
EMCRefClk period
20
PCIXClk input frequency (asynchronous mode)
PCIXClk period (asynchronous mode)
EMCMDClk output frequency
EMCRefClk input high time
45% of nominal period
55% of nominal period
ns
EMCRefClk input low time
45% of nominal period
55% of nominal period
ns
PerClk output frequency (for ext. master or sync. slaves)
–
66.66
MHz
PerClk period
15
–
ns
PerClk output high time
50% of nominal period
66% of nominal period
ns
PerClk output low time
33% of nominal period
50% of nominal period
ns
–
1000/(2TOPB1+2ns)
MHz
1
UARTSerClk period
2TOPB+2
–
ns
1
UARTSerClk input high time
TOPB+1
–
ns
1
UARTSerClk input low time
TOPB+1
–
ns
1
UARTSerClk input frequency
62
ns
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Peripheral Interface Clock Timings (Continued)
Parameter
Min
Max
Units
TmrClk input frequency
–
100
MHz
TmrClk period
10
–
ns
TmrClk input high time
40% of nominal period
60% of nominal period
ns
TmrClk input low time
40% of nominal period
60% of nominal period
ns
Notes
Notes:
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2the frequency of the PLB clock. The maximum OPB clock frequency is 66.66 MHz.
2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz.
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Input Setup and Hold Waveform
Clock
TIS min
TIH min
Inputs
Valid
Output Delay and Float Timing Waveform
Clock
Outputs
TOV max
TOV max
TOV max
TOH min
TOH min
TOH min
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
64
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds
(Sheet 1 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
Input (ns)
Signal
Output (ns)
Output Current (mA)
Clock
Notes
1.5
PCIXClk
2
0.5
1.5
PCIXClk
2
0.7 (Note 2)
0.5
1.5
PCIXClk
2
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
na
na
dc
dc
0.5
1.5
PCIXClk
async
PCIXIRDY
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXTRDY
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXStop
Note 2 (3
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXDevSel
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXIDSel
Note 2 (3)
0.5 (0)
na
na
na
na
PCIXClk
2
PCIXPErr
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXSErr
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXClk
dc
dc
na
na
na
na
PCIXReset
na
na
na
na
na
na
PCIXClk
PCIXReq64
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXAck64
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
PCIXCap
Note 2 (3)
0.5 (0)
na
na
na
na
PCIXClk
2
3.8
0.7
0.5
1.5
PCIXClk
2
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
PCIXAD00:63
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
0.5
PCIXC3:0[BE3:0]
Note 2 (3)
0.5 (0)
3.8 (6)
0.7 (Note 2)
PCIXParLow
Note 2 (3)
0.5 (0)
3.8 (6)
PCIParHigh
Note 2 (3)
0.5 (0)
PCIXFrame
Note 2 (3)
PCI-X Interface
PCIXINT
PCIX133Cap
async
PCIXM66En
Note 2 (3)
0.5 (0)
na
na
na
na
PCIXClk
2
PCIXReq0:5
Note 2 (3)
0.5 (0)
na
na
na
na
PCIXClk
2
PCIXGnt0:5
na)
na
3.8 (6)
0.7 (Note 2)
0.5
1.5
PCIXClk
2
AMCC
65
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds
(Sheet 2 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
Input (ns)
Signal
Output (ns)
Output Current (mA)
Clock
Notes
n/a
EMCRxClk
1
n/a
n/a
EMCRxClk
1
na
n/a
n/a
na
na
n/a
n/a
EMCRxClk
1
na
15
2
10.3
7.1
EMCTxClk
1
na
na
15
2
10.3
7.1
EMCTxClk
1
EMCTxClk
na
na
na
na
na
na
EMCTxErr
na
na
15
2
10.3
7.1
EMCCrS
na
na
n/a
n/a
1,
async
EMCCD
na
na
n/a
n/a
1,
async
10.3
7.1
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
EMCRxD0:3
4
1
na
na
n/a
EMCRxDV
4
1
na
na
EMCRxClk
na
na
na
EMCRxErr
4
1
EMCTxD0:3
na
EMCTxEn
Ethernet MII Interface
EMCMDIO
EMCMDClk
1,
async
1,
async
EMCTxClk
EMCMDClk
1
1
1,
async
na
na
na
na
10.3
7.1
EMC0RxD0:1
2
1
na
na
n/a
n/a
EMCRxClk
EMC0RxErr
2
1
na
na
n/a
n/a
EMCRxClk
na
na
n/a
n/a
EMCRxClk
Ethernet RMII Interface
EMC0CrSDV
EMC0TxD0:1
na
na
11
2
10.3
7.1
EMCTxClk
EMC0:1TxEn
na
na
11
2
10.3
7.1
EMCTxClk
EMC1RxD0:1
na
na
10.3
7.1
EMCRxClk
EMC1RxErr
na
na
n/a
n/a
EMCRxClk
EMC1CrSDV
na
na
n/a
n/a
EMCRxClk
EMCTxClk
EMC1TxD0:1
na
na
11
2
10.3
7.1
EMCRefClk
na
na
na
na
10.3
7.1
66
3,
async
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds
(Sheet 3 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
Input (ns)
Signal
Setup Time
(TIS min)
Output (ns)
Output Current (mA)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
na
na
na
15.3
10.2
15.3
10.2
Clock
Notes
Internal Peripheral Interface
IICxSClk
na
IICxSDA
UARTSerClk
na
na
UART0_Rx
UART0_Tx
na
na
na
na
na
na
na
na
na
10.3
7.1
na
UART0_DCD
na
na
na
na
UART0_DSR
na
na
na
na
UART0_CTS
na
na
na
na
10.3
7.1
na
na
10.3
7.1
na
na
10.3
7.1
na
na
10.3
7.1
na
na
TDI
na
na
async
TMS
na
na
async
TDO
15.3
10.2
async
TCK
na
na
async
TRST
na
na
async
UART0_DTR
na
na
UART0_RI
UART0_RTS
na
na
na
UART1_Rx
UART1_Tx
na
na
na
na
na
na
UART1_DSR/CTS
UART1_RTS/DTR
na
na
na
Interrupts Interface
IRQ00:12
JTAG Interface
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds
(Sheet 4 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
Input (ns)
Signal
Setup Time
(TIS min)
Output (ns)
Hold Time
(TIH min)
Output Current (mA)
Clock
Notes
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
SysClk
na
na
na
na
TmrClk
na
na
na
na
async
na
na
async
na
na
async
10.3
7.1
async
async
System Interface
SysReset
Halt
SysErr
na
na
na
na
TestEn
na
na
na
na
DrvrInh1:2
na
na
na
na
10.3
7.1
10.3
7.1
TrcBS0:2
10.3
7.1
TrcES0:4
10.3
7.1
TrcTS0:6
10.3
7.1
GPIO00:31
Trace Interface
TrcClk
68
na
na
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—400, 466, and 500MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Signal
Setup
Time
(TIS min)
Output (ns)
Output Current (mA)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Clock
Notes
External Slave Peripheral Interface
PerData00:31
3
1
9
0
15.3
10.2
PerClk
PerAddr00:31
3
1
7.6
0
15.3
10.2
PerClk
PerPar0:3
4
1
8.4
0
15.3
10.2
PerClk
PerWBE0:3
2.5
1
6.5
0
15.3
10.2
PerClk
PerCS0:7
na
na
6
0
15.3
10.2
PerClk
PerOE
na
na
6
0
15.3
10.2
PerClk
PerWE
na
na
7
0
15.3
10.2
PerBLast
2.5
1
5
na
15.3
10.2
PerClk
5
1
na
na
na
na
PerClk
PerR/W
2.5
1
5.6
na
15.3
10.2
PerClk
DMAReq0:3
dc
dc
na
na
na
na
PerClk
DMAAck0:3
na
na
7
0
15.3
10.2
PerClk
EOT0:3/TC0:3
dc
dc
6.8
0
15.3
10.2
PerClk
PerReady[RcvrInh]
External Master Peripheral Interface
PerClk
na
na
na
na
15.3
10.2
PLB Clk
ExtReset
na
na
6.2
0
15.3
10.2
PerClk
HoldReq
3.5
1
na
na
na
na
PerClk
HoldAck
na
na
6.4
0
15.3
10.2
PerClk
ExtReq
2.5
1
na
na
na
na
PerClk
ExtAck
na
na
6.2
0
15.3
10.2
PerClk
BusReq
na
na
6.2
0
15.3
10.2
PerClk
PerErr
4.5
1
na
na
15.3
10.2
PerClk
AMCC
1
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM I/O Specifications
The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific application and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM
controller chapter in the PowerPC 440GP User’s Manual).
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and
MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0 by 90°
creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to
MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.
The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.
Values are calculated over best case and worst case processes with speed, temperature, and voltage as follows:
Best Case = Fast process, -40°C, +1.9V
Worst Case = Slow process, +85°C, +1.7V
Note: In all the following DDR tables and timing diagrams, the maximum values are measured under worst case
conditions. The minimum values (best case) are estimates based on comparable timing in a similar chip of a different technology.
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.
DDR SDRAM Simulation Signal Termination Model
MemClkOut0
10pF
120Ω
10pF
MemClkOut0
VTT = SVDD/2
PPC440GP
50Ω
Addr/Ctrl/Data/DQS
10pF
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM Output Driver Specifications
Output Current (mA)
Signal Path
I/O H (maximum)
I/O L (minimum)
MemData00:07
15.2
15.2
MemData08:15
15.2
15.2
MemData16:23
15.2
15.2
MemData24:31
15.2
15.2
MemData32:39
15.2
15.2
MemData40:47
15.2
15.2
MemData48:55
15.2
15.2
MemData56:63
15.2
15.2
ECC0:7
15.2
15.2
DM0:8
15.2
15.2
MemClkOut0
15.2
15.2
MemAddr00:12
15.2
15.2
BA0:1
15.2
15.2
RAS
15.2
15.2
CAS
15.2
15.2
WE
15.2
15.2
BankSel0:3
15.2
15.2
ClkEn0:3
15.2
15.2
DQS0:8
15.2
15.2
Write Data
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut0
MemClkOut0(90)
TSA
Addr/Cmd
TDS
TSK
TDS
THA
DQS
TSD
TSD
MemData
THD
THD
TSK = Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
TSA = Setup time for address and command signals to MemClkOut0(90)
THA = Hold time for address and command signals from MemClkOut0(90)
TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Timing—DDR SDRAM TDS
Notes:
1. All of the DQS signals are referenced to MemClkOut0(0).
2. The TDS values in the table include 3/4 of a cycle at the indicated clock speed.
3. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle
time for the lower clock frequency (TDS - 5.625 + 0.75TCYC).
TDS (ns)
Clock Speed (MHz)
Signal Name
Minimum
Maximum
133
DQS0
na
6.25
133
DQS1
na
6.25
133
DQS2
na
6.25
133
DQS3
na
6.25
133
DQS4
na
6.25
133
DQS5
na
6.25
133
DQS6
na
6.25
133
DQS7
na
6.25
133
DQS8
na
6.25
I/O Timing—DDR SDRAM TSK, TSA, and THA
Notes:
1. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).
2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and
subtract TSK maximum (0.75TCYC - TSKmax).
3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
TSK minimum (0.25TCYC + TSKmin).
TSK (ns)
Clock Speed (MHz)
AMCC
TSA (ns)
THA (ns)
Signal Name
Minimum
Maximum
Minimum
Minimum
133
MemAddr00:12
0.4
1.2
4.425
2.275
133
BA0:1
0.4
1.2
4.425
2.275
133
BankSel0:3
0.4
1.2
4.425
2.275
133
ClkEn0:3
0.4
1.2
4.425
2.275
133
CAS
0.4
1.2
4.425
2.275
133
RAS
0.4
1.2
4.425
2.275
133
WE
0.4
1.2
4.425
2.275
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440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
I/O Timing—DDR SDRAM TSD and THD
Notes:
1. TSD and THD are measured under worst case conditions.
2. The time values in the table include 1/4 of a cycle at the indicated clock speed.
3. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and add
1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.875 + 0.25TCYC).
Clock Speed (MHz)
Signal Names
Reference Signal
TSD (ns)
THD (ns)
133
MemData00:07, DM0
DQS0
1.375
1.375
133
MemData08:15, DM1
DQS1
1.375
1.375
133
MemData16:23, DM2
DQS2
1.375
1.375
133
MemData24:31, DM3
DQS3
1.375
1.375
133
MemData32:39, DM4
DQS4
1.375
1.375
133
MemData40:47, DM5
DQS5
1.375
1.375
133
MemData48:55, DM6
DQS6
1.375
1.375
133
MemData56:63, DM7
DQS7
1.375
1.375
133
ECC0:7, DM8
DQS8
1.375
1.375
DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (TMD) is provided.
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the
PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be
programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set
in RDCT. The delay of Read Clock relative to the PLB clock (TRD) shown below assumes the programmable Read
Clock delay is set to zero.
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
MemClkOut0(0)
TMD
TMDmin = 850ps
TMDmax = 2600ps
Read Clock
TRD
TRDmin = 0ps
TRDmax = 300ps
In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
Mux
Package pins
RDSP
Q
D
Stage 1
D
Data
FF,
XL
DQS
Q
D
FF
C
C
1/4
Cycle
Delay
Stage 3
Stage 2
Q
Programmed
Read Clock
Delay
ECC
D
FF
Q
FF
PLB bus
C
C
Read Select
(SDRAM0_TR1)
PLB Clock
FF Timing:
TIS = Input setup time = 0.2ns
TIH = Input hold time = 0.1ns
TP = Propagation delay (D to Q or C to Q) = 0.6ns maximum
AMCC
FF: Flip-Flop
XL: Transparent Latch
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Timing—DDR SDRAM TSIN and TDIN
Notes:
1. TSIN = Delay from DQS at package pin to C on Stage 1 FF.
2. TDIN = Delay from data at package pin to D on Stage 1 FF.
3. The time values for TSIN include 1/4 of a cycle at the indicated clock speed.
Clock Speed (MHz)
Signal Name
TSIN (ns)
minimum
TSIN (ns)
maximum
Signal Name
TDIN (ns)
minimum
TDIN (ns)
maximum
133
DQS0
2.775
3.775
MemData00:07
1.0
2.0
133
DQS1
2.775
3.775
MemData08:15
1.0
2.0
133
DQS2
2.775
3.775
MemData16:23
1.0
2.0
133
DQS3
2.775
3.775
MemData24:31
1.0
2.0
133
DQS4
2.775
3.775
MemData32:39
1.0
2.0
133
DQS5
2.775
3.775
MemData40:47
1.0
2.0
133
DQS6
2.775
3.775
MemData48:55
1.0
2.0
133
DQS7
2.775
3.775
MemData56:63
1.0
2.0
133
DQS8
2.775
3.775
ECC0:7
1.0
2.0
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically
close to the PPC440GP, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary
to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example
TT = 1.5ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 1
DQS at pin
Data at pin
D0
D1
D3
D2
TSIN
DQS Stage 1 C
Data in Stage 1 D
D0
D1
TDIN
D3
D2
TP
TP
High
D0
D2
Data out Stage 1
Low
Data in at RDSP
with no ECC
D0
High
Low
D2
D1
D3
D0
D2
D2
D1
D0
D3
TT
PLB Clock
Data out RDSP
High
D0
D2
Low
D1
D3
(1)
TSIN = Delay from DQS at package pin to C on Stage 1 FF.
TP = Propagation delay through FFs
TDIN = Delay from data at package pin to D on Stage 1 FF.
TT = Propagation delay, Stage 1 input to RDSP input w/o ECC
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 2:
In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC
is enabled, Stage 3 data must be sampled (see Example 3). In this example, TT = 1.5ns and TTE = 4.3ns at worst
case conditions.
DDR SDRAM Read Cycle Timing—Example 2
DQS at pin
Data at pin
DQS Stage 1 C
D0
D1
D3
D2
TSIN
Data in Stage 1 D
D0
D1
D3
D2
TDIN
TP
High
D0
D2
Data out Stage 1
Low
D0
D1
D2
D3
PLB Clock
Read Clock Delayed
TP
Data out Stage 2
Data in at RDSP
without ECC
High
D0
D2
Low
D1
D3
High
D0
D2
Low
D1
D3
TT
TTE
Data in at RDSP
with ECC
Data out at RDSP
without ECC
High
D0
D2
Low
D1
D3
High
D0
D2
Low
D1
D3
(2)
TT = Propagation delay from Stage 2 input to RDSP input w/o ECC
TTE = Propagation delay from Stage 2 input to RDSP input with ECC
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. Again, TT = 1.5ns and TTE =
4.3ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 3
DQS at pin
Data at pin
DQS Stage 1 C
D0
D1
D3
D2
TSIN
Data in Stage 1 D
D0
D1
D3
D2
TDIN
TP
High
D0
D2
Data out Stage 1
Low
D0
D1
D2
D3
PLB Clock
Read Clock Delayed
TP
Data out Stage 2
Data out Stage 3
with ECC
High
D0
D2
Low
D1
D3
High
D0
D2
Low
D1
D3
TTE
Data in at RDSP
with ECC
Data out RDSP
with ECC
High
D0
D2
Low
D1
D3
High
D0
D2
Low
D1
D3
(3)
TT = Propagation delay from Stage 2 input to RDSP input w/o ECC
TTE = Propagation delay from Stage 2 input to RDSP input with ECC
AMCC
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440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Initialization
The PPC440GP provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GP start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. They are used for strap functions only during reset. Following
reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Strapping Pin Assignments
Function
Option
Ball Strapping
V24
(UART0_DCD)
Bootstrap controller
Disabled
0
Enabled
1
V02
(UART0_DSR)
IIC0 slave address that will respond with boot data
0x54
0
0x50
1
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GP
sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SYS0and SYS1 registers
accordingly. Otherwise, the default values set in the STRP0 and STRP1 registers are used for initialization.
The initialization settings and their default values are covered in detail in the PowerPC 440GP Embedded
Processor User’s Manual.
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Revision Log
Date
Contents of Modification
08/07/2002
Add revision log.
08/30/2002
Change EMC0:1TxD0:1 and EMC0:1TxEn TOV from 15 to 11 ns.
09/11/2002
Update for 466 and 500 MHz parts
10/22/2002
Add heat sink mounting information and additional part numbers for E temperature range.
11/20/2002
Update I/O timing data.
01/07/2003
Update PCI-X I/O voltage specification.
01/22/2003
Correct description of SysReset signal.
03/25/2003
Update DDR SDRAM timing.
06/16/2003
Change PCI setup specification from 2 to 3ns.
08/22/2003
Remove references to 2xPLB in DDR SDRAM timing section.
01/21/2004
Update DDR SDRAM timing section to be consistent 440GX presentation.
02/12/2004
Restore VDD/OVDD voltage sequence restriction.
05/12/2004
Add plastic package data and update part number list.
07/8/2004
Update supported part numbers.
11/01/2004
Add information on minimum SysClk and TRST duration during power-on reset.
Remove power sequence restrictions note from Absolute Maximum Rating table.
Restate power sequencing restrictions in Recommended DC Operating Conditions table.
Convert to AMCC format.
12/09/2004
Remove references to Ethernet SMII mode.
06/07/2005
Add reduced-lead part numbers.
10/17/2005
Clarify DDR SDRAM interface diagram.
11/07/2005
Remove metal-layer specification from technology description.
Add logo and number nomenclature to package drawing.
08/30/2007
Change the technical support telephone and fax number.
AMCC
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440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Printed in the United States of America, Thursday, October 04, 2007
The following are trademarks of AMCC in the United States, or other countries, or both:
AMCC
Other company, product, and service names may be trademarks or service marks of others.
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under the intellectual property rights of AMCC or third parties.
Without limiting the generality of the foregoing, any performance data contained in this document was
determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore,
the results obtained in other operating environments may vary significantly. Under no circumstances will
AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or the
information contained herein.
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Applied Micro Circuits Corporation
215 Moffett Park Drive, Sunnyvale, CA 94089
Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601
http://www.amcc.com
AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data
sheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under
its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower
grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2007 Applied Micro Circuits Corporation.
AMCC
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