ETC IBM25PPC405CR

PowerPC 405CR Embedded Controller Data Sheet
Features
• IBM PowerPCTM 405 32-bit RISC processor
core operating up to 266MHz
• DMA support for external peripherals, internal
UART and memory
- Memory Management Unit
- Scatter-gather chaining supported
- 16KB instruction and 8KB data caches
- Four channels
- Multiply-Accumulate (MAC) function,
including fast multiply unit
- Programmable Timers
- Supports JTAG for board level testing
• Programmable Interrupt Controller supports
interrupts from a variety of sources
- Supports 7 external and 10 internal
interrupts
- Edge triggered or level-sensitive
• PC-100 Synchronous DRAM (SDRAM)
interface operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• External Peripheral Bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
- Positive or negative active
- Non-critical or critical interrupt to processor
core
- Programmable critical interrupt priority
ordering
- Programmable critical interrupt vector for
faster vector processing
• Two serial ports (16550 compatible UART)
- Up to eight devices
• One IIC (I2C) interface
- External Mastering supported
• General Purpose I/O (GPIO) available
• Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
Description
The IBM PowerPC 405CRTM is a 32-bit RISC
embedded controller. High performance, peripheral
integration, and low cost make the device ideal for
wired communications, network printers, and other
computing applications.
This device is an easy upgrade for systems based
on PowerPC 403xx embedded processors, while
providing a base for custom chip designs.
The controller is powered by a PPC405 embedded
core. This core tightly couples a 266-MHz CPU,
MMU, I- and D-cache, and debug logic. Fine-tuning
of the core reduces data transfer overhead,
minimizes pipeline stalls, and greatly improves
performance.
The PPC405CR employs the IBM CoreConnectTM
bus architecture. This architecture, as implemented
on the PPC405CR, consists of a 64-bit, 100-MHz
Processor Local Bus (PLB) and a 32-bit, 50-MHz
On-Chip Peripheral Bus (OPB).High-performance
peripherals attach to the PLB; and less
performance-critical peripherals attach to the OPB.
Technology: IBM CMOS SA12E 0.25 µm
(0.18 µm Leff)
Package: 27mm, 316-ball enhanced plastic ball grid
array (E-PBGA)
Power (estimated): Typical 0.9W, Maximum 2.0W
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
1
PowerPC 405CR Embedded Controller Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figures
PPC405CR Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
27mm, 316-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
PowerPC 405CR Embedded Controller Data Sheet
Tables
SysMem Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SysClk and MemClk Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I/O Specifications—All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I/O Specifications—200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I/O Specifications—266MHz (Preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3
PowerPC 405CR Embedded Controller Data Sheet
Ordering and PVR Information
Product Name
Order Part Number1
Processor
Frequency
Package
Rev
Level
PVR Value
JTAG ID
200MHz
27mm, 316 E-PBGA
C
0x40110145
0x42051049
PPC405CR
IBM25PPC405CR-3BC200C
PPC405CR
IBM25PPC405CR-3BC200CZ
200MHz
27mm, 316 E-PBGA
C
0x40110045
0x42051049
PPC405CR
IBM25PPC405CR-3BC266C
266MHz
27mm, 316 E-PBGA
C
0x40110045
0x42051049
PPC405CR
IBM25PPC405CR-3BC266CZ
266MHz
27mm, 316 E-PBGA
C
0x40110045
0x42051049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
This section provides the part numbering nomenclature for the PPC405CR. For availability, contact your local
IBM sales office.
The part number contains a part modifier. This modifier provides for identification of future enhancements (for
example, higher performance).
Each part number also contains a revision code. This refers to the die mask revision number and is specified
in the part numbering scheme for identification purposes only.
The PVR (Processor Version Register) is software accessible and contains additional information about the
revision level of the part. Refer to the PPC405CR User’s Manual for details on the register content.
IBM Part Number Key
IBM25PPC405CR-3BC200Cx
IBM Part Number
Grade 3 Reliability
Package (E-PBGA)
4
Shipping Package*
* Blank = Tray
Z
= Tape and reel
Case Temperature Range
(-40°C to +85°C)
Processor Speed
Revision Level
PowerPC 405CR Embedded Controller Data Sheet
PPC405CR Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
*Serial
Clock
MMU
PPC405
Processor Core
8KB
D-Cache
JTAG
Trace
DCU
ICU
GPIO
DCR Bus
16KB
I-Cache
IIC
UART
UART
On-chip Peripheral Bus (OPB)
Arb
DMA
Controller
(4-Channel)
OPB
Bridge
* See Peripheral Interface
Clock Timings table
Processor Local Bus (PLB)
Code
Decompression
(CodePack)
SDRAM
Controller
133MHz max
- 13-bit addr
- 32-bit data
External
Bus
Controller
External
Bus Master
Controller
66MHz max
- 32-bit addr
- 32-bit data
The PPC405CR is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
Note: IBM CoreConnect busses provide:
• 64-bit PLB interfaces up to 133MHz
• 32-bit OPB interfaces up to 66MHz
5
PowerPC 405CR Embedded Controller Data Sheet
Address Map Support
The PPC405CR incorporates two simple and separate address maps. The first is a fixed processor address
map that serves the PowerPC family of processors. This address map defines the possible contents of
various address regions which the processor can access. The second address map is for Device
Configuration Registers (DCR). This address map is accessed by software running on the PPC405CR
processor through the use of MTDCR and MFDCR commands.
SysMem Memory Address Map 4GB System Memory
Function
Sub Function
Local Memory/Peripherals1
Reserved
Internal Peripherals
Start Address
End Address
Size
00000000
7FFFFFFF
2GB
80000000
EF5FFFFF
Total
EF600000
EFFFFFFF
10MB
UART0
EF600300
EF600307
8B
Reserved
EF600308
EF6003FF
UART1
EF600400
EF600407
Reserved
EF600408
EF6004FF
IIC0
EF600500
EF60051F
Reserved
EF600520
EF6005FF
8B
32B
OPB Arbiter
EF600600
EF60063F
Reserved
EF600640
EF6006FF
GPIO Controller Registers
EF600700
EF60077F
Reserved
EF600780
EFFFFFFF
Expansion ROM2
F0000000
FFDFFFFF
254MB
ROM2
FFE00000
FFFFFFFF
2MB
Boot
64B
128B
Notes:
1. The Local Memory/Peripheral area of the memory map can be configured for SDRAM, ROM or Peripherals.
2. The Boot ROM and Expansion ROM area of the memory map are intended for use by ROM or Flash-type devices. While locating
volatile SDRAM and SRAM in this region is supported by the controller it is not recommended that these regions be used for this
purpose.
6
PowerPC 405CR Embedded Controller Data Sheet
DCR Address Map 4KB Device Configuration Register
Function
Base Address
Strap/Parameter
DCR Address Space1
Reserved
Start
Address(0:9)
End
Address(0:9)
Size
000
3FF
1KW (4KB)1
16W
000
00F
Memory Controller Registers
[0:8] = 000001000
010
011
2W
External Bus Controller Registers
[0:8] = 000001001
012
013
2W
Decompression Controller Registers
[0:8] = 000001010
014
015
2W
016
07F
106W
[0:5] = 000100
080
08F
16W
090
09F
16W
[0:6] = 000110 0
0A0
0A7
8W
0A8
0AF
8W
Clock, Control and Reset
parm=0x0B0
0B0
0B7
8W
Power Management
parm=0x0B8
0B8
0BF
8W
Interrupt Controller
parm=0x0C0
0C0
0CF
16W
0D0
0FF
48W
100
13F
64W
140
3FF
704W
Reserved
PLB Registers
Reserved
OPB Bridge Out Registers
Reserved
Reserved
DMA Controller Registers
Reserved
[0:3] = 0100
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single
32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
7
PowerPC 405CR Embedded Controller Data Sheet
SDRAM Memory Controller
The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to four logical banks. Up to
256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
• 11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
• Memory bus operates at same frequency as PLB
• 32-bit memory interface support
• Programmable address compare for each bank of memory
- 4GB of address space
• Industry standard 168-pin DIMMS are supported (some configurations)
• Up to 133MHz Memory, includes PC133 support
• 4MB to 256MB per bank
• Programmable address mapping and timing
• Auto refresh
• Page Mode Accesses with up to 4 open pages
• Sync DRAM configuration via mode set command
• Power Management (self-refresh)
• Error Checking and Correction (ECC) support
- Standard SEC/DED coverage
- Aligned nibble error detect
- Address error logging
- Mixed ECC/non-ECC banks
- Bypass mode
External Peripheral Bus Controller (EBC)
• Up to eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported
• Up to 50MHz operation
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus width support
• Latch data on Ready, Synchronous or Asynchronous
8
PowerPC 405CR Embedded Controller Data Sheet
• Programmable 2K clock time-out counter with disable for Ready
• Programmable access timing per device
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
• Peripheral Device pacing with external “Ready”
• External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
• Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Internal 32-byte data buffering capability
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
9
PowerPC 405CR Embedded Controller Data Sheet
UART
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC Bus Interface
• Compliant with Phillips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
10
PowerPC 405CR Embedded Controller Data Sheet
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses.
• All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose. Twenty-three GPIOs are multiplexed with:
- 7 of 8 chip selects
- All seven external interrupts
- All nine instruction trace pins
• Each GPIO output is separately programmable to emulate an open drain driver (i.e., drives to zero, threestated if output bit is 1).
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between
the various sources of interrupts and the local PowerPC processor.
Features include:
• Supports 7 external and 10 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to PPC405 processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
JTAG
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)
11
PowerPC 405CR Embedded Controller Data Sheet
27mm, 316-Ball E-PBGA Package
Reserved Area for Ejector Pin Mark x 4 TYP
Corner Shape is Chamferred or Rounded
Top View
Gold Gate Release
Corresponds to
A1 Ball Location
15.0 TYP
27.0 REF
7.5 TYP
27.0
C
Note: All dimensions are in mm.
0.20 C
A
0.20
Bottom View
24.13
27.0
B
0.25 C
27.0
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.35 C
1.27 TYP
Mold
Compound
Thermal Balls
PCB
Substrate
1
2
3
4
9
7
5
6
8
11 13 15 17 19
10 12 14 16 18 20
0.6 ± 0.1
2.65 MAX
0.75 ± 0.15 SOLDERBALL x 316
∅ 0.30 M C A B
∅ 0.15 M C
12
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically
Signal Name
Ball
Interface Group
Page
AVDD
E20
Power
29
BA0
BA1
J17
H18
SDRAM Interface
24
BankSel0
BankSel1
BankSel2
BankSel3
L19
N17
P17
U19
SDRAM Interface
24
BusReq
P2
External MASTER Peripheral Interface
26
CAS
K17
SDRAM Interface
24
ClkEn0
ClkEn1
J19
G20
SDRAM Interface
24
DMAAck0
DMAAck1
DMAAck2
DMAAck3
C16
B17
B16
A14
External SLAVE Peripheral Interface
24
DMAReq0
DMAReq1
DMAReq2
DMAReq3
A19
C15
B15
A8
External SLAVE Peripheral Interface
24
DQM0
DQM1
DQM2
DQM3
U18
W14
Y10
U8
SDRAM Interface
24
DQMCB
V19
SDRAM Interface
24
DrvrInh1
DrvrInh2
F17
C19
System Interface
28
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
V17
Y18
U14
V13
Y13
V12
W11
V11
SDRAM Interface
24
EOT0[TC0]
EOT1[TC1]
EOT2[TC2]
EOT3[TC3]
G4
F2
W1
Y2
External SLAVE Peripheral Interface
24
ExtAck
ExtReq
ExtReset
U5
Y3
P4
External MASTER Peripheral Interface
26
13
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name
GND
14
Ball
A1
A6
A10
A15
A20
B2
B19
C3
C18
D4
D17
E5
E10
E11
E16
F1
F20
J9
J10
J11
J12
K5
K9
K10
K11
K12
K16
K20
L1
L5
L9
L10
L11
L12
L16
M9
M10
M11
M12
R1
R20
Interface Group
Power
Page
29
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name
Ball
Interface Group
Page
GND (cont)
T5
T10
T11
T16
U4
U17
V3
V18
W2
W19
Y1
Y6
Y11
Y15
Y20
Power
29
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
B18
D16
C17
P18
T17
W18
Y19
W13
V6
System Interface
28
Halt
E19
System Interface
28
HoldAck
HoldPri
HoldReq
T4
T3
V2
External MASTER Peripheral Interface
26
IICSCL
U15
Internal Peripheral Interface
26
IICSDA
W17
Internal Peripheral Interface
26
IRQ0[GPIO17]
IRQ1[GPIO18]
IRQ2[GPIO19]
IRQ3[GPIO20]
IRQ4[GPIO21]
IRQ5[GPIO22]
IRQ6[GPIO23]
D18
C20
E18
D20
G17
F18
W20
Interrupts Interface
27
MemAddr0
MemAddr1
MemAddr2
MemAddr3
MemAddr4
MemAddr5
MemAddr6
MemAddr7
MemAddr8
MemAddr9
MemAddr10
MemAddr11
MemAddr12
Y7
W7
V8
U7
Y4
U6
W4
V5
W3
V4
U3
V1
T2
SDRAM Interface
24
15
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name
Ball
Interface Group
Page
MemClkOut0
MemClkOut1
H20
G18
SDRAM Interface
24
MemData0
MemData1
MemData2
MemData3
MemData4
MemData5
MemData6
MemData7
MemData8
MemData9
MemData10
MemData11
MemData12
MemData13
MemData14
MemData15
MemData16
MemData17
MemData18
MemData19
MemData20
MemData21
MemData22
MemData23
MemData24
MemData25
MemData26
MemData27
MemData28
MemData29
MemData30
MemData31
J18
K19
L20
M20
M19
L18
L17
N20
N19
M18
M17
P20
P19
N18
U20
T18
W16
Y17
Y16
V14
Y14
U12
W12
Y12
Y9
W9
V10
U10
Y8
W8
V9
U9
SDRAM Interface
Notes:
1. MemData0 is the most significant bit (msb)
2. MemData31 is the least significant bit (lsb)
24
OVDD
F5
G5
P5
R5
T6
T7
T14
T15
F16
G16
P16
R16
E6
E7
E14
E15
Power
29
16
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name
PerAddr0
PerAddr1
PerAddr2
PerAddr3
PerAddr4
PerAddr5
PerAddr6
PerAddr7
PerAddr8
PerAddr9
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
Ball
A3
A4
B6
D7
C6
B7
D8
C7
B8
A7
D9
C8
B9
D10
C9
A9
B11
A11
B12
D11
A13
B13
C12
D12
B14
C13
D13
A16
C14
D14
A17
D15
Interface Group
External SLAVE Peripheral Interface
Note: PerAddr0 is the most significant bit (msb) on this bus.
Page
24
PerBLast
E2
External SLAVE Peripheral Interface
24
PerClk
D3
External MASTER Peripheral Interface
26
PerCS0
PerCS1[GPIO10]
PerCS2[GPIO11]
PerCS3[GPIO12]
PerCS4[GPIO13]
PerCS5[GPIO14]
PerCS6[GPIO15]
PerCS7[GPIO16]
D6
B5
C5
A5
B10
C10
A12
C11
External SLAVE Peripheral Interface
24
17
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name
Ball
Interface Group
Page
PerData0
PerData1
PerData2
PerData3
PerData4
PerData5
PerData6
PerData7
PerData8
PerData9
PerData10
PerData11
PerData12
PerData13
PerData14
PerData15
PerData16
PerData17
PerData18
PerData19
PerData20
PerData21
PerData22
PerData23
PerData24
PerData25
PerData26
PerData27
PerData28
PerData29
PerData30
PerData31
U2
R4
U1
R2
R3
T1
N4
P3
N2
P1
M4
N3
M2
N1
L4
M3
L2
M1
K2
L3
K1
J1
J2
K3
K4
H1
H2
J3
J4
G1
G2
H3
External SLAVE Peripheral Interface
Note: PerData0 is the most significant bit (msb) on this bus.
24
PerErr
B1
External MASTER Peripheral Interface
26
PerOE
E4
External SLAVE Peripheral Interface
24
PerPar0
PerPar1
PerPar2
PerPar3
C2
G3
E1
H4
External SLAVE Peripheral Interface
24
PerReady
E3
External SLAVE Peripheral Interface
24
PerR/W
C1
External SLAVE Peripheral Interface
24
PerWBE0
PerWBE1
PerWBE2
PerWBE3
PerWE
D2
F4
F3
D1
C4
External SLAVE Peripheral Interface
24
RAS
K18
SDRAM Interface
24
RcvrInh
E17
System Interface
28
18
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed Alphabetically (Continued)
Signal Name
Ball
Interface Group
Page
Reserved
J20
G19
R17
T20
V16
Other pins
Notes:
1.Connect G19 to ground.
2. Other reserved pins are not connected internally within the chip and
should not have signals, voltage, or ground applied to them.
29
SysClk
SysErr
SysReset
H17
A18
D19
System Interface
28
TCK
TDI
TDO
B4
A2
D5
JTAG Interface
27
TestEn
F19
System Interface
28
TmrClk
B20
System Interface
28
TMS
B3
JTAG Interface
27
TRST
H19
JTAG Interface
27
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
UART0_RTS
UART0_Rx
UART0_Tx
W10
R18
U16
U13
V15
V20
T19
W15
Internal Peripheral Interface
26
UART1_DSR[UART1_CTS]
UART1_RTS[UART1_DTR]
UART1_Rx
UART1_Tx
V7
W6
W5
Y5
Internal Peripheral Interface
26
UARTSerClk
R19
Internal Peripheral Interface
26
VDD
E8
E9
E12
E13
H5
H16
J5
J16
M5
M16
N5
N16
T8
T9
T12
T13
Power
29
WE
U11
SDRAM Interface
24
19
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed by Ball Assignment
Ball
20
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
A1
GND
B10
PerCS4[GPIO13]
C19
DrvrInh2
E8
VDD
A2
TDI
B11
PerAddr16
C20
IRQ1[GPIO18]
E9
VDD
A3
PerAddr0
B12
PerAddr18
D1
PerWBE3
E10
GND
A4
PerAddr1
B13
PerAddr21
D2
PerWBE0
E11
GND
A5
PerCS3[GPIO12]
B14
PerAddr24
D3
PerClk
E12
VDD
A6
Gnd
B15
DMAReq2
D4
GND
E13
VDD
A7
PerAddr9
B16
DMAAck2
D5
TDO
E14
OVDD
A8
DMAReq3
B17
DMAAck1
D6
PerCS0
E15
OVDD
A9
PerAddr15
B18
GPIO1[TS1E]
D7
PerAddr3
E16
GND
A10
GND
B19
GND
D8
PerAddr6
E17
Rcrvinh
A11
PerAddr17
B20
TmrClk
D9
PerAddr10
E18
IRQ2[GPIO19]
A12
PerCS6[GPIO15]
C1
PerR/W
D10
PerAddr13
E19
Halt
A13
PerAddr20
C2
PerPar0
D11
PerAddr19
E20
AVDD
A14
DMAAck3
C3
GND
D12
PerAddr23
F1
GND
A15
GND
C4
PerWE
D13
PerAdd26
F2
EOT1(TC1)
A16
PerAddr27
C5
PerCS2[GPIO11]
D14
PerAddr29
F3
PerWBE2
A17
PerAddr30
C6
PerAddr4
D15
PerAddr31
F4
PerWBE1
A18
SysErr
C7
PerAddr7
D16
GPIO2[TS2E]
F5
OVDD
A19
DMAReq0
C8
PerAddr11
D17
GND
F16
OVDD
A20
GND
C9
PerAddr14
D18
IRQ0[GPIO17]
F17
DrvrInh1
B1
PerErr
C10
PerCS5[GPIO14]
D19
SysReset
F18
IRQ5[GPIO22]
B2
GND
C11
PerCS7[GPIO16]
D20
IRQ3[GPIO20]
F19
TestEn
B3
TMS
C12
PerAddr22
E1
PerPar2
F20
GND
B4
TCK
C13
PerAddr25
E2
PerBLast
G1
PerData29
B5
PerCS1[GPIO10]
C14
PerAddr28
E3
PerReady
G2
PerData30
B6
PerAddr2
C15
DMAReq1
E4
PerOE
G3
PerPar1
B7
PerAddr5
C16
DMAAck0
E5
GND
G4
EOT0[TC0]
B8
PerAddr8
C17
GPIO3[TS1O]
E6
OVDD
G5
OVDD
B9
PerAddr12
C18
GND
E7
OVDD
G16
OVDD
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed by Ball Assignment (Continued)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
G17
IRQ4[GPIO21]
K2
PerData18
M3
PerData15
P18
GPIO4[TS2O]
G18
MemClkout1
K3
PerData23
M4
PerData10
P19
MemData12
G19
Reserved
K4
PerData24
M5
VDD
P20
MemData11
G20
ClkEn1
K5
GND
M9
Thermal Ball
R1
GND
H1
PerData25
K9
Thermal Ball
M10
Thermal Ball
R2
PerData3
H2
PerData26
K10
Thermal Ball
M11
Thermal Ball
R3
PerData4
H3
PerData31
K11
Thermal Ball
M12
Thermal Ball
R4
PerData1
H4
PerPar3
K12
Thermal Ball
M16
VDD
R5
OVDD
H5
VDD
K16
GND
M17
MemData10
R16
OVDD
H16
VDD
K17
CAS
M18
MemData9
R17
Reserved
H17
SysClk
K18
RAS
M19
MemData4
R18
UART0_DCD
H18
BA1
K19
MemData1
M20
MemData3
R19
UARTSerClk
H19
TRST
K20
GND
N1
PerData13
R20
GND
H20
MemClkout0
L1
GND
N2
PerData8
T1
PerData5
J1
PerData21
L2
PerData16
N3
PerData11
T2
MemAddr12
J2
PerData22
L3
PerData19
N4
PerData6
T3
HoldPri
J3
PerData27
L4
PerData14
N5
VDD
T4
HoldAck
J4
PerData28
L5
GND
N16
VDD
T5
GND
J5
VDD
L9
Thermal Ball
N17
BankSel1
T6
OVDD
J9
Thermal Ball
L10
Thermal Ball
N18
MemData13
T7
OVDD
J10
Thermal Ball
L11
Thermal Ball
N19
MemData8
T8
VDD
J11
Thermal Ball
L12
Thermal Ball
N20
MemData7
T9
VDD
J12
Thermal Ball
L16
GND
P1
PerData9
T10
GND
J16
VDD
L17
MemData6
P2
BusReq
T11
GND
J17
BA0
L18
MemData5
P3
PerData7
T12
VDD
J18
MemData0
L19
BankSel0
P4
ExtReset
T13
VDD
J19
ClkEn0
L20
MemData2
P5
OVDD
T14
OVDD
J20
Reserved
M1
PerData17
P16
OVDD
T15
OVDD
K1
PerData20
M2
PerData12
P17
BankSel2
T16
GND
21
PowerPC 405CR Embedded Controller Data Sheet
Signals Listed by Ball Assignment (Continued)
Ball
22
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
W20
Signal Name
T17
GPIO5 (TS3)
U18
DQM0
V19
DQMCB
IRQ6[GPIO23]
T18
MemData15
U19
BankSel3
V20
UART0_RTS
Y1
GND
T19
UART0_RX
U20
MemData14
W1
EOT2[TC2]
Y2
EOT3[TC3]
T20
Reserved
V1
MemAddr11
W2
GND
Y3
ExtReq
U1
PerData2
V2
HoldReq
W3
MemAddr8
Y4
MemAddr4
U2
PerData0
V3
GND
W4
MemAddr6
Y5
UART1_TX
U3
MemAddr10
V4
MemAddr9
W5
UART1_RX
Y6
GND
U4
GND
V5
MemAddr7
W6
UART1_RTS
[UART1_DTR]
Y7
MemAddr0
U5
ExtAck
V6
GPIO9[TrcClk]
W7
MemAddr1
Y8
MemData28
U6
MemAddr5
V7
UART1_DSR
[UART1_CTS]
W8
MemData29
Y9
MemData24
U7
MemAddr3
V8
MemAddr2
W9
MemData25
Y10
DQM2
U8
DQM3
V9
MemData30
W10
UART0_CTS
Y11
GND
U9
MemData31
V10
MemData26
W11
ECC6
Y12
MemData23
U10
MemData27
V11
ECC7
W12
MemData22
Y13
ECC4
U11
WE
V12
ECC5
W13
GPIO8[TS6]
Y14
MemData20
U12
MemData21
V13
ECC3
W14
DQM1
Y15
GND
U13
UART0_DTR
V14
MemData19
W15
UART0_TX
Y16
MemData18
U14
ECC2
V15
UART0_RI
W16
MemData16
Y17
MemData17
U15
IICSCL
V16
Reserved
W17
IICSDA
Y18
ECC1
U16
UART0_DSR
V17
ECC0
W18
GPIO6[TS4]
Y19
GPIO7[TS5]
U17
GND
V18
GND
W19
GND
Y20
GND
PowerPC 405CR Embedded Controller Data Sheet
Pin Lists
The PPC405CR embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA).
The following tables describe the package level pinout.
Pin Summary
Group
No. of Pins
SDRAM
71
External Peripheral
97
External Master
9
Internal Peripheral
15
Interrupts
7
JTAG
5
System
18
Total Signal Pins
222
AVDD
1
OVDD
16
VDD
16
Gnd
40
Thermal (and Gnd)
16
Reserved
5
Total Pins
316
In the table “Signal Functional Description” on page 24, each I/O signal is listed along with a short description
of the signal function. Some signals are multiplexed onto the same pin (ball) so that the pin is usable for
different functions. Multiplexed signals are shown in square brackets following the default signal (for example,
C0:3[BE0:3]) and described consecutively within each pin functional description. Active-low signals such as
BE0:3 are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
In addition to multiplexing, many pins are also multi-purpose. These pins are described in the table using a
single row with a text description that indicates the different functional uses of the pin. For example, the EBC
peripheral controller address pins are used as outputs by the PPC405CR to broadcast an address to external
slave devices when the PPC405CR has control of the external bus. When during the course of normal chip
operation an external master gains ownership of the external bus, these same pins are used as inputs which
are driven by the external master and received by the EBC in the PPC405CR.
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Strapping” on page 39). Note
that these are not multiplexed pins since the function of the pins is not programmable.
The following table lists all of the I/O signals provided by the PPC405CR. Please refer to “Signals Listed
Alphabetically” on page 13 for the pin number to which each signal is assigned.
23
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 1 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
I/O
Type
Notes
MemData0:31
Memory Data bus
Notes:
1. MemData0 is the most significant bit (msb)
2. MemData31 is the least significant bit (lsb)
I/O
3.3V LVTTL
4
MemAddr12:0
Memory Address bus
O
3.3V LVTTL
Signal Name
Description
SDRAM Interface
BA0:1
Bank Address supporting up to four internal banks
O
3.3V LVTTL
RAS
Row Address Strobe
O
3.3V LVTTL
CAS
Column Address Strobe
O
3.3V LVTTL
DQM0:3
DQM for byte lanes 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
DQMCB
DQM for ECC check bits
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7
I/O
3.3V LVTTL
Select up to four external SDRAM banks
O
3.3V LVTTL
BankSel0:3
WE
ClkEn0:1
MemClkOut0:1
Write Enable
O
3.3V LVTTL
SDRAM Clock Enable
O
3.3V LVTTL
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a
PLL or zero-delay buffer.
O
3.3V LVTTL
4
External SLAVE Peripheral Interface
PerData0:31
Peripheral data bus used by PPC405CR when not in external
master mode, otherwise used by external master
Note: PerData0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr0:31
Peripheral address bus used by PPC405CR when not in external
master mode, otherwise used by external master.
Note: PerAddr0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
Peripheral byte parity signals
I/O
5V tolerant
3.3V LVTTL
1
As outputs, these pins can act as byte-enables which are valid for
an entire cycle or as write-byte-enables which are valid for each
byte on each data transfer, allowing partial word transactions. As
outputs, pins are used by either peripheral controller or DMA
controller depending upon the type of transfer involved. Used as
inputs when external bus master owns the external interface
I/O
5V tolerant
3.3V LVTTL
1, 2
Peripheral chip select bank 0
O
5V tolerant
3.3V LVTTL
2
PerPar0:3
PerWBE0:3
PerWE
PerCS0
24
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 2 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
PerCS1:7[GPIO10:16]
Description
Seven additional peripheral chip selects
or
General Purpose I/O - To access this function, software must
toggle a DCR register bit.
I/O
Type
Notes
O[I/O]
5V tolerant
3.3V LVTTL
1,2
PerOE
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC405CR is the
bus master, it enables the selected SDRAMs to drive the bus.
O
5V tolerant
3.3V LVTTL
2
PerR/W
Used by the PPC405CR when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise it used by the external master as an input to indicate
the direction of transfer.
I/O
5V tolerant
1, 2
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
I
5V tolerant
Rcvr
1, 2
PerBLast
Used by the PPC405CR when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
memory access.
I/O
5V tolerant
3.3V LVTTL
1, 4
DMAReq0:3
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
I
5V tolerant
Rcvr
1, 5
DMAAck0:3
DMAAck0:3 are used by the PPC405CR to indicate that data
transfers have occurred.
O
5V tolerant
3.3V LVTTL
6
End Of Transfer/Terminal Count
I/O
5V tolerant
3.3V LVTTL
1, 5
EOT0:3[TC0:3]
25
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 3 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
External MASTER Peripheral Interface
PerClk
Peripheral clock to be used by an external master and by
synchronous peripheral slaves
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by an external master and by
synchronous peripheral slaves
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request, used by an external master to request ownership
of the peripheral bus
I
5V tolerant
Rcvr
1, 5
HoldAck
Hold Acknowledge, used by the PPC405CR to transfer
ownership of peripheral bus to an external master
O
5V tolerant
3.3V LVTTL
6
ExtReq
ExtReq is used by an external master to indicate it is prepared to
transfer data
I
5V tolerant
Rcvr
1, 4
ExtAck
ExtAck is used by the PPC405CR to indicate that a data transfer
occurred.
O
5V tolerant
3.3V LVTTL
6
HoldPri
Used by an external master to indicate the priority of a given
transfer (0 = high, 1 = low)
I
5V tolerant
Rcvr
1, 4
BusReq
Used when the PPC405CR needs to regain control of peripheral
interface from an external Master
O
5V tolerant
3.3V LVTTL
Used as an input used to record external Master errors and
external slave peripheral errors
I
5V tolerant
Rcvr
1, 5
Serial Clock used to provide an alternative clock to the internally
generated serial clock. Used in cases where the allowable
internally generated baud rates are not satisfactory. This input
can be individually connected to either UART.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Rx
UART0 Serial Data In
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Tx
UART0 Serial Data Out
O
5V tolerant
3.3V LVTTL
6
UART0_DCD
UART0 Data Carrier Detect
I
5V tolerant
3.3V LVTTL
1, 4
UART0_DSR
UART0 Data Set Ready
I
5V tolerant
3.3V LVTTL
1, 4
UART0_CTS
UART0 Clear To Send
I
5V tolerant
3.3V LVTTL
1, 4
UART0_DTR
UART0 Data Terminal Ready
O
5V tolerant
3.3V LVTTL
6
UART0_RTS
UART0 Request To Send
O
5V tolerant
3.3V LVTTL
6
UART0 Ring Indicator
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
PerErr
Internal Peripheral Interface
UARTSerClk
UART0_RI
26
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 4 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
UART1_Rx
UART1 Serial In data
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
UART1_Tx
UART1 Serial Out data.
O
5V tolerant
3.3V LVTTL
6
UART1_DSR
[UART1_CTS]
UART1 Data Set Ready
or
UART1 Clear To Send. To access this function, software must
toggle a DCR register bit.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
UART1_RTS
[UART1_DTR]
UART1 Request To Send
or
UART1 Data Terminal Ready. To access this function, software
must toggle a DCR register bit.
O
5V tolerant
3.3V LVTTL
6
IICSCL
IIC Serial Clock
I/O
5V tolerant
3.3V LVTTL
1, 2
IICSDA
IIC Serial Data
I/O
5V tolerant
3.3V LVTTL
1, 2
I[I/O]
5V tolerant
3.3V LVTTL
1, 5
Interrupts Interface
IRQ0:6[GPIO17:23]
Interrupt requests
or
General Purpose I/O. To access this function, software must
toggle a DCR register bit.]
JTAG Interface
TDI
Test data in
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
TMS
JTAG test mode select
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
TDO
Test data out
O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
JTAG reset
I
5V tolerant
Rcvr
5
TRST
27
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 5 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
Notes
I/O
Type
I
5V tolerant
3.3V LVTTL
Rcvr
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to start a system reset. The
PPC405CR then holds the output low for 8192 cycles to reset all
internal and external logic connected to SysReset. A system
reset can also be initiated by software.
I/O
5V tolerant
3.3V LVTTL
Rcvr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
System Interface
SysClk
SysReset
SysErr
Halt
Main system clock input
1, 2
GPIO1[TS1E]
GPIO2[TS2E]
General Purpose I/O
or
Even Trace execution status.To access this function, software
must toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO3[TS1O]
GPIO4[TS2O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software
must toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1 (A22, AF18),
6 (AF18 only)
I/O[O]
5V tolerant
3.3V LVTTL
1, 4
I/O[O]
5V tolerant
3.3V LVTTL
1, 4
General Purpose I/O
GPIO5:8[TS3:6]
GPIO9[TrcClk]]
28
Trace status. To access this function, software must toggle a
DCR register bit.
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR register bit.
TestEn
Test Enable
I
5V tolerant
Rcvr w/ PD
3
RcvrInh
Receiver Inhibit. Set to 1 for normal operation. Setting to 0
disables all inputs for test purposes.
I
5V tolerant
Rcvr
2
DrvrInh1:2
Driver Inhibit 1 and 2. Set to 1 for normal operation. Setting to 0
disables all outputs for test purposes.
I
5V tolerant
Rcvr
2
TmrClk
This input must toggle at a rate of less than one half the CPU
core frequency (less than 100MHz in most cases). In most cases
this input toggles much slower (in the 1MHz to 10MHz range).
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
PowerPC 405CR Embedded Controller Data Sheet
Signal Functional Description (Part 6 of 6)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Power
GND
Ground
Note: Pins J9–J12, K9–K12, L9–L12, and M9–M12 are also
thermal balls.
I
AVDD
Filtered voltage input for PLL (analog) circuits
I
OVDD
Output driver voltage—3.3V
I
Logic voltage—2.5V
I
VDD
Other pins
Reserved
Connect G19 to ground. Do not connect signals, voltage, or
ground to any other reserved pins.
29
PowerPC 405CR Embedded Controller Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device
Characteristic
Symbol
Value
Unit
Supply Voltage (Internal Logic)
VDD
0 to 2.7
V
Supply Voltage (I/O Interface)
OVDD
0 to 3.6
V
PLL Supply Voltage
AVDD
0 to 2.7
V
VIN
0 to 3.6
V
VIN
Input Voltage (3.3V LVTTL receivers)
0 to 5.5
V
Storage Temperature Range
TSTG
-55 to 150
°C
Case temperature under bias
TC
-40 to +120
°C
Input Voltage (5.0V LVTTL receivers)
Package Thermal Specifications
The PPC405CR is designed to operate within a case temperature range of -40˚C to 120˚C. Thermal resistance values for
the E-PBGA package in a convection environment are as follows:
Parameter
Airflow
ft/min (m/sec)
Symbol
Unit
0 (0)
100 (0.51)
200 (1.02)
Junction-to-case thermal resistance
θJC
2
2
2
°C/W
Case-to-ambient thermal resistance (without heat
sink)
θCA
18
16
15
°C/W
Notes:
1. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
2. TA = TC – P×θ CA, where TA is ambient temperature and P is power consumption.
3. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption.
4. The above assumes that the chip is mounted on a card with at least one signal and two power planes.
30
PowerPC 405CR Embedded Controller Data Sheet
Recommended DC Operating Conditions
Note: Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
VDD
2.3
2.5
2.7
V
I/O Supply Voltage
OVDD
3.0
3.3
3.6
V
PLL Supply Voltage
AVDD
2.3
2.5
2.7
V
Input Logic High (3.3V LVTTL
receivers)
VIH
2.0
OVDD
V
Input Logic High (5.0V LVTTL
receivers)
VIH
2.0
5.5
V
Input Logic Low
VIL
0
0.8
V
Output Logic High
VOH
2.4
OVDD
V
Output Logic Low
VOL
0
0.4
V
Input Leakage Current (No pull-up
or pull-down)
IIL1
0
0
µA
Input Leakage Current for PullDown
IIL2
0 (LPDL)
400 (MPUL)
µA
Input Leakage Current for Pull-Up
IIL3
−250 (LPDL)
0 (MPUL)
µA
Logic Supply Voltage
Input Max Allowable Overshoot
(3.3V LVTTL receivers)
VIMAO3
OVDD + 0.6
V
Input Max Allowable Overshoot
(5.0V LVTTL receivers)
VIMAO5
5.5
V
Input Max Allowable Undershoot
(3.3V or 5.0V receivers)
VIMAU
Output Max Allowable Overshoot
(3.3V or 5.0V receivers)
VOMAO
Output Max Allowable Undershoot
(3.3V and 5.0V receivers)
VOMAU3
− 0.6
TC
− 40
Case Temperature
− 0.6
Notes
V
OVDD + 0.3
V
V
°C
85
Capacitance
Parameter
Symbol
Maximum
Unit
Input Capacitance Group 1 (3.3V LVTTL //O)
CIN1
2.5
pF
Input Capacitance Group 2 (5V tolerant LVTTL I/O)
CIN2
3.5
pF
Input Capacitance Group 3
CIN3
5.0
pF
Input Capacitance Group 1 (RX only pins)
CIN4
0.75
pF
Notes
DC Electrical Characteristics
Parameter
Active Operating Current (VDD)
Symbol
Minimum
Typical
Maximum
Unit
IDD
TBD
mA
Active Operating Current (OVDD)
IODD
TBD
mA
PLL Voltage
VPLL
PLL VDD Input current
IPLL
2.3
2.5
2.7
V
16
23
mA
31
PowerPC 405CR Embedded Controller Data Sheet
Test Conditions
Output
Pin
Clock timing and switching characteristics are specified in accordance
with operating conditions shown in the table “Recommended DC
Operating Conditions.” AC specifications are characterized at
VDD = 3.14V and TJ = 100˚C with the 50pF test load (CL) shown in
the figure at right.
CL = 50pf for all signals
CL
SysClk and MemClk Timing
Symbol
Parameter
Min
Max
Units
SysClk Input
FC
SysClk clock input frequency
25
66.6
MHz
TC
SysClk clock period
15
40
ns
TCS
Clock edge stability
–
0.15
ns
TCH
Clock input high time
40% of nominal period
60% of nominal period
ns
TCL
Clock input low time
40% of nominal period
60% of nominal period
ns
100
MHz
133
MHz
Note: Input slew rate > 2V/ns
MemClk Output
FC
MemClk clock output frequency—200MHz
TC
MemClk clock period—200MHz
FC
MemClk clock output frequency—266MHz
TC
MemClk clock period—266MHz
TCH
Clock output high time
35% of nominal period
65% of nominal period
ns
TCL
Clock output low time
35% of nominal period
65% of nominal period
ns
10
ns
7.5
ns
Timing Waveform
2.0V
1.5V
0.8V
TCH
TCL
TC
32
PowerPC 405CR Embedded Controller Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405CR. This
controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG
is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew
there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When
using an SSCG with the PPC405CR the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405CR with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board PPC405CR peripherals impose more stringent requirements (see
Note 1).
• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
modulation.
• Use the SDRAM MemClk since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the
connected device is running at precise baud rates.
2. IIC operation is unaffected.
Caution: It is up to the system designer to ensure that any SSCG used with the PPC405CR meets the
above requirements and does not adversely affect other aspects of the system.
33
PowerPC 405CR Embedded Controller Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
PerClk output frequency—200MHz (for external master or synchronous
slaves)
–
50
MHz
PerClk period—200MHz
20
–
ns
PerClk output frequency—266MHz (for external master or synchronous
slaves)
–
66
MHz
PerClk period—266MHz
15
–
ns
PerClk output high time
50% of nominal period
66% of nominal period
ns
PerClk output low time
33% of nominal period
50% of nominal period
ns
–
1000/(2TOPB+2ns)
MHz
UARTSerClk period
2TOPB+2
–
ns
UARTSerClk input high time
TOPB+1
–
ns
UARTSerClk input low time
UARTSerClk input frequency (Note 1)
TOPB+1
–
ns
TmrClk input frequency—200MHz
–
50
MHz
TmrClk period—200MHz
20
–
ns
TmrClk input frequency—266MHz
–
66
MHz
TmrClk period—266MHz
15
–
ns
TmrClk input high time
40% of nominal period
60% of nominal period
ns
TmrClk input low time
40% of nominal period
60% of nominal period
ns
Notes:
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB
clock frequency is 50 MHz for 200MHz parts and 66MHz.for 266MHz parts.
34
PowerPC 405CR Embedded Controller Data Sheet
Input Setup and Hold Waveform
SysClk
1.5V
TIS
TIH
MIN
MIN
Inputs
1.5V
Valid
TIS
MIN
Data Bus
D0:31
(Inputs)
TIH
MIN
1.5V
Valid
Valid
Output Delay and Float Timing Waveform
SysClk
1.5V
TOH
MIN
TOV
MAX
Outputs
1.5V
Valid
TOF
Outputs
MAX
MIN
1.5V
35
PowerPC 405CR Embedded Controller Data Sheet
I/O Specifications—All
Input (ns)
Signal
Setup Time Hold Time
(minimum) (minimum)
Output (ns)
Valid Delay
Hold Time
(maximum) (minimum)
50pF load
50pF load
Output Current (mA)
I/O H
(maximum)
I/O L
(minimum)
12
12
8
8
8
8
8
8
8
8
Clock
Notes
Internal Peripheral Interface
IICSCL
IICSDA
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
UART0_RTS
UART0_Rx
UART0_Tx
UART1_RTS
[UART1_DTR]
UART1_DSR
[UART1_CTS]
UART1_Rx
UART1_Tx
UARTSerClk
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
19
19
12
12
12
12
12
12
12
12
na
na
12
8
n/a
n/a
n/a
12
n/a
n/a
8
n/a
12
8
n/a
n/a
12
n/a
n/a
n/a
n/a
8
n/a
n/a
n/a
n/a
12
8
n/a
n/a
n/a
12
12
n/a
n/a
n/a
n/a
n/a
8
8
n/a
n/a
na
na
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK
TDI
TDO
TMS
TRST
async
async
async
async
async
System Interface
DrvrInh1:2
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
Halt
RcvrInh
SysClk
SysErr
SysReset
TestEn
TmrClk
36
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
async
async
async
async
async
PowerPC 405CR Embedded Controller Data Sheet
I/O Specifications—200MHz
Notes:
1. The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
2. SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and risingedge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
3. SDRAM CLK0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a typical clock
network or a lumped 10pF load.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Signal
Setup Time Hold Time
(minimum) (minimum)
Output (ns)
Valid Delay
Hold Time
(maximum) (minimum)
50pF load
50pF load
Output Current (mA)
I/O H
(maximum)
I/O L
(minimum)
Clock
Notes
1, 2
2
1, 2
2
2
2
2
1, 2
2, 3
2
1, 2
1, 2
SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn0:1
DQM0:3
DQMCB
ECC0:7
MemAddr12:0
MemClkOut0:1
MemData0:31
RAS
WE
n/a
n/a
n/a
n/a
n/a
n/a
2
n/a
n/a
2
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
n/a
n/a
1
n/a
n/a
7.3
5.8
7.3
4.7
6.2
6
6
7.8
0
6.2
7.4
7.4
1
1
1
1
1
1
1
1
-1
1
1
1
19
19
19
40
19
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
12
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
n/a
dc
dc
4
4
n/a
dc
dc
1
1
8
n/a
9
10
8
0
n/a
0
0
0
12
n/a
12
19
12
8
n/a
8
12
8
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
n/a
9
0
12
8
PerClk
6
n/a
4
5
9
4
1
n/a
1
1
1
1
10
8
10.5
8
n/a
8
0
0
0
0
n/a
0
19
12
19
12
n/a
12
12
8
12
8
n/a
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
8
8
n/a
8
8
n/a
n/a
0.9
n/a
0
0
n/a
0
0
n/a
n/a
0.9
n/a
12
12
n/a
19
12
n/a
n/a
19
n/a
8
8
n/a
12
8
n/a
n/a
12
n/a
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
External SLAVE Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3[TC0:3]
PerAddr0:31
PerBLast
PerCS0
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
External MASTER Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
PerErr
n/a
n/a
6
n/a
n/a
4
6
n/a
4
n/a
n/a
1
n/a
n/a
1
1
n/a
1
4
37
PowerPC 405CR Embedded Controller Data Sheet
I/O Specifications—266MHz (Preliminary)
Notes:
1. The two-cycle SDRAM command interface is driven in cycle 1 and used in cycle 2. Output times in table are in cycle 1.
2. SDRAM output timing is relative to the rising edge of the internal PLB clock, which is an integral multiple of and risingedge aligned with SysClk. Therefore, SDRAM output timings in the table are shown relative to SysClk. Timings shown
are for a lumped 50pF load, however the interface has been verified for PC100-compliant operation using transmission
line circuit analysis.
3. SDRAM CLK0:1 rising edge at package pin precedes the internal PLB clock by approximately 0.5ns for a typical clock
network or a lumped 10pF load.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Signal
Setup Time Hold Time
(minimum) (minimum)
Output (ns)
Valid Delay
Hold Time
(maximum) (minimum)
50pF load
50pF load
Output Current (mA)
I/O H
(maximum)
I/O L
(minimum)
Clock
Notes
1, 2
2
1, 2
2
2
2
2
1, 2
2, 3
2
1, 2
1, 2
SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn0:1
DQM0:3
DQMCB
ECC0:7
MemAddr12:0
MemClkOut0:1
MemData0:31
RAS
WE
n/a
n/a
n/a
n/a
n/a
n/a
1.5
n/a
n/a
1.5
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
n/a
n/a
1
n/a
n/a
5.5
4.5
5.5
3.9
4.9
4.7
4.7
5.9
0
4.8
5.6
5.6
1
1
1
1
1
1
1
1
1
1
1
1
19
19
19
40
19
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
12
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
SysClk
n/a
dc
dc
3
3.5
n/a
dc
dc
1
1
6
n/a
8
8
6
0
n/a
0
0
0
12
n/a
12
19
12
8
n/a
8
12
8
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
n/a
6
0
12
8
PerClk
5
n/a
3.5
4
6.5
3
1
n/a
1
1
1
1
8
6
8
6
n/a
6
0
0
0
0
n/a
0
19
12
19
12
n/a
12
12
8
12
8
n/a
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
External SLAVE Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3[TC0:3]
PerAddr0:31
PerBLast
PerCS0
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
External MASTER Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
PerErr
38
n/a
n/a
5
n/a
n/a
1
6
6
n/a
0
0
n/a
12
12
n/a
8
8
n/a
PerClk
PerClk
PerClk
n/a
n/a
3
5
n/a
3
n/a
n/a
1
1
n/a
1
6
6
n/a
n/a
0.9
n/a
0
0
n/a
n/a
0.9
n/a
19
12
n/a
n/a
12
n/a
12
8
n/a
n/a
12
n/a
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
4
PowerPC 405CR Embedded Controller Data Sheet
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial
conditions prior to PPC405CR start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. These pins are use for strap functions only during
reset. They are used for other signals during normal operation. The following table lists the strapping pins
along with their functions and strapping options:
Strapping Pin Assignments
Function
PLL Tuning
for 6 ≤ M ≤ 7 use choice 3
for 7 < M ≤ 12 use choice 5
for 12 < M ≤ 32 use choice 6
See Note.
Option
Ball Strapping
W15
U13
V20
Choice 1; TUNE[5:0] = 010001
0
0
0
Choice 2; TUNE[5:0] = 010010
0
0
1
Choice 3; TUNE[5:0] = 010011
0
1
0
Choice 4; TUNE[5:0] = 010100
0
1
1
Choice 5; TUNE[5:0] = 010101
1
0
0
Choice 6; TUNE[5:0] = 010110
1
0
1
Choice 7; TUNE[5:0] = 010111
1
1
0
Choice 8; TUNE[5:0] = 100100
1
1
1
C16
B17
PLL Forward Divider
Bypass mode
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 6
1
1
B16
A14
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
PLL Feedback Divider
Divide by 4
1
1
B18
D16
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
PLB Divider from CPU
Divide by 4
1
1
T4
U5
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
OPB Divider from PLB
External Bus Divider from PLB
C17
P18
Divide by 2
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 5
1
1
39
PowerPC 405CR Embedded Controller Data Sheet
Strapping Pin Assignments (Continued)
Function
Option
ROM Width
Ball Strapping
Y5
W6
8-bit ROM
0
0
16-bit ROM
0
1
32-bit ROM
1
0
Reserved
1
1
Note: The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405CR. These bits are shown for information only; and do not require modification except in special clocking circumstances
such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405CR,
visit the technical documents area of the IBM PowerPC web site.
40
PowerPC 405CR Embedded Controller Data Sheet
Inside of back cover
41
PowerPC 405CR Embedded Controller Data Sheet
(c) Copyright International Business Machines Corporation 1999, 2001
All Rights Reserved
Printed in the United States of America January 2001
The following are trademarks of International Business Machines Corporation in the United States, or other
countries, or both:
Blue Logic
IBM
PowerPC 405CR
CodePack
IBM Logo
CoreConnect
PowerPC
Other company, product, and service names may be trademarks or service marks of others.
While the information contained herein is believed to be accurate, such information is preliminary, and should
not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or
completeness are made.
All information contained in this document is subject to change without notice. The products described in this
document are NOT intended for use in implantation or other life support applications where malfunction may
result in injury or death to persons. The information contained in this document does not affect or change
IBM product specifications or warranties. Nothing in this document shall operate as an express or implied
license or indemnity under the intellectual property rights of IBM or third parties. All information contained in
this document was obtained in specific environments, and is presented as an illustration. The results
obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event
will IBM be liable for damages arising directly or indirectly from any use of the information contained in this
document.
IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction, NY 12533-6351
The IBM home page can be found at
http://www.ibm.com
The IBM Microelectronics Division home page can be found at
http://www.chips.ibm.com
SA14-2522-05
42