AMIS-720639: 600dpi CIS Sensor Chip Data Sheet 1.0 Description AMI Semiconductor’s AMIS-720639 (PI3039) contact image sensor (CIS) sensor chip is a linear array image sensor chip with a 600 elements per inch resolution. The sensor chip is fabricated with AMI Semiconductor’s proprietary CMOS image sensing technology. Since this image sensor chip is intended for CIS module applications, multiple numbers of these sensors will be serially cascaded to form a linear scanning image array of arbitrary length. These sensors are butted end-to-end on a printed circuit board (PCB). The sensors are mounted using the chip-on-board technology to form scanning arrays with various lengths. Figure 1: AMIS-720639 Sensor Block Diagram Figure 1 is a block diagram of the sensor chip. Each sensor chip consists of 192 detector elements, their associated multiplexing switches, buffer amplifiers and a chip selector. The detector's element-to-element spacing is approximately 42µm. The size of each chip without the scribe lines is 8080µm by 360µm and each sensor chip has six bonding pads. The pad symbols and functions are described in Table 1. Table 1: Pad Symbols and Functions Symbol Function SP Start pulse: input to start the line scan CP Clock pulse: input to clock the shift register VDD Positive supply: +5V supply connected to substrate VSS VSS is tied to ground: connection topside common IOUT Video signal current output from a source follower EOS End-of-scan pulse: output from the shift register at end-of-scan AMI Semiconductor – May 06, M-20569-001 www.amis.com 1 AMIS-720639: 600dpi CIS Sensor Chip Data Sheet Figure 2: Bonding Pad Layout Diagram: Figure 2 shows the bonding pad locations for the AMIS-720639 sensor chip. The locations are referenced to the lower left corner of the die. AMI Semiconductor – May 06, M-20569-001 www.amis.com 2 AMIS-720639: 600dpi CIS Sensor Chip Data Sheet 2.0 Electro-Optical Characteristics (25°C) Table 2 lists the electro-optical characteristics of the AMIS-720639 sensor chip at 25°C. Table 2: Electro-Optical Characteristics Parameters Number of photo-elements Pixel-to-pixel spacing Chip scanning rate Symbols Typical 192 42 38.4 Units Elements µm µsec Notes Tint (1) Clock frequency fclk (2) 5.0 MHz IOUT (saturation charge output for a given sample time) At 5.0MHz clock frequency Video voltage output from an A4 size CIS module, AMIS-710620-A4 (PI620MC-A4) (four tapped outputs, for high speed application) Output voltage non-uniformity Qsat (3) 170 to 200 pC With 570nm light source. At saturation 2 exposure of 5.7Joules/cm 1.0 0.300 V V ± 7.5 % ± 7.5 % <50 <20 mV mV Using a red LED source Using a Yellow-Green LED source, at minimum integration time ≅ 277µsec @ 5MHz clock rate Test circuit used only the amplifier of Note 4 Test circuit used only the amplifier in Note 4 Test circuit see Note 4 Test circuit see Note 4 Vpavg Up (5) Chip-to-chip non-uniformity Ucc Dark output voltage Dark output non-uniformity Vd (6) Ud Notes: (1) (2) (3) (4) (5) (6) (7) (6) (4) @ typical 5MHz pixel rate See Note 2 See Note 2 Tint stands for the line scanning rate or the integration time. It is determined by the time interval between two SPs at the maximum clock rate of 6.5MHz, Tint = 29.5µsec. fclk stands for the input clock frequency; maximum operating frequency is 6.5MHz. There are three types of signal outputs that are called out in the table (see Section 7.0). The referenced section discusses each of the video output circuits. Two are defined for pulsed current, or charge processing, (see Figure 5 or Figure 7). The third is voltage output circuit, specified for most CIS applications because of its lower cost and simpler implementation advantages (see Figure 6). Specified for CIS application is a circuit with a buffer amplifier that interfaces the video output (see Figure 6).This typical video output line is terminated with a commonly used standard op-amp circuit. It is located in Section 7.0. The AMIS-710227 (PI227MC-A4) CIS module, employing this type of output circuit, was used in the measurements. Note: A LED light source is an integral part of the module. Up is the uniformity specification. It is measure with the image sensor exposed under a uniform light source. Up = [(Vpmax-Vpavg)/Vpavg]x100% Or [(Vpavg-Vpmin)/Vpavg]x100%, which ever is greater. Where Vpavg = ∑Vpn/Npixels a. Vpn is the nth pixels of sensor chip. b. Npixels is the total number of pixels in sensor chip. c. Vpmax is the maximum pixel output voltage in the light. d. Vpmin is the minimum pixel output voltage in the light. Note: In the light means the sensor is exposed to the light. Video output in dark: Vd = ∑Vdn/Npixels Note: In the dark means that sensor are placed on dark target and measured with the light off. Uniformity in the dark: Ud = (Vdmax-Vdmin) a. Vdmax is the maximum pixel output voltage in the dark. b. Vdmin is the minimum pixel output voltage in the dark. AMI Semiconductor – May 06, M-20569-001 www.amis.com 3 AMIS-720639: 600dpi CIS Sensor Chip Data Sheet 3.0 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings Parameters Power supply voltage Power supply current Input clock pulse (high level) Input clock pulse (low level) Symbol VDD IDD Vih Vil Maximum Rating 7.0 <3.0 Vdd + 0.5 -0.25 Units V ma V V Symbol Top Hop Tstg Hstg Maximum Rating 0 to 50 10 to 85 -25 to 75 10 to 90 Units ° C RH % ° C RH % 4.0 Environmental Ratings Table 4: Environmental Ratings Parameters Operating Temperature Operating humidity Storage temperature Storage humidity 5.0 Operating Range at Room Temperature Table 5: Recommended Operating Conditions at Room Temperature Parameters Symbols Power supply VDD (1) Input clock pulses high level Vih (1) Input clock pulse low level Vil (2) Video signal current (charge for given sample Iout time) (3)(4) Clock frequency fclk (5) Clock pulse duty cycle Dty Clock pulse high durations Tw (6) Integration time Tint Operating temperature Top Notes: (1) (2) (3) (4) (5) (6) Min. 4.5 4.0 0 Typical 5.0 5.0 0 See Note 2 Max. 5.5 VDD 0.8 Units V V V 0.1 5.0 50 100 6.5 25 50 MHz % nsec µsec ° C 29.54 Applies to both CP and SP. See Note 3 under Table 2. Although the clock frequency will operate the device at less than 100kHz, it is recommended that the device be operated above 500kHz. This recommendation is for long module length, such as the A4 size with 27 sequentially cascaded sensors. The long module at low clock rates has a long scan time. This results in a long photo integration time that generates leakage currents. The leakage currents randomly store arbitrary amounts of charges in the photo-site, contributing to the FPN in the dark. For fclk < 5.0MHz, the clock duty cycle is typically 25 percent. But at fclk = 5.0MHz or higher a typical of 50 percent is recommended. This is to keep the die-todie, fixed pattern noise (FPN), to a minimum between die transitions in CIS operation. Duty cycle is the ratio of clock pulse width over the clock period. Tint at the minimum integration time is specified with a maximum clock frequency of 6.5MHz. This specification is for a single sensor. When multiple sensors are cascaded in series, this minimum integration time increases with each additional number of sensors. AMI Semiconductor – May 06, M-20569-001 www.amis.com 4 AMIS-720639: 600dpi CIS Sensor Chip Data Sheet 6.0 Switching Characteristics at 25°C Since these image sensors are applied in a multiple-length line array with a wide range in scanning speeds, two types of output video amplifiers are used. Three video output circuits are discussed in Section 7.0. There are only two basic types of video output circuits. One is a current sensing amplifier and the other is a charge storing buffer amplifier. Simplified block diagrams show their interface connections with the image sensors. They were also used to measure the specifications given in this data sheet. The timing relationships among these two different video signals and the image sensor’s two input clocks, its SP, its shift register clock (CP) and its shift register output (EOS), are shown in two diagrams, Figure 3 and its supplement, Figure 4. The two timing diagrams are accompanied with two tables of timing symbol’s specification. These symbols graphically define the timing relationships among the waveforms in the timing diagrams; see Figure 3. The switching specifications are given in Table 6. Except for the analog video output, the rest are digital clock waveforms. Their levels are +5V CMOS compatible. The video signal, Iout, timing is specified in Table 6. Its amplitude was specified in Table 2. Figure 3: Timing Diagram of the AMIS-720639 Sensor Table 6: Timing Symbol's Definition Item Clock cycle time Clock pulse width Clock duty cycle Data setup time Data hold time Prohibit crossing time SP turn on and off EOS rise delay EOS fall delay Signal delay time to peak Signal fall time delay Notes: (1) (2) (3) (4) (5) (6) Symbol (1) to (2) tw (3) Dty tds tdh (4) Tprh (5) Tonoff terdl tefdl (6) tdtp (6) tftd Min. 154 77 25 20 20 Mean Max. 10000 50 75 20 80 75 20 80 Units ns ns % ns ns ns Note 5 ns ns ns ns Minimum is specified at the maximum clock frequency of 6.5MHz. Since the clock pulse width varies with frequency, tw will vary according to duty cycle. This minimum is specified at 6.5MHz and 50 percent duty cycle. The clock duty cycle typically is 25 percent. At 5.0MHz or higher 50 percent is recommended. This recommendation is to keep the die-to-die FPN to a minimum between die transitions in CIS operation. Tprh is the time where the SP high is prohibited. No consecutive falling clock edges are allowed during one cycle of SP. Otherwise, two SPs or more will load into the shift register for each negative going clock edge. Multiple SPs loaded into the shift register will access proportional numbers of multiple pixels simultaneously at each clock cycle. The recommended time to start and stop the SP is between two consecutive rising clock edges, indicated by the tonoff arrows. These values, tdtp and tftd, are measurements from the circuit in Figure 6, which is essentially the pulse voltage across the 50Ω resistor. This is one of the circuits employed to convert the video signal current to voltage. See the discussion on the two amplifier configurations in Section 7.0. AMI Semiconductor – May 06, M-20569-001 www.amis.com 5 AMIS-720639: 600dpi CIS Sensor Chip Data Sheet Figure 4: Supplement Timing Diagram This supplementary timing diagram, Figure 4, graphically defines the symbols used to describe the timing relationship between the waveforms at the output of the voltage buffer amplifier. The accompanying Table 7 is shown below. Cp is the same clock that is shown in Figure 3. As in the Figure 3, it is the reference for defining the video signal pulse times. Vp is the peak amplitude of the pixel when the image sensor is under light exposure. Vd is the dark level of the pixel when the image sensor has no light exposure. The reset level is used during the time when image sensor is reset to ground with an external shunting switch, SW. Refer to any of the simplified block diagrams in Section 7.0. The video line reset is active while Cp is high. The video signal charges the video line with the falling edge of Cp. The shape of the video is a typical characteristic that is exhibited when the sensor current charges the video line capacitance. It continues to rise until it becomes asymptotic to a horizontal line. However, for a clock frequency >2.0MHz, the slope does not reach the asymptotic condition. Because of this ever-charging slope, the output voltage changes with the clock frequency and its duty cycle. Hence, there is no optimum point for the video pixel sampling position. Using an edge-triggered sampling A/D with a very narrow aperture, the users of these CIS devices sample the signal as close to top of the waveform as possible. Although the optimum way is to adjust the sampling position in the application, the following sampling time given in terms of clock-time ratio will provide a rule-ofthumb in setting the sampling time. By using the relationship below, the user can place the sampling clock within an acceptable range. Tsmp ≈ [to x (1.0 – Dty) + Damp] where Dty is the clock duty cycle defined in Table 6. Table 7: Supplement Timing Symbol's Definition Item Symbol (1) Clock pulse period to (2) Video sample time tsmp (3) Amplifier group delay Damp Video fall time tvf Notes: (1) (2) (3) Min. 166 107 15 20 Mean 200 120 20 30 Max. 10000 to is the clock cycle period with minimum set with 6.0MHz. tsmp has been previously defined above, with Dty=0.5. Damp is group delay time associated with the amplifier design in Figure 7, Video Buffer Amplifier, EL2044 by Elantec. AMI Semiconductor – May 06, M-20569-001 www.amis.com 6 Units ns ns % ns AMIS-720639: 600dpi CIS Sensor Chip Data Sheet 7.0 Output Circuits for Converting the Video Signals This section discusses the test methods employed to measure the video performance characteristics of the AMIS-720639 image sensors and serves as a reference for Table 2, Notes 3 and 4. It also serves as an application note for implementing the AMIS-720639 image sensors. The output of each sensor element in the AMIS-720639 image sensor is an emitter of a source. Accordingly, when its video output line is terminated into a low impedance line, such as the current amplifier in Figure 5, the pulsed video signal currents proportional to photon integration time are produced. At a high sampling frequency rate, these video current pulse widths are limited to the pixel sampling time. Hence, the output signal voltage is limited to the signal current pulse time and amplitude. Accordingly, the usual practice is to integrate this small signal charge instead of using a sensing resistor, RFB, (see Figure 5). In this case, RFB can be changed to a capacitor with a reset switch, thus converting the circuit to a Miller Integrator. The integrator will convert the charges to proportional signal voltages. However, the disadvantage to this low-cost application is that the cost is higher than just using a single amplifier and the implementation is more complex. Another disadvantage to this application is that it will require a signal-inverting amplifier if a positive-going signal is desired. But, if kept in this simple resistor feedback form and, if the application can accept an inverted output voltage, this current-to-voltage amplifier can also implement a relatively low cost, simple circuit. Accordingly, it is introduced and discussed as one of the three amplifier structures that can be used for the video output of the AMIS-720639 device. The other amplifiers that will be discussed are configured as simple buffer amplifiers. IOUT Figure 5: Virtual Ground Amplifier The first circuit is shown in Figure 5. The signal currents from the photo-site are converted into a voltage signal through its feedback resistor, while the photo-site output sees a very close approximation to a ground because the input resistor value can be small enough to render the video line capacitance negligible, hence providing a fast responding video samples. The first method is to use the video line capacitance as a charge storing capacitance. When the selected sensor’s photo-site outputs its video signal current, the video line reset switch, SW, is open. After the video is sampled by the host system, SW closes and resets the video line and the photo-site which are presently under interrogation. Then it opens just prior to the next pixel readout. This reset is active during CP’s high state. The disadvantage of this circuit is that it has negative-going output and will have pulse shape of the current impulse that decays over a long period. Hence, it may not be desirable at low clock sample frequencies. To get around this decaying type of sampling pixels, the second circuit may be more desirable (see Figure 6). This method uses the video line as a storage medium. It uses a buffer amplifier and buffers the video line with its high input impedance. Hence, the video line effectively approaches the condition of an open circuit and becomes a capacitance that is proportional to video line length and geometry. When the photo site produces the signal current, it charges the video line capacitance and converts the output into a voltage signal. The switch, SW, is a video line reset switch. It resets the video line and the photo-site presently under interrogation, just prior to the next pixel readout. This reset is active during CP’s high state. AMI Semiconductor – May 06, M-20569-001 www.amis.com 7 AMIS-720639: 600dpi CIS Sensor Chip Data Sheet Figure 6, shows the buffer amplifier configuration. The general video wave shape and timing characteristics of this circuit are discussed in Section 6.0. Figure 4 shows the general signal wave shape and its timing relationship to the clock. Table 6 defines the symbols used in Figure 4. This circuit is generally employed in CIS applications where the clock speeds are under 5.0MHz. IOUT Figure 6: Voltage Buffer Amplifier This video line charging implementation is extensively used because of its simplicity and low cost, however, speed is limited because of the video line capacitance. For any given video line capacitance, the rate of signal charge remains the same, creating the charging slope. As the sampling frequency is increased, the pixel’s signal window decreases, reducing the amplitude and at very high frequency the video sample becomes triangular in shape. This effect is especially prevalent when longer line arrays are implemented. However, the CIS modules are cascaded structures of N Image sensors in series, forming various lengths of line arrays. It is easy to see that as N increases, the length of the video line on the PCB increases, thus increasing the video line capacitance and making it difficult to extract the signal, especially at high speeds. The third circuit is desirable for high-speed application, specifically, above 5.0MHz. Again, a buffer amplifier is employed. It uses the same buffer stage as in the second circuit. It has a positive-going output buffer amplifier, but instead of applying the video directly to the input of the amplifier, it uses a small shunt-sensing resistor to ground (see Figure 7). In this case, a small 50Ω resistor load, low enough in impedance to allow the image sensor to effectively see a virtual ground, is employed. This low impedance minimizes the effect of video line capacitance. The signal is pulsed out as an impulse current. This signal current produces a fast rising signal voltage across the resistor, then the signal decays at a slightly slower rate. At high clock rates, the time duration is short enough for the impulse current to develop an approximated square wave voltage across the resistor (see Figure 3). Iout, the signal current across the 50Ω is exemplified as a very fast rising and falling signal voltage pulse. The advantage of this circuit is that it is a positive going output signal, which eliminates the need for the second inverter stage. In addition, although it is not recommended for low frequency operation, its low impedance video line lends to high-speed operation, above 5.0MHz. Accordingly, this circuit offers the advantages of high-speed performance in addition to its cost and implementation advantages. The disadvantage to this circuit is that since it senses the output on a 50Ω resistor, the signal-to-noise is slightly less than the circuit that stores the signal charges on the video line. AMI Semiconductor – May 06, M-20569-001 www.amis.com 8 AMIS-720639: 600dpi CIS Sensor Chip IOUT Figure 7: Signal Current to Voltage Converter AMI Semiconductor – May 06, M-20569-001 www.amis.com 9 Data Sheet AMIS-720639: 600dpi CIS Sensor Chip Data Sheet 8.0 Company or Product Inquiries For more information about AMI Semiconductor, our technology and our product, visit our Web site at: http://www.amis.com North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Tel: +32 (0) 55.33.22.11 Fax: +32 (0) 55.31.81.12 Production Technical Data - The information contained in this document applies to a product in production. AMI Semiconductor and its subsidiaries (“AMIS”) have made every effort to ensure that the information is accurate and reliable. However, the characteristics and specifications of the product are subject to change without notice and the information is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify that data being relied on is the most current and complete. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. Products sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no other warranty, express or implied, and disclaims the warranties of noninfringement, merchantability, or fitness for a particular purpose. AMI Semiconductor's products are intended for use in ordinary commercial applications. These products are not designed, authorized, or warranted to be suitable for use in life-support systems or other critical applications where malfunction may cause personal injury. Inclusion of AMIS products in such applications is understood to be fully at the customer’s risk. Applications requiring extended temperature range, operation in unusual environmental conditions, or high reliability, such as military or medical life-support, are specifically not recommended without additional processing by AMIS for such applications. Copyright © 2006 AMI Semiconductor, Inc. AMI Semiconductor – May 06, M-20569-001 www.amis.com 10