REVISION NUMBER: REV A
PAGES: Page 1 of 18
DATE: 09/26/05
PI3042A
Contact Image Sensor Chip
Preliminary Data Sheet
Preliminary PI3042A datasheet
PI3042A
400DPI CIS Sensor Chip
Engineering Data Sheet
Description:
Peripheral Imaging Corporation PI3042A CIS, Contact Image Sensor is a 400 dot per inch
(dpi) resolution, linear array image sensor chip. The sensor chip is processed using PIC’s
proprietary CMOS Image Sensor Technology. Designed for cascading multiple chips in a
series, the image sensor chips, using chip-on-board process, are bonded end-to-end on a
printed circuit board (PCB). This bonding process allows users to produce variable CIS
module lengths in increments of chip array lengths. Hence, the wide variety of image reading
widths can easily be applied to the numerous document scanners, found in facsimile, as well
as, the narrow width scanners, such as, those found in check readers, lotto tickets, entrance
gate tickets and other office automation equipment which requires a wide variety of scanning
widths.
Figure 1 is a block diagram of the imaging sensor chip. Each sensor chip consists of 128 detector
elements, their associated multiplexing switches, buffers, and a chip selector. The detectors
element-to-element spacing is approximately 62.5 µm. The size of each chip without scribe lines is
8080 µm by 385 µm. Each sensor chip has 7 bonding pads. The pad symbols and functions are
described in Table 1.
8080µm
1
2
4
3
Row of 128 Sensors 125
and Video Signal
Multiplexers
126
127
128
385µm
Readout Shift Register
Buffer
SP
Chip
Select
Buffer
CP
VDD DGND
IOUT
Buffer
AGND EOS
Figure 1. PI3042A Block Diagram
SYMBOL
SP
CP
VDD
DGND
IOUT
AGND
EOS
FUNCTION
Start Pulse: Input clock to start the line scan.
Clock Pulse: Input clock to clock of the Shift Register.
Positive Supply: +5 volt supply connected to substrate.
Digital Ground: Connection topside common
Signal Current Output: Output for video signal current
Analog Ground: Connection topside common
End of Scan Pulse: Output from the shift register at end of scan.
Table 1. Pad Symbols and Functions
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Figure 2. Bonding Pad and Chip Layout
Figure 2 shows image sensor’s die dimension and the bonding pad locations for PI3042A Sensor Chip. The location is
referenced to the lower left corner of the die.
Bonding Pad Outputs Locations and Die Dimensions
Preliminary PI3042A datasheet
70 µm
380 µm
70 µm
60 µm
Page 4 of 18 Date: 09/23/05
Figure 3. Wafer Scribe Lines
880 µm
SENSOR DIE
DIMENSION
PIXEL PITCH = 62.5 µm
WAFER THICKNESS = 350 µm
Scribe width
60 µm
Figure 3 shows the wafer scribe lines bordering the PI3042A Sensor Chip. The wafer thickness is 350 µm.
Wafer Scribe Lines Bordering The Die
Preliminary PI3042A datasheet
Prelininary PI3042A datasheet
Output Circuit Of The Image Sensor
The video signal from each photo-site is connected to a common video line on the sensor.
Each photo-site is composed of a phototransistor with a series MOS switch connecting its
emitter to a common video line. The video line is connected to the pad labeled IOUT. The
photo-sites are readout upon the closure of the MOS switch, which is sequentially switched on
and off by its internal scanning shift register, see Figure 1, PI3042A Block Diagram. For the
clock & timing operation of the image sensor see Figure 7, Timing Diagram Of The PI3042A
Sensor. The photo-sensing element is the base of the phototransistor where it detects and
converts the light energy to proportional charges and stores them in its base and collector
capacitance. When the MOS switch is activated, the emitter is connected to the video line and
acts as source follower, producing an impulse current proportional to the stored charges in the
base. This current is a discrete-time analog signal output called the video pixel. The charges in
the video pixel are proportional to the light energy impinging in the neighborhood of its photosites. Figure 4, Video Pixel Output Structures, show a output structure of four photo-sites out of
128. The multiplexing MOS switch in each photo-site terminates into the output pad, IOUT,
through a common video line. As the shift register sequentially accesses each photo-site the
charges of the video pixel is sent to the IOUT where they are processed with an external signal
conversion circuit. See the follow section, Signal Conversion Circuit.
Figure 4. Video Pixel Output Structures
Signal Conversion Circuit
Figure 5, Video Output Test and Application Circuit is an example of the charge conversion that
is used in the CIS modules. It is usually bonded on the same PCB on which the image sensors
are bonded. In applications where cost is an important factor, this simple circuit provides the
cleanest technique in processing the video output. It integrates all the currents from each pixel
element onto a capacitor, CAP. It, also, sums the switch edge’s energy along with the signal
current pulses, hence minimizes the switching patterns on the video pixels. The summed
charges stored on the CAP, produce a pixel voltage. Its voltage amplitude is proportional to the
charge from the current pulse and the value of the CAP.
Page 5 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
TP
FROM
IOUT
PAD
CAP
OP-AMP
VIDEO OUT
SW
RIN
RFB
Figure 5. Video Output Circuit & Application Circuit
Since switching energies are high frequencies components, they tend to integrate to a 0 value and the
remainder adds a constant value to off-set the dark level. After the pixel is integrated, the CAP is reset
to zero volts by activating the shunt switch, SW, that connects the video line to ground prior to
accessing the following pixel element. As it is seen, depicting a typical pixel voltage waveform, in
Figure 6, Single Pixel Output Voltage, the shunt time is controlled with CP. Simultaneous to SW
activation, the pixel element storage is, also, reset to the dark reference level, hence initializing the
pixel for its integration process cycle. The signal pixels Vp(n) is referenced to its Dark Level as it is
seen in Figure 6.
Figure 6. Single Pixel Video Output
Two Test Setups For Specifications And Performance
First Setup: The standard specifications are the image sensor tests that are performed on the wafer
probe machine where each device on the wafer are tested in production. However, the data in these
measurements are measured with a clock frequency at a fixed 500 KHz. Since the pixel rate is equal
to the clock rate, the pixel rate is also at 500KHz. The specification under the section Electro-Optical
Characteristics (25o C) is the wafer probe specifications, Table 2.
Page 6 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
Second Setup: The CIS modules made with these devices operate in excess of 5.0 MHz.
Accordingly the wafer probe specifications are supplemented with high frequency clocking
performance using an A6 length modules PCB board.
Electro-Optical Characteristics (25o C)
The electro-optical characteristics of PI3042A imaging sensor chip are listed in Table 2. This is
the wafer probe specification used to tests the each die at 25o C.
Parameters
Number of Photo-elements
Pixel-to-pixel spacing
Line scanning rate
Clock frequency
Symbols
Output voltage
Output voltage non-uniformity
Dark output voltage
Dark output non-uniformity
Adjacent Pixel non-uniformity
Chip-to-chip non-uniformity
Tint (1)
Fclk (2)
Typical
128
~62.5
128/Fclk
500
Units
elements
µm
µs/line
KHz
Vpavg (3)
Up (4)
Vd (5)
Ud (6)
Upadj (7)
Ucc (8)
1.8 ± 0.35
7.5
<100
<100
<7.5
7.5
V
%
mV
mV
%
%
Notes
See note 2 for higher
clock speed.
(maximum 5 MHz)
Table 2. Electro-Optical Characteristic
Notes: (1)
(2)
(3)
Tint stands for the line scanning rate or the integration time. It is
determined by the time interval between two start pulses, where the start
pulses start the line-scan process, as soon as, CP, module clock, acquires
it and shifts it into the internal shift register. The minimum integration time
in a scan is determined by the number of pixels in the scan divided by the
clock frequency. In a CIS module it is the number of sensors times the
number of pixel in the sensor, all over the clock frequency. This time is
especially set for the wafer prober in order to calibrate the Vpavg, see
note (3).
Fclk is the device’s clock, CP, frequency and it is, also, equal to the pixel
rate. In the wafer test Fclk is set to 500 KHz. However, PIC (recently
acquired by AMIS) has been successfully mass-producing high frequency
CIS modules, using only the wafer test to qualify them. Hence, the device,
tested on an A6 size module’s PCB board at their standard high speed, is
specified.
Vpavg = Vp(n)/Npixels (average level in one line scan).
Where Vp(n) is the amplitude of nth pixel in the sensor chip and
Npixels is the total number of pixels in sensor chip. Vpavg is converted from
impulse current video pixel into a voltage output. See Figure 4, Video Pixel
Output Structure in section Output Circuit Of The Image Sensor and Figure 5,
Video Output Test and Application Circuit in section Signal Conversion Circuit on
page 6 and 7. Vpavg is calibrated for each image sensor type because of probe
card variations, as well as, the interfacing circuits to the wafer probe machine.
Page 7 of18 Date: 09/23/05
Preliminary PI3042A datasheet
(4)
(5)
(6)
(7)
(8)
Up is the uniformity specification, measured under a uniform exposing light
exposure. Up = [Vp(max) - Vpavg] / Vpavg x 100% or [Vpavg - Vp(min)] / Vpavg}
x 100%, whichever is greater.
Where
Vp(max) is the maximum pixel output voltage in the light.
Vp(min) is the minimum pixel output voltage in the light.
The pixel Vp(n) is one nth pixel in Npixels in the sensor.
Vd = Vp(n)/Npixels. Where Vp(n) is the pixels signal amplitude of the nth pixel
of the sensor. Dark is where light is off, leaving the image surface unexposed.
Ud = Vdmax – Vdmin.
Upadj = MAX[ | (Vp(n) - Vp(n+l) | / Vp(n)) x 100%. Upadj is the nonuniformity in
percentage. It is the amplitude difference between two neighboring pixels.
Ucc is the uniformity specifications, measured among the good die on the wafer.
Under uniform light exposure the sensors are measured and calculated with
following algorithm: Vpavg of all the good dies on the wafer are averaged and
assigned VGpavg. Then the die with maximum Vpavg is assigned Vpavg(max),
and the one with minimum Vpavg is assigned Vpavg(min). Then UCC =
{[Vpavg(max)-Vpavg(min)]/VGpavg}x100.
Measuring The Device’s High Frequency Performances
The PI3042A devices were tested on an A6 length standard CIS module’s PCB. Thirteen sensors
bonded on the PCB board along with its support circuits, such as, clock buffer circuits, the shunt
switch, SW, and its amplifier. The board’s video line capacitance, input capacitance of SW and input
capacitance of the amplifier become part of the CAP. The A6 PCB was selected because together
with the shunt switch, SW, and with its amplifier input, the video line had a typical value of ~100pf
including its stray from its PCB copper traces. Another reason for this selection is that the PI3042A
wafer probe tests of these devices are similarly setup using this method.
By removing RIN, the amplifier gain was set to one. Then with the total value of CAP at ~100pf the
Video Pixels Voltage amplitude gives a measure of the approximate Pixel charge. Note the amplifier is
a 1:1 buffer amplifier that serves to isolate the video line from the measuring instruments. Further note
that when the modules are produced, RIN is in the circuit as variable resistor. Then, in production of
the CIS modules, the video output amplitude, Vpavg, can be adjusted to the module’s specified level.
This factory adjust is required because the exposure is fixed (Exposure = Light Power X Time).
Example, the module’s light power is fixed and integrations time, Tint, is fixed. Note Tint is fixed in
accordance to users requirement, or specified for factory adjustment procedure during production. In
either case, the light exposure is fixed. Accordingly, to adjust the voltage amplitude to the specified
level, RIN is used.
Since the sensor response vary as a function of color, the PI3042A is measured with a Yellow-Green
LED light source, as well as, the Red (660 nm) LED light source. The light sources were selected
because historically, these LED light bars were used in the CIS industry and accepted in the low-cost
CIS markets. Today, the users are turning towards the Light Guides or Light Pipes as the costs have
been reducing and the image sensor’s technology continually improves. Yet, in low-cost applications
and, especially in mid-size volume production, the light bars and the older image sensors persistently
continues to be in demand by the scanning industry.
Page 8 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
The high frequency performance specifications are graphical curves showing the video output, Vpavg,
response to its applied light exposure. Although four exposure response graphs serve as good design
reference for the designer who have prior knowledge of the image power that will be exposing image
sensors, this is not always the case, example in designing and producing a CIS module. So to this
end, the A6 PCB board, used to characterize the light exposure to video response specification, is
enclosed in its A6 module housing and measured for its standard CIS parameters. These modules
were fabricated exactly as their production counter part except that the gain of the amplifier is set one.
The measurements were conducted with two different LED bars, one Yellow-Green and the other Red.
Video Output Response Under Exposure
The four video signal output as function of light exposure are given in Graphs, A, B, C and D. The
measurements are conducted in Black Box that enclosed the light source, the PCB and the instrument
to measure the light power. The LED source mounted at the top radiated its light energy directly on the
image sensor of the A6 PCB that is lying flat at the bottom of box. The video output was measured at
the amplifier output of the A6 PCB. The PCB setup condition is described under the section,
Measuring The Device’s High Frequency Performance. Note the gain of the amplifier is set to one.
Also the clock duty cycle is set to 25% for the 2.0 MHz clock frequency and set to 50% for the 5.0
MHz.
3.5
3
2.5
2
EXP
1.5
1
0.5
0
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
VIDEO OUTPUT Vpavg (Volts)
VIDEO OUTPUT VS EXPOSURE
PI3042A RED LED RESPONSE 2.0 Mhz
EXPOSURE (uJ/cm^2)
Graph A. A typical Video Output a as function of Light Exposure
Illuminated with a RED 660 nm LED Source with the PI3042A clocked at 2.0 MHz
Page 9 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
VIDEO OUTPUT VS EXPOSURE
PI3042A Y-G LED RESPONSE 2.0 Mhz
VIDEO OUTPUT, Vpavg
(Volts)
4
3.5
3
2.5
EXP
2
1.5
1
0.5
0
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
EXPOSURE (uJ/cm^2)
Graph B. A typical Video Output a as function of Light Exposure
Illuminated with a Y-G LED Source with the PI3042A clocked at 2.0 MHz
VIDEO OUTPUT VS EXPOSURE
PI3042A RED LED RESPONSE 5.0 Mhz
VIDEO OUTPUT, Vpavg
(Volts)
2.5
2
1.5
EXP
1
0.5
0
0.12
0.1
0.08
0.06
0.04
0.02
0
EXPOSURE (uJ/cm^2)
Graph C. A typical Video Output a as function of Light Exposure
Illuminated with a RED 660 nm LED Source with the PI3042A clocked at 5.0 MHz
Page 10 of 18 Date: 09/23/05
VIDEO OUTPUT VS EXPOSURE
PI3042A Y-G LED RESPONSE 5.0 Mhz
VIDEO OUTPUT, Vpavg
(Volts)
2.5
2
1.5
EXP
1
0.5
0
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
EXPOSURE (uJ/cm^2)
Graph D. A typical Video Output a as function of Light Exposure
Illuminated with a Y-G LED Source with the PI3042A clocked at 5.0 MHz
A6 Module with PI3042A High Frequency Specifications
RED 660 LED Bar, A6 PCB In A6 Module Housing, At 2.0 MHz CLOCK
Parameters
Symbols
Typical
Units
Remarks
(1)
Line scanning rate
Tint
835
13 dies in the scan.
µs/line
see note 1. (Bottom of
Table 6)
Clock frequency
Fclk (2)
2
MHz
Output voltage
Vpavg (3)
1.0
V
Amplifier Gain = 1.0,
see note 3
Output voltage non-uniformity
Up (4)
%
LED bar non± 20
uniformity, see note 4.
Dark output voltage
Vd (5)
<15
mV
Dark output non-uniformity
Ud (6)
<15
mV
Adjacent Pixel non-uniformity
Upadj (7)
<20
%
LED Bar Input Voltage
VLED (8)
5.0
V
LED Power Varies
greatly. See note 8.
(8)
LED Bar Input Current
ILED
90
mA
LED Power Varies
greatly. See note 8.
Table 3. Electro-Optical Characteristic at High Frequency
Page 11 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
RED 660 LED Bar, A6 PCB In A6 Module Housing, At 5.0 MHz CLOCK
Parameters
Symbols
Typical
Units
Remarks
(1)
Line scanning rate
Tint
334
13 dies in the scan. see
µs/line
note 1. (Bottom of Table 6)
Clock frequency
Fclk (2)
5
MHz
Output voltage
Vpavg (3)
0.5
V
Amplifier Gain = 1.0, see
note 3
Output voltage non-uniformity
Up (4)
%
LED bar non-uniformity,
20
see note 4.
Dark output voltage
Vd (5)
<180
mV
Dark output non-uniformity
Ud (6)
<80
mV
Adjacent Pixel non-uniformity
Upadj (7)
<20
%
LED Bar Input Voltage
VLED (8)
5.0
V
LED Power Varies greatly.
See note 8.
(8)
LED Bar Input Current
ILED
90
mA
LED Power Varies greatly.
See note 8.
Table 4. Electro-Optical Characteristic At High Frequency
Y-G LED Bar, A6 PCB In A6 Module Housing, At 2.0 MHz CLOCK
Parameters
Symbols
Typical
Units
Remarks
Line scanning rate
Tint (1)
835
13
dies
in
the scan. see
µs/line
note 1. (Bottom of Table 6)
Clock frequency
Fclk (2)
2
MHz
Output voltage
Vpavg (3)
0.4
V
Amplifier Gain = 1.0, see
note 3
(4)
Output voltage non-uniformity
Up
%
LED bar non-uniformity,
20
see note 4.
Dark output voltage
Vd (5)
<15
mV
Dark output non-uniformity
Ud (6)
<15
mV
(7)
Adjacent Pixel non-uniformity
Upadj
<20
%
LED Bar Input Voltage
VLED (8)
5.0
V
LED Power Varies greatly.
See note 8.
LED Bar Input Current
ILED (8)
380
mA
LED Power Varies greatly.
See note 8.
Table 5. Electro-Optical Characteristic At High Frequency
Y-G LED Bar, A6 PCB In A6 Module Housing, At 5.0 MHz CLOCK
Parameters
Symbols
Typical
Units
Remarks
Line scanning rate
Tint (1)
334
13 dies in the scan. see
µs/line
note 1. (Bottom of Table 6)
Page 12 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
5
0.2
MHz
V
Clock frequency
Output voltage
Fclk (2)
Vpavg (3)
Output voltage non-uniformity
Up (4)
Dark output voltage
Dark output non-uniformity
Adjacent Pixel non-uniformity
LED Bar Input Voltage
Vd (5)
Ud (6)
Upadj (7)
VLED (8)
<160
<60
<20
5.0
mV
mV
%
V
LED Bar Input Current
ILED (8)
380
mA
25
%
Amplifier Gain = 1.0, see
note 3
LED bar non-uniformity,
see note 4.
LED Power Varies greatly.
See note 8.
LED Power Varies greatly.
See note 8.
Table 6. Electro-Optical Characteristic At High Frequency
Notes: (1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Note 1 under Table 2, Electro-Optical Characteristic is valid definition, except
that in the A6 modules has 13 sensors sequentially cascaded, hence, Tint =
(13X128)/Fclk for the minimum integration time.
Fclk is the module’s clock, CP, frequency and equal to the pixel rate. Also, the
clock duty cycle is set to 25% for the 2.0 MHz clock frequency and set to 50% for
the 5.0 MHz.
Vpavg = Vp(n)/Npixels (average level in one line scan).
Where Vp(n) is the amplitude of nth pixel in one line scan of the modules.
Npixels is the total number of pixels in the module, i.e., 13 die x 128 pixels. The
amplitude of Vpavg is adjusted with RIN (which installed in the production
module) on all of CIS modules because of variations caused by the LED light
sources. The low-cost production LED’s light power are known to vary as much
as ± 30%.
Up is the uniformity specification, measured under a uniform exposing light
exposure. Up = [Vp(max) - Vpavg] / Vpavg x 100% or [Vpavg - Vp(min)] / Vpavg}
x 100%, whichever is greater.
Where
Vp(max) is the maximum pixel output voltage in the light.
Vp(min) is the minimum pixel output voltage in the light.
The pixel Vp(n) is one nth pixel in Npixels in the sensor.
In applying the Up definition, Npixels must change. It must include 13 sensors,
or 13x128 pixels.
Additionally, because the low-cost LED power variation can be high as ± 30%,
the non-uniformities may varies as much as ± 30%. Hence the uniformities are
worst because of the LED Bar CIS modules.
Vd = Vp(n)/Npixels. Where Vp(n) is the pixels signal amplitude of the nth pixel
of the sensor. Dark is where light is off, leaving the image surface unexposed.
Ud = Vdmax – Vdmin.
Upadj = MAX[ | (Vp(n) - Vp(n+l) | / Vp(n)) x 100%. Upadj is the nonuniformity in
percentage. It is the amplitude difference between two neighboring pixels.
The low-cost LED light powers are widely specified, worst case as high as ± 30%,
hense, the requirement for the Vpavg Gain Control and the wide Up specifications.
Page 13 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
Sensor’s Operational Specifications
Absolute Maximum Ratings:
Parameters
Power Supply Voltage
Power Supply Current
Input clock pulse (high level)
Input clock pulse (low level)
Operating Temperature
Operating Humidity
Storage Temperature
Storage Humidity
VDD
IDD
Vih
Vil
Top
Hop
Tstg
Hstg
Symbol
Maximum Rating
10
<2.0
Vdd + 0.5
-0.25
0 to 50
10 to 85
-25 to 75
10 to 90
Table 7. Absolute Maximum Ratings
Units
Volts
ma
Volts
Volts
o
C
RH %
o
C
RH %
Recommended Operating Conditions at Room Temperature
Parameters
Power Supply
Input clock pulses high level
Input clock pulse low level
Operating high level exposed output
Clock Frequency
Clock pulse duty cycle
Clock pulse high durations
Integration time
Operating Temperature
Symbol
VDD
Vih (1)
Vil (1)
IOUT (2)
Fclk (3)
Duty (4)
tw
Tint
Top
Min.
4.5
3.0
0
0.1
Typical
5.0
5.0
0
See note.
2.0
25
0.125
0.864
25
Max.
5.5
VDD
0.8
Units
Volts
Volts
Volts
5.0
MHz
%
sec
ms
o
C
10
50
Table 8. Recommended Operating Condition At Room Temperature
Note
(1)
(2)
(3)
(4)
Applies to both CP and SP.
The output is a current that is proportional to the charges, which are
integrated on the phototransistor’s base via photon-to-electron conversion.
For its conversion to voltage pixels see Figure 4, Video Pixel Output Structure
in section Output Circuit Of The Image Sensor.
Although the clock frequency, Fclk, will operate the device at less than
100KHz, it is recommended that the device be operated above 500KHz to
avoid complication of leakage current build-up. In applications using long CIS
module length, such as an array of image sensor > 27, increases the readout
time, i.e., increases Tint, hence, leakage current build-up occurs.
The clock duty cycle typically is normally set to 25 %. However, it can operate
with duty cycle as large as 50 %, which will allow more reset time at the
expense of video pixel readout time. At clock frequencies approaching 5.0
MHz it is recommended to use 50% duty cycle to allow more time for the
signal pixel to integrate and settle.
Page 14 of 18 Date: 09/23/05
Preliminary PI3042A datasheet
Switching Characteristics @ 25o C.
The timing relationships of the video output voltage and its two input clocks the start pulse, SP, and
the shift register clock, CP, along with the shift register EOS output clock are shown in Figure 7,
Timing Diagram Of The PI3042A Sensor. The switch timing specification for the symbols on the
timing diagram is given in Table 5, Timing Symbol's Definition below the timing diagram. The digital
clocks' levels are +5 Volts CMOS compatible. The video, IOUT, is specified in Figure 4, Video Pixel
Output in section Output Circuit Of The Image Sensor.
Figure 7. Timing Diagram Of The PI3042A Sensor
Item
Clock cycle time
Clock pulse width(1)
Clock duty cycle
Data setup time
Data hold time
Prohibit crossing time(2)
EOS rise delay
EOS fall delay
Signal delay time(3)
Signal settling time(3)
Symbol
to
tw
tds
tdh
tprh
terdl
tefdl
tdl
ts/h
Minimum
200
50
25
20
20
Mean
Maximum
10000
50
75
20
60
70
20
120
Table 9. Timing Symbol's Definition
Page 15 of 18 Date: 09/23/05
Units
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
Preliminary PI3042A datasheet
Notes (1)
(2)
(3)
The clock pulse width, tw, varies with frequency, as well as, the duty cycle.
Prohibit crossing time is to insure that no two start pulses are locked into the shift
register for any single scan time. Since the start pulse is entered into the shift
register during its active high level when the CP clock edges falls, the active high
of the start pulse is permitted only during one falling, CP, clock edges for any
given scan. Otherwise, multiple start pulses will load into the shift register.
Pixel delay times and settling time depend on the output amplifier, which is
employed. These values, tdl and ts/h, are measured with the amplifier see in
Figure 8. Typical A6 CIS Module Circuit using the PI3042A sensors. Note, the
impulse signal current out of the device has pulse width ~ 30 ns. Hence, the
faster the amplifier with a faster settling time will yield a signal video pulse with
faster rise and settle times.
Typical A6 CIS Module Circuit
See Figure 8. Typical A6 CIS Module Circuit using the PI3042A sensors. The circuit is provided as
reference to illustrate the interconnection of the PI3042A for a serially cascaded line of image sensors.
It is a typical A6 size CIS module produced by PIC. It provides the first time user with additional insight
for designing a CIS module and supplements the circuit descriptions given in the section, Signal
Conversion Circuit.
The difference is in the arrangement of the two shunt switches, U3D, and U3A. U3D is a counterpart
to SW in Figure 5. Video Output Test and Application Circuit. A DC restoration capacitor, C20,
with value of 500pf added between the shunts switch. The first, U3D, clamps the video line to
ground to reset the image sensors. Simultaneously the second, U3A, clamps the node
between C15 and amplifier input to an output reference bias voltage that is on the node
between R4 and R9. These resistors are voltage divider that sets the DC operating level of
the amplifier’s output by applying same bias voltage to both inputs of the amplifier
(See next page for the Typical A6 CIS Module Circuit.)
Page 16 of 18 Date: 09/23/05
PI3042A Preliminary
1 VOUT
2 GND
3 VDD
4 VN
5 GND
6 SP
7 GND
8 CP
9 GLED
10 VLED
VDD
C6
* 0.1uF
P1
1
2
3
4
5
6
7
8
9
10
C7
* 10uF
VDD
CONN-10PIN
C9
* 0.1uF
T12
TESTPOINT
500PF
4
3
2Z
C1
0.1UF
U2B
6
5
11
4Y
4Z
10
C13
100PF
U3B
CD4066
4E
U3C
CD4066
12
9
3Z
3E
3Y
8
74HC00
6
4
1000
5
C12
0.1uF
R5
500
C2
0.1UF
2E
1
7
U3D
CD4066
2Y
3
1
2
1Z
GND
VCC
1Y
R4
13
3
VDD
VDD
U3A
CD4066
VDD
14
1E
3K
5K
Figure 8. Typical A6 CIS Module Circuit
Page 17 of 18 Date: 09/23/05
Place C3 after S6
Place C4 after S9
T13
TESTPOINT
C5
0.1UF
DGND
EOS
6
7
SP
CP
VDD
DGND
IOUT
1
2
3
4
5
DGND
EOS
S13 PI3042A
6
7
1
2
3
4
5
S4 through S11
SP
CP
VDD
DGND
IOUT
DGND
EOS
S12 PI3042A
6
7
SP
CP
VDD
DGND
IOUT
T11
TESTPOINT
PI3042A
1
2
3
4
5
6
7
DGND
EOS
SP
CP
VDD
DGND
IOUT
T3
TESTPOINT
S3
1
2
3
4
5
DGND
EOS
6
7
74HC00
2
R3
U2A
74HC00
8
10
T2
TESTPOINT
S2 PI3042A
C11
3
2
S1 PI3042A
1
2
3
4
5
4
C10
1
9
U2C
SP
CP
VDD
DGND
IOUT
11
13
74HC00
1..5PF
R2
T1
TESTPOINT
14
12
2
-
U2D
7
6
SMT JUMPER PADS
VDD
U1
AD8051
3
+
2
50
VLED
GLED
1
1
2
V- V+
J1
7
R1
Preliminary PI3042A datasheet
______________________________________________________________________________
© 2005 Peripheral Imaging Corporation. Printed in USA. All rights reserved. Specifications are
subject to change without notice. Contents may not be reproduced in whole or in part without the
express prior written permission of Peripheral Imaging Corporation. Information furnished herein is
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Corporation for its use nor for any infringement of patents or other rights granted by implication or
otherwise under any patent or patent rights of Peripheral Imaging Corporation.
Page 18 of 18 Date: 09/23/05