austriamicrosystems D a ta S he e t A S 11 2 0 46-Segment LCD Driver 1 General Description 2 Key Features The AS1120 is an LCD direct-driver capable of driving up to 46 LCD segments with one non-multiplexed backplane. The device contains an integrated serial-to-parallel interface and generates the necessary signals to drive LCD panels. Internal synchronous backplane signal regeneration allows the device to mix different drivers with different LCDs for superior brightness stability over a wide temperature range. The device also supports external backplane signals. The AS1120 was specifically designed to easily interface with a variety of microprocessors and a wide range of LCD panel types. The AS1120 is available in a 64-pin PQFP package. ! 46-Segment LCD Driver ! Serial-to-Parallel Interface ! Integrated Oscillator w/ External R/C and Backplane Input ! Supports Alphanumeric and Bar-Graph Devices ! Two Data Transfer Configurations: - Cascade - Parallel ! Non-Multiplexed Backplane ! Very-Low Current Consumption ! Power Supply Range: 3.0 to +5.5V ! Operating Temperature Range: -40 to +85ºC ! 64-pin PQFP Package 3 Applications The device is ideal for industrial LCD systems, portablesystem displays, panel meters with wide temperature ranges, high-performance optical displays, or for any other space-limited A/D application with low power-consumption and single-supply requirements. Figure 1. Application Diagram AS1120 43 VDD +VDD XOR 46-bit LCD[0:45] 6 TEST 9 LOAD Register 46-bit 13 RESETN REXT CEXT 10 DATAIN 8 CLKIN 11 BPLIN 15 OSC www.austriamicrosystems.com Shift Register 46-bit OSC Divide by 16 Revision 1.01 7 DATAOUT 12 BPLOUT 42 VSS 14 VSSOSC 1 - 12 austriam i c r o systems AS1120 Data Sheet 4 Absolute Maximum Ratings Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 5 Electrical Characteristics on page 3 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 1. Absolute Maximum Ratings Symbol Parameter Min Max Unit VDD Positive Supply Voltage to Ground -0.3 +7.0 V 0 VDD V -200 +200 mA +150 ºC +150 ºC VIN, VOUT Digital Input and Output Voltage to Ground Comments ISCR Input Current (Latchup Immunity) TJMAX Maximum Junction Temperature TSTRG Storage Temperature Pt Package Power Dissipation (TJMAX - TAMB)/RTH 760 mW Package related ESD Electrostatic Discharge 1000 V HBM Mil-Std883E 3015.7 methods 85 % Humidity (Non-Condensing) Package Body Temperature www.austriamicrosystems.com -65 5 +250 Revision 1.01 ºC Norm: JEDEC 17 The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices” 2 - 12 austriam i c r o systems AS1120 Data Sheet 5 Electrical Characteristics Table 2. Electrical Characteristics Symbol Parameter Conditions Min Max Unit VDD Positive Supply Voltage +3.0 +5.5 V TAMB Ambient Temperature Verify that the LCD is compatible with the desired temperature range -40 85 ºC IDD Supply Current fBPL =50Hz, output not connected, TAMB = 25ºC 5 Bpfreq = fOSC/16 0.5 µA fOSC Oscillator Frequency 100 kHz CSEG Segment Capacitance 300 pF CBP Backplane Capacitance 50 nF CMOS Input Pin: TEST (VDD = 5V, TAMB = -40 to +85 ºC unless otherwise noted). VIH High Level Input Voltage VIL Low Level Input Voltage ILEAK tT 0.7 x VDD V 0.2 x VDD V Input Leakage Current ±1 µA Input Transition Time 10 ns CMOS Input with Schmitt Trigger, Pin: CLKIN, LOAD, DATAIN, BPLIN, RESETN (VDD = 5V, TAMB = -40 to +85 ºC unless otherwise noted). VTH+ Positive-Going Threshold VTL- Negative-Going Threshold ILEAK Input Leakage Current VDD = 4.5V 2.8 3.2 VDD = 5.5V 3.4 3.9 VDD = 4.5V 1.1 1.6 VDD = 5.5V 1.4 1.9 ±1 V V µA CMOS Output Pins: BPLOUT, DATAOUT (VDD = 5V, TAMB = -40 to +85 ºC unless otherwise noted). VOH High Level Input Voltage VOL Low Level Input Voltage VDD = 5V, IOH = -4mA 4.0 VDD = 3.3V, IOH = -2.8mA 2.5 V VDD = 5V, IOL = 4mA 0.4 VDD = 3.3V, IOL = 3.2mA 0.4 V CMOS Output Pin: LCDxx (VDD = 5V, TAMB = -40 to +85 ºC unless otherwise noted). VOH High Level Input Voltage VOL Low Level Input Voltage VDD = 5V, IOH = -25µA 4.0 VDD = 3.3V, IOH = -16µA 2.5 V VDD = 5V, IOL = 22µA 0.4 VDD = 3.3V, IOL = 17µA 0.4 V Oscillator Pin: OSC (VDD = 5V, TAMB = -40 to +85 ºC unless otherwise noted). VOL Low Level Output Voltage (open collector) REXT External Resistance CEXT External Capacitance fOSC Frequency VDD = 5V, IOL = 4mA 0.4 47 1/fOSC = 0.69 x REXT x CEXT V kΩ 0.3 1 nF 0.5 100 kHz Table 3. Timing Characteristics Symbol Parameter Min tCHP Time CLKIN high pulse 50 ns tCLP Time CLKIN low pulse 50 ns www.austriamicrosystems.com Revision 1.01 Max Unit 3 - 12 austriam i c r o systems AS1120 Data Sheet Table 3. Timing Characteristics Symbol Parameter Min tSDC Time setup DATAIN to CLKIN rising edge 30 ns tHDC Time hold DATAIN from CLKIN rising edge 30 ns 30 ns 30 ns tSLC Time setup LOAD to CLKIN rising edge (active low) tHLC Time hold LOAD to CLKIN rising edge (active low) 1, 2 1, 2 Max Unit tRLP Time RESETN low pulse (active low) 20000 ns tSRC Time setup RESETN to CLKIN rising edge 30 ns tDOUT Time from CLKIN falling edge to DATAOUT 10 ns 1. LOAD must be high while RESETN is active (low). 2. LOAD can stay low for more than one CLKIN cycle. Figure 2. Signal Waveform Timing tCHP tCLP CLKIN tSDC tHDC tSLC tHLC DATAIN LOAD tSRC tRLP RESETN DATAOUT tDOUT www.austriamicrosystems.com Revision 1.01 4 - 12 austriam i c r o systems AS1120 Data Sheet Shift Register 6 Detailed Description The AS1120 can drive up to 46 LCD segments and multiple AS1120 devices can be cascaded (see Figure 7 on page 8) to increase the number of LCD segments. Note: Due to the accurate delay balance between the backplane input, backplane output, and the LCD segments, it is possible to mix segments of different display crystal types. Shift Register Data accesses are made serially via pins DATAIN and CLKIN. At each CLKIN rising edge the signal present at DATAIN pin is shifted in the first bit of the internal shift register and the other bits are shifted ahead of the first bit. To cascade multiple AS1120 devices (see Figure 7 on page 8), the last bit of the internal shift register is presented at pin DATAOUT at the falling edge of the same CLKIN pulse. The LSB is entered first while MSB is the last bit to be shifted into the shift register. Note: The shift register is cleared at when the AS1120 is reset. Latch Register and Error When a signal is applied at pin LOAD, data present in the shift register is latched into the internal latch register and presented to the LCD output segments (LCD[0:45]), also passing through an XOR gate with the backplane signal (BPLIN). The XOR function is necessary to generate the appropriate signals to drive the LCD segments. Note: At reset the latch register is cleared, thus no LCD segment will be active at power-on. Synchronous Mode Data is shifted into the internal shift register at the rising edge of the CLKIN signal. To load the shift register all 46 data bits are clocked into the register at the rising edge of CLKIN (see Figure 3). The LOAD signal has to be set high for 8 CLKIN periods before the end of the 46 bits. The display will be updated at the 8th CLKIN rising edge after LOAD goes high as is shown in Figure 3. Note: During synchronous mode, a clock on BPLIN must be applied to avoid the risk of damaging the LCD crystal. Figure 3. Synchronous Mode Timing Diagram 46 CLKIN Cycles 8 CLKIN Cycles LOAD DATAIN X X LD45 LD44LD43 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Stop CLKIN BPLIN Display www.austriamicrosystems.com Update Revision 1.01 5 - 12 austriam i c r o systems AS1120 Data Sheet Asynchronous Mode Asynchronous Mode Data can be preloaded into the AS1120 shift register and then activated via a LOAD pulse. To preload the shift register the LOAD signal must stay high as all 46 data bits are clocked into the internal shift register at the rising edge of CLKIN (see Figure 4). Note: In asynchronous mode, a clock signal must be applied on pin BPLIN. Asynchronous mode does not support the use of the AS1120 internal clock. Figure 4. Timing Diagram for Preloading the Shift Register 46 CLKIN Cycles LOAD Always High LOAD DATAIN X X LD45 LD45LD45 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Stop CLKIN BPLIN To update the LCD display the LOAD signal must be held low for at least 8 periods of the clock applied at BPLIN, and CLKIN must be set to low. Note that since BPLIN is normally asynchronous in respect to LOAD, it is advisable to keep LOAD low for 8+1 BPLIN cycles. The display will be updated at the 8th BPLIN rising edge while LOAD is Low. In case of internal BPLIN generation through the internal oscillator BPLIN = fOSC/16. Figure 5. Timing Diagram for Updating the Display in Asynchronous Mode 9 BPLIN Cycles LOAD DATAIN X X CLKIN X X X X X X X X X X X X X X X CLKIN Always High BPLIN Display Update R/C Oscillator and Backplane Generation The AS1120 can generate the backplane signal using an internal R/C oscillator, or an externally generated backplane signal can be supplied. When cascading multiple AS1120 devices (see Figure 7 on page 8), only the first device should have the oscillator running; the other devices must use pin BPLIN to regenerate the backplane signal and to synchronize their LCD output segments with the common backplane. www.austriamicrosystems.com Revision 1.01 6 - 12 austriam i c r o systems AS1120 Data Sheet R/C Oscillator and Backplane Generation The selection of internal or external backplane signal (see Table 4) is initiated after RESETN is disabled – the first rising edge at pin OSC after RESETN is disabled will force pin BPLOUT to deliver the internally generated backplane signal. If there is no rising edge at pin OSC, BPLOUT will simply buffer the signal at pin BPLIN. Table 4. Backplane Source Generation Selection Mode OSC Pin BPLOUT Internal Running fOSC/16 External Tied Low BPLIN Note: The LCD should never be supplied with static signals. Verify that signals at pins BPLIN and BPLOUT are always running while VDD is supplied; note that pin BPLOUT is stopped during a reset. Internal Mode – R/C Oscillator Running (Generating the Backplane) Connect external R/C components to pin OSC as shown in Figure 1 on page 1. When an external REXT and CEXT are connected to pin OSC, a clock signal whose frequency is equal to fOSC divided by 16 will be present at pin BPLOUT. Note: Internal mode requires that pin BPLIN be connected to pin BPLOUT. The oscillation period is approximately tOSC = 1/fOSC = 0.69 x REXT x CEXT, and the error between the expected frequency and the generated frequency increases as indicated in Table 5. Table 5. Oscillator Error Rate Expected Oscillator Frequency Error 1 kHz 1% 10 kHz 5% 50 kHz 20% 100 kHz 40% Figure 6. AS1120 Clock Circuit 11 BPLIN 43 VDD D SEL Q A 15 OSC Oscillator fOSC/16 CLRN CLRN 13 RESETN 12 BPLOUT B AS1120 External Mode: R/C Oscillator Stopped (External Backplane) Connect pin OSC to VSS in order to block the internal oscillator. In this external mode, an external backplane signal should be presented at pin BPLIN, which will be regenerated and presented at pin BPLOUT. www.austriamicrosystems.com Revision 1.01 7 - 12 austriam i c r o systems AS1120 Data Sheet 7 Application Information The AS1120 can support all types of static LCD displays. Note: For proper display operation, ensure that the LCD can safely operate within the full temperature range of the AS1120 (see page 1). Figure 7. Cascaded Configuration LCD Segments LCD Segments LCD Segments LOAD LCD[0:45] LCD[0:45] +VDD 43 AS1120 +VDD VDD 43 AS1120 Register 46-Bit 6 TEST Register 46-Bit 9 LOAD 13 RESETN Shift Register 46-Bit 8 CLKIN 11 BPLIN 7 DATAOUT 12 BPLOUT OSC Divide by 16 14 VSSOSC 42 VSS www.austriamicrosystems.com 13 RESETN 10 DATAIN 8 CLKIN Shift Register 46-Bit 11 BPLIN 15 OSC Register 46-Bit 9 LOAD 13 RESETN 10 DATAIN AS1120 XOR 46-Bit 6 TEST 9 LOAD 43 VDD XOR 46-Bit 6 TEST 15 OSC +VDD VDD XOR 46-Bit +VDD LCD[0:45] 7 DATAOUT 12 BPLOUT OSC Divide by 16 14 VSSOSC 42 VSS Revision 1.01 10 DATAIN Shift Register 46-Bit 8 CLKIN 11 BPLIN 15 OSC 7 DATAOUT 12 BPLOUT OSC Divide by 16 14 VSSOSC 42 VSS 8 - 12 austriam i c r o systems AS1120 Data Sheet Pin Assignments and Markings 8 Pinout and Packaging Pin Assignments and Markings 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LCD41 LCD40 LCD39 LCD38 LCD37 LCD36 LCD35 LCD34 LCD33 LCD32 LCD31 LCD30 LCD29 LCD28 LCD27 N/C Figure 8. Pin Assignments (Top View) and Markings N/C LCD42 LCD43 LCD44 LCD45 TEST DATAOUT CLKIN LOAD DATAIN BPLIN BPLOUT RESETN VSSOSC AS1120 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 N/C LCD26 LCD25 LCD24 LCD23 VDD VSS LCD22 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 N/C LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 N/C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 OSC N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Descriptions Table 6. Pin Descriptions Pin Number 1, 16, 32, 33, 48, 49 2:5 6 7 8 9 10 11 12 13 14 Pin Name N/C LCD42:LCD45 TEST DATAOUT CLKIN LOAD DATAIN BPLIN BPLOUT RESETN VSSOSC 15 OSC 17:31 34:41 42 43 44:47 50:64 LCD0:LCD14 LCD15:LCD22 VSS VDD LCD23:LCD26 LCD27:LCD41 www.austriamicrosystems.com Description Not Connected LCD Output Segments 42:45 Test pin. This pin must be tied to pin VDD. Serial Data Output Shift Register Clock Load Strobe from Shift Register to Latch Serial Data Input Backplane Input Backplane Output Active-Low Asynchronous Reset Internal Oscillator Power Ground Oscillator Pad. a). Internal clock (see page 7) b) External clock; tied to VSSOSC LCD Output Segments 0:14 LCD Output Segments 15:22 Power Ground Positive Power Supply LCD Output Segments 23:26 LCD Output Segments 27:41 Revision 1.01 9 - 12 austriam i c r o systems AS1120 Data Sheet Package Drawings and Markings Package Drawings and Markings The devices are available in an 64-pin PQFP package. Figure 9. 64-pin PQFP Package B 0.60 Variation (mm) Min Max 0.30 0.45 ddd 0.20 Notes: 1. Controlling dimension is millimeters. 2. Pin 1 indicator may be chamfer, dot, or both. 3. Center line reference is defined by the mid-point of the center lead or the center space between leads at the package. www.austriamicrosystems.com Revision 1.01 10 - 12 austriam i c r o systems AS1120 Data Sheet 9 Ordering Information The device is available as the standard product shown in Table 7. Table 7. Ordering Information Type Description Delivery Form Package AS1120 46-Segment LCD Driver Tape and Reel PQFP44 www.austriamicrosystems.com Revision 1.01 11 - 12 austriam i c r o systems AS1120 Data Sheet Copyrights Copyright © 1997-2005, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 e-mail: [email protected] For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com austriamicrosystems www.austriamicrosystems.com Revision 1.01 – a leap ahead 12 - 12