APL6535 Two-Channel Supervisory IC Features General Description • 2.6V to 5.5V Input Voltage Range The APL6535 is a two channel supervisory IC designed • Low Quiescent Current : less than 50µA to monitor voltage supplies in mP and digital system. • High Accuracy Detection Threshold : ± 1.6% This IC can supervise any positive voltage using an • Adjustable Undervoltage Lockout for Each external resistor divider to translate to a lower voltage Supply for comparison to the internal 0.633V reference. Once • Active high PGOOD Output any VMON input falls below 0.633V the PGOOD out- • Guaranteed PGOOD Valid to Falling VCC < 1V put is pulled low, the hysteresis of the internal refer- • VMON Glitch Immunity : 30µs ence is 15mV. The PGOOD pin has an internal 20kW • Lead Free Available (RoHS Compliant) pull-up to VCC making an external pull-up resistor unnecessary. Each rail’s VMON point is independently Applications adjustable with a resistor divider. The PGOOD output is guaranteed to be valid with IC bias lower than 1V. • Graphics Cards This IC is designed to reject fast line transient glitches • Portable Battery-Powered Equipment 30ms on VMON input. The PGOOD output is an open- • µP Voltage Monitoring drain to allow ORing of multiple signals. If less than • Set-Top Boxes four voltages are being monitored, connect the unused • • VMON pins to VCC. The ENABLE input pin provides Notebook Computer for a reset of the PGOOD output when it is pulled Multiple Supply System down below 0.5V. With an internal 10mA pull-up to Pinouts VCC, it can be signaled with common logic or pulled to ground with a push button switch. APL6535 come in a miniature SOT-23-5 package. SOT-23-5 Top View Vcc 1 GND 2 PGOOD 3 5 VMON1 4 VMON2 APL6535 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw 1 ° APL6535 Ordering and Marking Information Package Code B : SOT-23-5 Temp. Range I : -40 to 85 °C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APL6535 Lead Free Code Handling Code Temp. Range Package Code A PL6535 : 535X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Pin Function Description PIN No. Name 1 VCC 3 PGOOD 2 GND 4, 5 VMON1 VMON2 I/O Supply Voltage O I Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 Description PGOOD is the AND function of all the VMON inputs being satisfied. This is an open drain output and can be pulled high to the appropriate level with an external resistor. Additionally a 20kO pull up to VCC is provided internally. Ground Connection These inputs provide for a programmable monitored voltage threshold referenced to an internal 0.633V reference. These inputs have a 30µs glitch filter to prevent transient upsets from being recognized by PGOOD. 2 www.anpec.com.tw APL6535 Block Diagram VC C(2.6~5.5V) 10uA 20kΩ VMON1 PGOOD Falling Edge Glitch Filter VMON2 1M Ω 0.633V Absolute Maximum Ratings Symbol VCC VMON1, 2 PGOOD TJ TSTG TS ESD Parameter Rating Unit Input Voltage 6.5 V All Input Pins -0.3V to V +0.3V V Output Pin -0.3V to VCC+0.3V V 150 °C -65 to +150 °C CC Maximum Junction Temperature Storage Temperature Soldering Temperature (10 seconds) Electrostatic Discharge °C 260 -3000 to 3000* 1 V Note: 1.Human body model: C=100pF, R=1500, 3 positives pulse plus 3 negative pulses. Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 3 www.anpec.com.tw APL6535 Electrical Characteristics Unless Otherwise noted these specifications apply over full temperature, Vcc = 3.3V, TJ =- 40 °C to 85°C Typical values refer to TJ =25°C Symbol Parameter Test condition APL6535 Unit Min. Typ. Max. B BIAS Supply Current (EN disable) VCC Power On VCC Power On Reset VMON > VMON_L2H VMON < VMON_H2L VMON > VMON_L2H VMON < VMON_H2L VCC low to high VCC high to low 40 400 µA 230 2000 µA 50 500 µA 50 500 µA 2.6 V 2.4 V PGpd Pull-Down Current VPGOOD=0.5V 10 mA PGpu Pull-Up Resistance 20 KΩ Supply Current (EN enable) ICC ICC VCC_L2H VCC_POR PGOOD VPGI Output Low TPG del Delay From VMON Rising VMON TPG del ENR Delay From EN Rising VCC = 1V 0 100 mV Last valid input =Vth to PG release 3 µs EN high to PG release 2 µs TPG del ENF Delay From EN Falling VMON Input VMON_H2L Falling Threshold Voltage EN low to PG pulling low 10 ns VMON _TC Falling Threshold Temperature Coeff. Hysteresis Voltage VVMON_HYS VVMON_RNG Range TFIL Glitch Filter Duration Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 TJ=25°C TJ=-40°C to 85°C VMON glitch to PGOOD low filter 4 0.623 0.633 0.643 V 100 µV/°C 15 mV 10 mV 30 µs www.anpec.com.tw APL6535 Electrical Characteristics Unless Otherwise noted these specifications apply over full temperature, Vcc = 5V, TJ =- 40 °C to 85°C Typical values refer to TJ =25°C Symbol Parameter Test condition APL6535 Unit Min. Typ. Max. B BIAS ICC Supply Current (EN Enable) ICC Supply Current (EN Disable) VCC_L2H VCC Power On VCC_POR VCC Power On Reset PGOOD PGpd Pull-Down Current PGpu Pull-Up Resistance VPGI Output Low TPG del Delay From VMON Rising VMON TPG del ENR Delay From EN Rising TPG del ENF Delay From EN Falling VMON Input VMON_H2L Falling Threshold Voltage Falling Threshold VMON_TC Temperature Coeff. VVMON_HYS Hysteresis Voltage VVMON_RNG Range TFIL Glitch Filter Duration Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 VMON > VMON_L2H VMON < VMON_H2L VMON > VMON_L2H VMON < VMON_H2L VCC low to high VCC high to low 50 500 µA 230 2000 µA 60 600 µA 60 600 µA 2.6 V 2.4 V VPGOOD=0.5V 10 20 0 KΩ 100 mV 5 µs 2 10 µs ns VCC = 1V Last valid input = Vth to PG release EN high to PG release EN low to PG pulling low TJ=25°C mA 0.623 0.633 0.643 V TJ=-40°C to 85°C 100 µV/°C VMON glitch to PGOOD low filter 15 10 30 mV mV µs 5 www.anpec.com.tw APL6535 Application Circuit 3.3V APL6535 Vcc PGOOD Output 1 V CC *10K 10kΩ 2 GND 3 PGOOD 1uF 22kΩ VMON1 5 VMON2 4 4.7kΩ 0.47uF 12V 1.5kΩ * Optional Timing Diagram Vth VMON TFIL <TFIL PGOOD EN Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 Vth 6 www.anpec.com.tw APL6535 Typical Characteristics Supply Current vs. Supply Voltage Supply Current vs. Temperature 400 70 VMON>VMON_L2H 60 VMON<VMON_H2L 300 Supply Current(µA) Supply Current(µA) 350 250 200 150 100 VMON>VMON_L2H VCC=5V 50 40 VCC=3.3V 30 20 10 50 0 0 2.6 3.1 3.6 4.1 4.6 5.1 5.6 -40 -20 0 Supply Voltage(V) 20 40 60 80 100 120 Temperature(°C) VMON_H2L vs. Temperature VMON Threshold vs. Supply Voltage 0.638 0.651 0.636 VCC=5V 0.648 VMON Threshold(V) 0.634 VMON_H2L(V) 0.632 0.630 0.628 VCC=3.3V 0.626 0.624 0.622 VMON_L2H 0.645 0.642 0.639 0.636 VMON_H2L 0.633 0.620 0.618 0.630 -40 -20 0 20 40 60 80 100 120 2.6 Copyright ANPEC Electronics Corp. Rev. 3.6 4.1 4.6 5.1 5.6 Supply Voltage(V) Temperature(°C) Rev. A.1 - May., 2005 3.1 7 www.anpec.com.tw APL6535 Typical Characteristics (Cont.) EN High to PGOOD VMON High to PGOOD VCC=3.3V VCC=3.3V EN(2V/div) VMON(1V/div) PGOOD(2V/div) PGOOD(2V/div) Time(1us/div) Time(4us/div) EN Low to PGOOD VMON Low to PGOOD VCC=3.3V VCC=3.3V EN(2V/div) VMON(1V/div) PGOOD(2V/div) PGOOD(2V/div) Time(10ns/div) Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 Time(20µs/div) 8 www.anpec.com.tw APL6535 Application Information PGOOD The APL6535 is a four channel supervisory IC designed to monitor multiple voltages greater than 0.7V. This IC is suitable for both microprocessors or industrial system applications. Once biased to 2.6V and enabled the IC continuously monitors from one to four voltages independently through external resistor dividers comparing each VMON pin voltage to an internal 0.633V reference. The PGOOD output is an opendrain to allow ORing of the signals and interfacing to a wide range of logic levels. If less than four voltages are being monitored, connect the unused VMON pins to V CC. The PGOOD pin has an internal 20kW pull-up to V CC making an external pull-up resistor unnecessary. Falling Edge Glitch Filter Once any VMON input falls below 0.633V the PGOOD output is pulled low, the VMON inputs are designed to reject fast transients (30us). Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 9 www.anpec.com.tw APL6535 Package Information SOT-23-5 e1 5 4 E1 1 E 3 2 e b D A2 A a A1 Dim A A1 A2 b D E E1 e e1 L L1 L2 N α L Millimeters Min. 0.95 0.05 0.90 0.30 2.8 2.6 1.5 Inches Max. 1.45 0.15 1.30 0.50 3.00 3.00 1.70 Min. 0.037 0.002 0.035 0.011 0.110 0.102 0.059 0.35 0.55 0.014 0.20 BSC 0.5 0.022 0.008 BSC 0.7 0.020 10° 0° 5 0° Max. 0.057 0.006 0.051 0.019 0 . 118 0 . 118 0.067 0.037BSC 0.07 4BSC 0.95BSC 1.90BSC Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 L2 L1 0.028 5 10 10° www.anpec.com.tw APL6535 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Time Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 11 (mm) www.anpec.com.tw APL6535 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s 3 3 Package Thickness Volume mm Volume mm <350 ≥350 <2.5 mm 240 +0/-5°C 225 +0/-5°C ≥2.5 mm 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA Carrier Tape & Reel Dimensions t D P Po E P1 Bo F W Ko Ao Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 D1 12 www.anpec.com.tw APL6535 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application SOT-23-5 A B C J 178±1 72 ± 1.0 F D D1 Po 3.5 ± 0.05 1.5 +0.1 1.5 +0.1 4.0 ± 0.1 13.0 + 0.2 2.5 ± 0.15 T1 T2 P E 1.5± 0.3 W 8.0+ 0.3 - 0.3 8.4 ± 2 4 ± 0.1 1.75± 0.1 P1 Ao Bo Ko t 3.2± 0.1 1.4± 0.1 0.2±0.03 2.0 ± 0.1 3.15 ± 0.1 (mm) Cover Tape Dimensions Application SOT- 23 Carrier Width 8 Cover Tape Width 5.3 Devices Per Reel 3000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 13 www.anpec.com.tw