AVAGO ADNB-3532

ADNB-3532
Low Power LED Integrated Slim Mouse Sensor
Data Sheet
Description
Features
The ADNB-3532 LED mouse bundle is a small form
factor (SFF) LED illuminated navigation system. The
bundle consists of an integrated chip-on-board (COB),
LED mouse sensor ADNS-3530 and a SFF lens ADNS3150-001.
• Low power architecture
• Small form factor
• Surface mount technology (SMT) device
• Self-adjusting power-saving modes for longest battery
life
• High speed motion detection up to 20 ips and 8 G
• Self-adjusting frame rate for optimum performance
• Motion detect pin output
• Internal oscillator – no clock input needed
• Selectable 500 and 1000 cpi resolution
• Wide operating voltage: 2.7 V - 3.6 V nominal
• Four wire serial port
• Minimal number of passive components
• Integrated chip-on-board LED
The ADNS-3530 is a low-power optical navigation sensor. It has a new, low-power architecture and automatic
power management modes, making it ideal for batteryand power-sensitive applications such as cordless input
devices.
The ADNS-3530 is capable of high-speed motion
detection — up to 20 ips and 8 G. In addition, it has
an on-chip oscillator and integrated LED to minimize
external components.
The ADNS-3530, along with the ADNS-3150-001 lens,
forms a complete and compact mouse tracking system.
There are no moving parts which means high reliability and less maintenance for the end user. In addition,
precision optical alignment is not required, facilitating
high volume assembly.
The bundle sensor is programmed via registers through
a four-wire serial port. It is packaged in a 16 I/O surface
mountable package.
Applications
• Optical mice
• Optical trackballs
• Integrated input devices
• Battery-powered input device
Theory of Operation
The ADNS-3530 is based on Optical Navigation Technology, which measures changes in position by optically
acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of
movement.
The ADNS-3530 contains an Image Acquisition System
(IAS), a Digital Signal Processor (DSP), and a four wire
serial port.
The IAS acquires microscopic surface images via the lens
and illumination system. These images are processed
by the DSP to determine the direction and distance
of motion. The DSP calculates the Dx and Dy relative
displacement values.
An external microcontroller reads the Dx and Dy information from the sensor serial port. The microcontroller
then translates the data into PS2, USB, or RF signals
0before sending them to the host PC or game console.
Bundle Part
Number
Part Number
Description
ADNB-3532
ADNS-3530
Integrated sensor
ANDS-3150-001
Small form factor lens
Pinout of ADNS-3530 Optical Mouse Sensor
Pin
Name
Description
1
MISO
Serial Data Output (Master In/Slave
Out)
2
SCLK
Serial Clock Input
3
MOSI
Serial Data Input (Master Out/Slave
In)
4
MOTION
Motion Detect (Active Low Output)
5
XY_LED
LED Control
6
LED_GND
Ground for LED Current
7
SHTDWN
Shutdown (Active High Input)
8
LED (+)
LED Positive Terminal
9
LED (-)
LED Negative Terminal
10
AVDD
Analog Supply Voltage
11
GND
Ground
12
GND
Ground
13
AGND
Analog Ground
14
VDD
Supply Voltage
15
GND
Ground
16
NCS
Chip Select (Active Low Input)
LED (-) 9
8 LED (+)
AVDD 10
7 SHTDWN
GND 11
6 LED-GND
GND 12
5 XY-LED
AGND 13
VDD 14
3 MOSI
GND 15
2 SCLK
NCS 16
1 MISO
Figure 1. Package outline drawing (top view)
4 MOTION
12.90 ± 0.20
(0.508 ± 0.008)
PAD #1
1.00
1.60
(0.039) (0.063)
4.80
(0.189)
9.60 ± 0.20
(0.378 ± 0.008) CL
8.40
(0.331)
0.80
(0.031)
0.50
(0.020)
1.19
(0.047)
NOTES:
1. DIMENSIONS IN MILLIMETERS (INCHES).
2. COPLANARITY OF PADS: ± 0.1 mm
3. CUMULATIVE PITCH TOLERANCE: ± 0.15 mm
4. PAD PITCH TOLERANCE: ± 0.1 mm
5. MAXIMUM FLASH: + 0.2 mm
6. DIMENSIONAL TOLERANCE (UNLESS OTHERWISE
STATED): ± 0.15 mm
PROTECTIVE
KAPTON TAPE
GUIDE HOLE B
OPTICAL CENTER
4.21
(0.166)
CL
5.61
(0.221)
GUIDE HOLE A
1.95
(0.077)
5.89
(0.232)
10.35
(0.408)
PAD #1
0.85
(0.033)
1.35
(0.053)
9.50
(0.374)
1.70
(0.067)
Figure 2. Package outline drawing
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.
Overview of Optical Mouse Sensor Assembly
Avago Technologies provides an IGES file drawing describing the base plate molding features for lens and
PCB alignment.
The components interlock as they are mounted onto
defined features on the base plate.
The ADNS-3530 sensor is designed for surface mounting
on a PCB, looking down. There is an aperture stop and
features on the package that align to the lens.
The ADNS-3150-001 lens provides optics for the imaging of the surface as well as illumination of the surface
at the optimum angle. Features on the lens align it to
the sensor and base plate.
0.53
(0.21)
0.53
(0.21)
1.60 (x 14)
(0.063)
0
5.89
(0.232)
PAD #1
0.45
(0.18)
OPTICAL
CENTER
0
0.45
(0.18)
4.20
(0.165)
8.40
(0.331)
Figure 3. Recommended customer’s PCB PADOUT and spacing
CUSTOMER PCB
ADNS-3530
ADNS-3150-001
Figure 4. 2D assembly drawing of ADNB-3532
MOUSE BOTTOM COVER
ADNS-3530
ADNS-3150-001
CUSTOMERSUPPLIED
BASE PLATE
Figure 5a. Exploded top view
ADNS-3530
ADNS-3150-001
CUSTOMERSUPPLIED
BASE PLATE
Figure 5b. Exploded bottom view
PCB Assembly Considerations
1.Surface mount the sensor and all other electrical components into PCB.
2.Reflow the entire assembly in a no-wash solder
process.
3.Place the lens onto the base plate. Care must be taken
to avoid contaminating or staining the lens.
4.Remove the protective kapton tape from optical aperture of the sensor and LED. Care must be taken to
keep contaminants from entering the aperture. Recommend not to place the PCB facing up during the entire mouse assembly process. Recommend to hold the
PCB first vertically for the kapton removal process.
5.Insert PCB assembly over the lens onto the base plate
aligning post to retain PCB assembly. The lens piece
has alignment posts which will mate with the alignment holes on the sensor aperture.
6.The optical position reference for the PCB is set by the
base plate and lens. Note that the PCB motion due to
button presses must be minimized to maintain optical
alignment.
BOTTOM OF PCB TO
BOTTOM MATING
SURFACE OF LENS
2.28
(0.09)
7.Install mouse top case. There MUST be a feature in the
top case to press down onto the sensor to ensure the
sensor and lens components are interlocked to the
correct vertical height.
Design Considerations for Improved ESD Performance
For improved electrostatic discharge performance, typical creepage and clearance distance are shown in the
table below. Assumption: base plate construction as per
the Avago Technologies supplied IGES file and ADNS3150-001 lens.
Typical Distance
Millimeters
Creepage
0.6
Clearance
2.76
Note that the lens material is polycarbonate and therefore, cyanoacrylate-based adhesives or other adhesives
that may damage the lens should NOT be used.
SENSOR
CUSTOMER'S
BASE PLATE
CUSTOMER'S PCB
3.25
BOTTOM OF PCB TO
NAVIGATION SURFACE (0.13)
2.50 DIE TO NAVIGATION
(0.10) SURFACE
0.29
LENS
(0.01)
BOTTOM OF LENS
TO NAVIGATION SURFACE
0.97
(0.04)
BOTTOM MATING SURFACE
OF LENS TO NAVIGATION SURFACE
NAVIGATION
SURFACE
Figure 6a. Sectional view of PCB assembly
LED DIE
SENSOR DIE
CUSTOMER'S PCB
CUSTOMER'S BASE PLATE
LENS
SENSOR PCB
NAVIGATION
SURFACE
Figure 6b. Sectional view of PCB assembly highlighting optical mouse components
Note: The supply and ground paths should be laid out using a star topology.
Figure 7. Schematic diagram for interface between ADNS-3530 and microcontroller
Regulatory Requirements
• Passes FCC B and worldwide analogous emission limits
when assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
• Passes IEC-1000-4-3 radiated susceptibility level when
assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
• Passes EN61000-4-4/IEC801-4 EFT tests when assembled
into a mouse with shielded cable and following Avago
Technologies recommendations.
• UL flammability level UL94 V-0.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Storage Temperature
TS
-40
85
°C
260
°C
3.7
V
2
kV
All pins, human body model MIL
883 Method 3015
VDD + 0.5
V
All pins
20
mA
All pins
Lead Solder Temperature
Supply Voltage
VDD
-0.5
ESD (Sensor Only)
Input Voltage
VIN
Latchup Current
Iout
-0.5
Notes
For 10 seconds, 1.6 mm below
seating plane
Recommended Operating Conditions
Parameter
Symbol
Minimum Typical Maximum Units
Operating Temperature
TA
0
40
°C
Power Supply Voltage
VDD
2.7
3.6
volts
Including noise
Power Supply Rise Time
VRT
0.001
100
ms
0 to 2.8 V
Supply Noise (Sinusoidal)
VNA
100
mVp-p
10 kHz - 50 MHz
1
MHz
Active drive, 50% duty cycle
+0.1
mm
Result in 0.1 mm DOF
Serial Port Clock Frequency fSCLK
Distance from Lens
Reference Plane to Surface
Z
-0.1
0.97
Speed
S
20
in/sec
Acceleration
A
8
G
CUSTOMER'S PCB
SENSOR
0.97
(0.04)
LENS
Figure 8. Distance from lens reference plane to surface
NAVIGATION
SURFACE
Notes
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25°C, VDD3 = 2.85 V.
Parameter
Motion Delay After Reset
Symbol
tMOT-RST
Shutdown
Wake from Shutdown
tSHTDWN
tWAKEUP
Forced Rest Enable
Wake from Forced Rest
tREST-EN
tREST-DIS
MISO Rise Time
MISO Fall Time
MISO Delay After SCLK
tr-MISO
tf-MISO
tDLY-MISO
MISO Hold Time
MOSI Hold Time
thold-MISO
thold-MOSI
0.5
200
MOSI Setup Time
SPI Time Between Write
Commands
tsetup-MOSI
tSWW
120
30
ns
µs
SPI Time Between Write and tSWR
Read Commands
20
µs
SPI Time Between Read and tSRW
Subsequent Commands
tSRR
500
ns
SPI Read Address-Data
Delay
tSRAD
4
µs
NCS Inactive After Motion
Burst
NCS to SCLK Active
tBEXIT
500
ns
tNCS-SCLK
120
ns
SCLK to NCS Inactive
(for Read Operation)
SCLK to NCS Inactive
(for Write Operation)
NCS to MISO High-Z
tSCLK-NCS
120
ns
tSCLK-NCS
20
us
MOTION Rise Time
MOTION Fall Time
SHTDWN Pulse Width
Transient Supply Current
tr-MOTION
tf-MOTION
tP-SHTDWN
IDDT
Min.
Typical
Max.
23
Units
ms
50
ms
s
1
1
s
s
300
300
120
ns
ns
ns
1/fSCLK
µs
ns
1
150
150
tNCS-MISO
150
150
500
ns
300
300
ns
ns
s
mA
1
45
Notes
From POWER_UP_RESET register write
to valid motion, assuming motion is
present
From SHTDWN pin active to low current
From SHTDWN pin inactive to valid
motion. Notes: A RESET must be asserted
after a shutdown. Refer to section “Notes
on Shutdown and Forced Rest,” also note
tMOT-RST
From RESTEN bits set to low current
From RESTEN bits cleared to valid
motion
CL = 100 pF
CL = 100 pF
From SCLK falling edge to MISO data
valid, no load conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK
rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first
data byte, to rising SCLK for last bit of
the second data byte
From rising SCLK for last bit of the first
data byte, to rising SCLK for last bit of
the second address byte
From rising SCLK for last bit of the first
data byte, to falling SCLK for the first
bit of the address byte of the next
command
From rising SCLK for last bit of the
address byte, to falling SCLK for first bit
of data being read
Minimum NCS inactive time after motion
burst before next SPI usage
From NCS falling edge to first SCLK rising
edge
From last SCLK rising edge to NCS rising
edge, for valid MISO data transfer
From last SCLK rising edge to NCS rising
edge, for valid MOSI data transfer
From NCS rising edge to MISO high-Z
state
CL = 100 pF
CL = 100 pF
Max supply current during a VDD ramp
from 0 to 2.8 V
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25°C, VDD =2.85 V.
Parameter
DC Supply Current
in Various Modes
Symbol
IDD_RUN
IDD_REST1
IDD_REST2
IDD_REST3
Min.
Typical
3.6
0.6
0.15
0.04
Peak Supply Current
Shutdown Supply
Current
IDDSHTDWN
Input Low Voltage
Input High Voltage
Input Hysteresis
Input Leakage
Current
Output Low Voltage
VIL
VIH
VI_HYS
Ileak
1
Units
mA
Notes
Average current, including LED
current. No load on MISO, MOTION.
mA
12
µA
0.5
±10
V
V
mV
µA
0.7
V
Peak current in 100 kHz bandwidth,
including LED current.
SCLK, MOSI and NCS must be within
300 mV of GND or VDD. SHTDWN
must be within 300 mV of VDD.
SCLK, MOSI, NCS, SHTDWN
SCLK, MOSI, NCS, SHTDWN
SCLK, MOSI, NCS, SHTDWN
Vin = VDD - 0.6 V, SCLK, MOSI, NCS,
SHTDWN
Iout = 1 mA, MISO, MOTION
10
V
pF
Iout = -1 mA, MISO, MOTION
MOSI, NCS, SCLK, SHTDWN
VDD – 0.6
100
±1
VOL
Output High Voltage VOH
Input Capacitance
Cin
Max.
10
1.8
0.40
0.15
40
VDD – 0.7
ADNS-3530 RESOLUTION
700
RESOLUTION (CPI)
600
500
WHITE PAPER
MANILA
WHITE FORMICA
BLACK COPY
WHITE PINE
400
300
200
100
0
0.77 0.87 0.97 1.07 1.17 1.27 1.37 1.47 1.57 1.67 1.77 1.87 1.97
Z-HEIGHT (mm)
Figure 9. Mean resolution vs. Z
TYPICAL PATH DEVIATION
LARGEST SINGLE PERPENDICULAR DEVIATION FROM A STRAIGHT LINE AT 45 DEGREES
PATH LENGTH = 4 INCHES; SPEED = 6 ips; RESOLUTION = 1000 cpi
90
MAXIMUM DISTANCE
(MOUSE COUNT)
70
WHITE PAPER
MANILA
WHITE FORMICA
WHITE PINE
BLACK COPY
50
30
10
-10
0.77 0.87 0.97 1.07 1.17 1.27 1.37 1.47 1.57 1.67 1.77 1.87 1.97
DISTANCE FROM LENS REFERENCE PLANE
TO NAVIGATION SURFACE (mm)
Figure 10. Typical path deviation vs. Z distance (mm)
Relationship of mouse count to distance = m (mouse count)/n (cpi). E.g.: Deviation of 7 mouse count = 7/1000 = 0.007 inch, where m = 7, n = 1000.
10
Power Management Modes
The lines that comprise the SPI port:
The ADNS-3530 has three power-saving modes. Each
mode has a different motion detection period, affecting
response time to mouse motion (Response Time). The
sensor automatically changes to the appropriate mode,
depending on the time since the last reported motion
(Downshift Time). The parameters of each mode are
shown in the following table.
SCLK: Clock input. It is always generated by the
master (the microcontroller).
Mode
Response Time
(Nominal)
Downshift Time
(Nominal)
Rest 1
16.5 ms
237 ms
Rest 2
82 ms
8.4 s
Rest 3
410 ms
504 s
Motion Pin Timing
The motion pin is a level-sensitive output that signals
the microcontroller when motion has occurred. The motion pin is lowered whenever the motion bit is set; in
other words, whenever there is data in the Delta_X or
Delta_Y registers. Clearing the motion bit (by reading
Delta_Y and Delta_X, or writing to the Motion register)
will put the motion pin high.
LED Mode
For power savings, the LED will not be continuously on.
ADNS-3530 will flash the LED only when needed.
Synchronous Serial Port
The synchronous serial port is used to set and read
parameters in the ADNS-3530, and to read out the
motion information.
The port is a four wire serial port. The host microcontroller
always initiates communication; the ADNS-3530 never
initiates data transfers. SCLK, MOSI, and NCS may be
driven directly by a microcontroller. The port pins may
be shared with other SPI slave devices. When the NCS
pin is high, the inputs are ignored and the output is tristated.
11
MOSI: Input data. (Master Out/Slave In)
MISO: Output data. (Master In/Slave Out)
NCS: Chip select input (active low). NCS needs to
be low to activate the serial port; otherwise,
MISO will be high Z, and MOSI & SCLK will be
ignored. NCS can also be used to reset the
serial port in case of an error.
Chip Select Operation
The serial port is activated after NCS goes low. If NCS
is raised during a transaction, the entire transaction is
aborted and the serial port will be reset. This is true for
all transactions. After a transaction is aborted, the normal
address-to-data or transaction-to-transaction delay is
still required before beginning the next transaction. To
improve communication reliability, all serial transactions
should be framed by NCS. In other words, the port
should not remain enabled during periods of non-use
because ESD and EFT/B events could be interpreted as
serial communication and put the chip into an unknown
state. In addition, NCS must be raised after each burstmode transaction is complete to terminate burst-mode.
The port is not available for further use until burst-mode
is terminated.
Write Operation
Write operation, defined as data going from the
microcontroller to the ADNS-3530, is always initiated
by the microcontroller and consists of two bytes. The
first byte contains the address (seven bits) and has a “1”
as its MSB to indicate data direction. The second byte
contains the data. The ADNS-3530 reads MOSI on rising
edges of SCLK.
NCS
1
2
3
4
5
6
7
8
9
10
11
12
13
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
14
15
16
1
2
SCLK
1
MOSI
D2
D1
D0
1
MISO
MOSI DRIVEN BY MICRO-CONTROLLER
Figure 11. Write operation
SCLK
MOSI
thold, MOSI
tsetup, MOSI
Figure 12. MOSI setup and hold time
Read Operation
A read operation, defined as data going from the ADNS3530 to the microcontroller, is always initiated by the
microcontroller and consists of two bytes. The first byte
contains the address, is sent by the microcontroller over
MOSI, and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-3530 over MISO. The sensor outputs MISO bits on
falling edges of SCLK and samples MOSI bits on every
rising edge of SCLK.
NCS
SCLK
CYCLE #
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
8
9
10
11
12
13
14
15
16
SCLK
1
MOSI
A0
D7
MISO
tSRAD DELAY
Figure 13. Read operation
SCLK
tDLY-MISO
MISO
tHOLD-MISO
D0
Figure 14. MISO delay and hold time
12
D6
D5
D4
D3
D2
D1
D0
A6
NOTE: The 0.5/fSCLK minimum high state of SCLK is also
the minimum MISO data hold time of the ADNS-3530.
Since the falling edge of SCLK is actually the start of the
next read or write command, the ADNS-3530 will hold
the state of data on MISO until the falling edge of SCLK.
Required Timing Between Read and Write
Commands
There are minimum timing requirements between read
and write commands on the serial port.
tSWW
SCLK
ADDRESS
DATA
ADDRESS
WRITE OPERATION
DATA
WRITE OPERATION
Figure 15. Timing between two write commands
If the rising edge of the SCLK for the last data bit of the
second write command occurs before the required delay
(tSWW), then the first write command may not complete
correctly.
tSWR
•••
SCLK
ADDRESS
DATA
ADDRESS
•••
WRITE OPERATION
NEXT READ OPERATION
Figure 16. Timing between write and read commands
If the rising edge of SCLK for the last address bit of the
read command occurs before the required delay (tSWR),
the write command may not complete correctly.
tSRW & tSRR
tSRAD
•••
SCLK
ADDRESS
DATA
ADDRESS
•••
READ OPERATION
Figure 17. Timing between read and either write or subsequent
read commands
13
NEXT READ
or WRITE OPERATION
During a read operation SCLK should be delayed at least
tSRAD after the last address data bit to ensure that the
ADNS-3530 has time to prepare the requested data. The
falling edge of SCLK for the first address bit of either the
read or write command must be at least tSRR or tSRW
after the last SCLK rising edge of the last data bit of the
previous read operation.
Burst Mode Operation
Burst mode is a special serial port operation mode that
may be used to reduce the serial transaction time for
a motion read. The speed improvement is achieved
by continuous data clocking from multiple registers
without the need to specify the register address, and
by not requiring the normal delay period between data
bytes.
Shutter_Lower and Maximum_Pixel registers in that
order. The burst transaction can be terminated after the
first three bytes of the sequence are read by bringing
the NCS pin high. After sending the register address, the
microcontroller must wait tSRAD and then begin reading
data. All data bits can be read with no delay between
bytes by driving SCLK at the normal rate. The data is
latched into the output buffer after the last address bit
is received. After the burst transmission is complete, the
microcontroller must raise the NCS line for at least tBEXIT
to terminate burst mode. The serial port is not available
for use until it is reset with NCS, even for a second burst
transmission.
Burst mode is activated by reading the Motion_Burst
register. The ADNS-3530 will respond with the contents
of the Motion, Delta_Y, Delta_X, SQUAL, Shutter_Upper,
tSRAD
•••
SCLK
MOTION_BURST REGISTER ADDRESS
READ FIRST BYTE
•••
FIRST READ OPERATION
READ SECOND BYTE
READ THIRD BYTE
Figure 18. Motion burst timing
Notes on Power-Up
The ADNS-3530 does not perform an internal power
up self-reset; the POWER_UP_RESET register must be
written every time power is applied. The appropriate
sequence is as follows:
1. Apply power
2. Drive NCS high, then low to reset the SPI port
3. Write 0x5a to register 0x3a
4. Read from registers 0x02, 0x03 and 0x04 (or read
these same three bytes from burst motion register
0x42) one time regardless the state of the motion
pin.
During power-up there will be a period of time after the
power supply is high but before any clocks are available.
The table below shows the state of the various pins
during power-up and reset.
State of Signal Pins After VDD is Valid
Pin
On Power-Up
NCS High Before Reset
NCS Low Before Reset
After Reset
NCS
Functional
High
Low
Functional
MISO
Undefined
Undefined
Functional
Depends on NCS
SCLK
Ignored
Ignored
Functional
Depends on NCS
MOSI
Ignored
Ignored
Functional
Depends on NCS
XY_LED
Undefined
Undefined
Undefined
Functional
MOTION
Undefined
Undefined
Undefined
Functional
SHTDWN
Must Be Low
Must Be Low
Must Be Low
Functional
14
Notes on Shutdown and Forced Rest
The ADNS-3530 can be set in Rest mode through the
Configuration_Bits register (0x11). This is to allow for
further power savings in applications where the sensor
does not need to operate all the time.
Pin
SHTDWN active
NCS
Functional*
MISO
Undefined
SCLK
Undefined
The ADNS-3530 can be set in Shutdown mode by asserting the SHTDWN pin. For proper operation, SHTDWN pulse width must be at least tSHTDWN. Shorter pulse
widths may cause the chip to enter an undefined state.
In addition, the SPI port should not be accessed when
SHTDWN is asserted. (Other ICs on the same SPI bus can
be accessed, as long as the sensor’s NCS pin is not asserted.) The table below shows the state of various pins
during shutdown. After deasserting SHTDWN, a full reset
must be initiated. Wait tWAKEUP before accessing the SPI
port, then write 0x5A to the POWER_UP_RESET register.
Any register settings must then be reloaded.
MOSI
Undefined
XY_LED
Low Current
MOTION
Undefined
*NCS pin must be held to 1 (high) if SPI bus is shared with other
devices. It can be in either state if the sensor is the only device in
addition to the microcontroller.
Note: There are long wakeup times from shutdown and forced Rest.
These features should not be used for power management during
normal mouse motion.
Registers
The ADNS-3530 registers are accessible via the serial
port. The registers are used to read motion data and
status as well as to set the device configuration.
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
0x10
0x11
0x12-0x2d
0x2e
0x2f-0x38
0x3a
0x3b-0x3d
0x3e
0x3f
0x42
15
Register
Product_ID
Revision_ID
Motion
Delta_Y
Delta_X
SQUAL
Shutter_Upper
Shutter_Lower
Maximum_Pixel
Pixel_Sum
Minimum_Pixel
Pixel_Grab
CRC0
CRC1
CRC2
CRC3
Self_Test
Configuration_Bits
Reserved
Observation
Reserved
POWER_UP_RESET
Reserved
Inverse_Revision_ID
Inverse_Product_ID
Motion_Burst
Read/Write
R
R
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
W
R/W
Default Value
0x0D
0x02
0x00
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
R/W
Any
0x03
W
R
R
R
0xFD
0xF2
Any
Product_ID
Access: Read
Address: 0x00
Reset Value: 0x0D
Bit
Field
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
Data Type: 8-bit unsigned integer
USAGE: This register contains a unique identification
assigned to the ADNS-3530. The value in this
register does not change; it can be used to
verify that the serial communications link is
functional.
Revision_ID
Access: Read
Address: 0x01
Reset Value: 0x02
Bit
Field
7
6
5
4
3
2
1
0
RID7
RID6
RID5
RID4
RID3
RID2
RID1
RID0
Data Type: 8-bit unsigned integer
USAGE: This register contains the IC revision. It is subject
to change when new IC versions are released.
Motion Access: Read/Write
Bit
Field
Address: 0x02
Reset Value: 0x00
7
6
5
4
MOT
PIXRDY
PIXFIRST
OVF
USAGE: Register 0x02 allows the user to determine if
motion has occurred since the last time it was
read. If the MOT bit is set, then the user should
read registers 0x03 and 0x04 to get the accumulated motion. Read this register before reading the Delta_Y and Delta_X registers.
Writing anything to this register clears the MOT
and OVF bits, Delta_Y and Delta_X registers.
The written data byte is not saved.
Internal buffers can accumulate more than
eight bits of motion for X or Y. If either one of
the internal buffers overflows, then absolute
path data is lost and the OVF bit is set. This bit is
cleared once some motion has been read from
the Delta_X and Delta_Y registers, and if the
16
2
Reserved Reserved
1
0
Reserved
Reserved
buffers are not at full scale. Since more data is
present in the buffers, the cycle of reading the
Motion, Delta_X and Delta_Y registers should
be repeated until the motion bit (MOT) is
cleared. Until MOT is cleared, either the Delta_X
or Delta_Y registers will read either positive or
negative full scale. If the motion register has
not been read for long time, at 500 cpi it may
take up to 16 read cycles to clear the buffers, at
1000 cpi, up to 32 cycles. To clear an overflow,
write anything to this register.
Data Type: bit field
3
The PIXRDY bit will be set whenever a valid
pixel data byte is available in the Pixel_Dump
register. Check that this bit is set before reading
from Pixel_Dump. To ensure that the Pixel_Grab
pointer has been reset to pixel 0,0 on the initial
write to Pixel_Grab, check to see if PIXFIRST is
set to high.
Field Name
Description
MOT
Motion since last report
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
PIXRDY
Pixel Dump data byte is available in Pixel_Dump register
0 = data not available
1 = data available
PIXFIRST
This bit is set when the Pixel_Grab register is written to or when the complete pixel array has
been read, initiating an increment to pixel 0,0.
0 = Pixel_Grab data not from pixel 0,0
1 = Pixel_Grab data is from pixel 0,0
OVF
Motion overflow, _Y and/or _X buffer has overflowed since last report
0 = no overflow
1 = Overflow has occurred
Delta_Y
Access: Read
Address: 0x03
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type: Eight bit 2’s complement number
USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading
clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_Y
80
81
FE
FF
00
01
02
7E
7F
NOTE: Avago Technologies RECOMMENDS that registers
0x03 and 0x04 be read sequentially.
17
Delta_X
Access: Read
Address: 0x04
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type: Eight bit 2’s complement number
USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading
clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_X
80
81
FE
FF
00
01
02
7E
7F
NOTE: Avago Technologies RECOMMENDS that registers
0x03 and 0x04 be read sequentially.
SQUAL
Access: Read
Bit
Field
Address: 0x05
Reset Value: Undefined
7
6
5
4
3
2
1
0
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type: Upper 8 bits of a 9-bit unsigned integer
USAGE: SQUAL (Surface Quality) is a measure of the
number of valid features visible by the sensor
in the current frame. The maximum SQUAL
register value is 167. Since small changes in the
current frame can result in changes in SQUAL,
variations in SQUAL when looking at a surface
are expected.
18
Shutter_Upper
Access: Read
Bit
Field
Address: 0x06
Reset Value: Undefined
7
6
5
4
3
2
1
0
S15
S14
S13
S12
S11
S10
S9
S8
Shutter_Lower
Access: Read
Address: 0x07
Reset Value: Undefined
Bit
7
6
5
4
3
2
1
0
Field
S7
S6
S5
S4
S3
S2
S1
S0
Data Type: Sixteen bit unsigned integer
USAGE: Units are clock cycles. Read Shutter_Upper
first, then Shutter_Lower. They should be read
consecutively. The shutter is adjusted to keep
the average and maximum pixel values within
normal operating ranges. The shutter value is
automatically adjusted.
Maximum_Pixel
Access: Read
Bit
Field
Address: 0x08
Reset Value: Undefined
7
6
5
4
3
2
1
0
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Eight-bit number
USAGE: Maximum Pixel value in current frame. Minimum
value = 0, maximum value = 254. The maximum
pixel value can vary with every frame.
19
Pixel_Sum
Access: Read
Address: 0x09
Reset Value: Undefined
Bit
Field
7
6
5
4
3
2
1
0
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP0
Data Type: High 8 bits of an unsigned 17-bit integer
USAGE: This register is used to find the average pixel value. It reports the seven bits of a 16-bit counter, which sums
all pixels in the current frame. It may be described as the full sum divided by 512. To find the average pixel
value, use the following formula:
Average Pixel = Register Value * 128/121 = Register Value * 1.06
The maximum register value is 240. The minimum is 0. The pixel sum value can change on every frame.
Minimum_Pixel
Access: Read
Bit
Field
Address: 0x0a
Reset Value: Undefined
7
6
5
4
3
2
1
0
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Eight-bit number
USAGE: Minimum Pixel value in current frame. Minimum
value = 0, maximum value = 254. The minimum
pixel value can vary with every frame.
Pixel_Grab
Access: Read/Write
Bit
Field
Address: 0x0b
Reset Value: Undefined
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Data Type: Eight-bit word
USAGE: For test purposes, the sensor will read out the
contents of the pixel array, one pixel per frame.
To start a pixel grab, write anything to this register to reset the pointer to pixel 0,0. Then read
the PIXRDY bit in the Motion register. When the
PIXRDY bit is set, there is valid data in this register to read out. After the data in this register
is read, the pointer will automatically increment
to the next pixel. Reading may continue indefinitely; once a complete frame’s worth of pixels
has been read, PIXFIRST will be set to high to
indicate the start of the first pixel and the address pointer will start at the beginning location again.
20
(Pixel Array Map Looking Through the ADNS-3150-001 Lens)
461
439
417
395
373
351
329
307
285
263
241
219
197
175
153
131
109
87
65
43
21
463
460
438
416
394
372
350
328
306
284
262
240
218
196
174
152
130
108
86
64
42
20
464
459
437
415
393
371
349
327
305
283
261
239
217
195
173
151
129
107
85
63
41
19
465
458
436
414
392
370
348
326
304
282
260
238
216
194
172
150
128
106
84
62
40
18
466
457
435
413
391
369
347
325
303
281
259
237
215
193
171
149
127
105
83
61
39
17
467
456
434
412
390
368
346
324
302
280
258
236
214
192
170
148
126
104
82
60
38
16
468
455
433
411
389
367
345
323
301
279
257
235
213
191
169
147
125
103
81
59
37
15
469
454
432
410
388
366
344
322
300
278
256
234
212
190
168
146
124
102
80
58
36
14
470
453
431
409
387
365
343
321
299
277
255
233
211
189
167
145
123
101
79
57
35
13
471
452
430
408
386
364
342
320
298
276
254
232
210
188
166
144
122
100
78
56
34
12
472
451
429
407
385
363
341
319
297
275
253
231
209
187
165
143
121
99
77
55
33
11
473
450
428
406
384
362
340
318
296
274
252
230
208
186
164
142
120
98
76
54
32
10
474
449
427
405
383
361
339
317
295
273
251
229
207
185
163
141
119
97
75
53
31
9
475
448
426
404
382
360
338
316
294
272
250
228
206
184
162
140
118
96
74
52
30
8
476
447
425
403
381
359
337
315
293
271
249
227
205
183
161
139
117
95
73
51
29
7
477
446
424
402
380
358
336
314
292
270
248
226
204
182
160
138
116
94
72
50
28
6
478
445
423
401
379
357
335
313
291
269
247
225
203
181
159
137
115
93
71
49
27
5
479
444
422
400
378
356
334
312
290
268
246
224
202
180
158
136
114
92
70
48
26
4
480
443
421
399
377
355
333
311
289
267
245
223
201
179
157
135
113
91
69
47
25
3
481
442
420
398
376
354
332
310
288
266
244
222
200
178
156
134
112
90
68
46
24
2
482
441
419
397
375
353
331
309
287
265
243
221
199
177
155
133
111
89
67
45
23
1
483
440
418
396
374
352
330
308
286
264
242
220
198
176
154
132
110
88
66
44
22
0
BOTTOM VIEW OF MOUSE
TOP VIEW OF MOUSE
LB
HOLE AT MOUSE BOTTOM
COVER FOR LENS
POSITIVE X
Figure 19. Surface image pixel address map
CRC0
Access: Read
Address: 0x0c
Reset Value: Undefined
Bit
Field
7
6
5
4
3
2
1
0
CRC07
CRC06
CRC05
CRC04
CRC03
CRC02
CRC01
CRC00
Data Type: Eight-bit number
USAGE: Register 0x0c reports the first byte of the system
self test results. Value = 0xAF. See Self Test register 0x10.
CRC1 Access: Read
Address: 0x0d
Reset Value: Undefined
Bit
Field
7
6
5
4
3
2
1
0
CRC17
CRC16
CRC15
CRC14
CRC13
CRC12
CRC11
CRC10
Data Type: Eight bit number
USAGE: Register 0x0c reports the second byte of the
system self test results. Value = 0x4E. See Self
Test register 0x10.
21
RB
POSITIVE Y
462
CRC2
Access: Read
Address: 0x0e
Reset Value: Undefined
Bit
Field
7
6
5
4
3
2
1
0
CRC27
CRC26
CRC25
CRC24
CRC23
CRC22
CRC21
CRC20
Data Type: Eight-bit number
USAGE: Register 0x0e reports the third byte of the
system self test results. Value = 0x31. See Self
Test register 0x10.
CRC3
Access: Read
Address: 0x0f
Reset Value: Undefined
Bit
Field
7
6
5
4
3
2
1
0
CRC37
CRC36
CRC35
CRC34
CRC33
CRC32
CRC31
CRC30
Data Type: Eight-bit number
USAGE: Register 0x0f reports the fourth byte of the
system self test results. Value = 0x22. See Self
Test register 0x10.
Self_Test
Access: Write
Address: 0x10
Reset Value: NA
Bit
Field
7
6
5
3
2
1
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Data Type: Bit field
USAGE: Set the TESTEN bit in register 0x10 to start the
system self-test. The test takes 250 ms. During
this time, do not write or read through the SPI
port. Results are available in the CRC0-3 registers. After self-test, reset the chip to start normal operation.
Field Name
Description
TESTEN
Enable System Self Test
0 = Disabled
1 = Enable
22
4
0
TESTEN
Configuration_bits Access: Read/Write
Bit
Field
Address: 0x11
Reset Value: 0x03
7
6
5
4
RES
Reserved
RESTEN
RESTEN
1
0
Data Type: Bit field
USAGE: Register 0x11 allows the user to change the
configuration of the sensor. Setting the RESTEN
bit forces the sensor into Rest mode, as described in the power modes section above.
The RES bit allows selection between 500 and
1000 cpi resolution.
Note: Forced Rest has a long wakeup time and
should not be used for power management during normal mouse motion.
Field Name
Description
RESTEN1-0
Puts chip into Rest mode
00 = normal operation
01 = force Rest1
10 = force Rest2
11 = force Rest3
RES
Sets resolution
0 = 500
1 = 1000
Reserved
Address: 0x12-0x2d
23
3
2
1
0
Reserved Reserved Reserved Reserved
Observation Access: Read/Write
Address: 0x2e
Reset Value: Undefined
Bit
Field
7
6
MODE1
MODE0
5
4
Reserved Reserved
3
2
1
0
OBS3
OBS2
OBS1
OBS0
Data Type: Bit field
USAGE: Register 0x2e provides bits that are set every
frame. It can be used during EFTB testing to
check that the chip is running correctly. Writing
anything to this register will clear the bits.
Field Name
Description
MODE1-0
Mode Status: Reports which mode the sensor is in.
00 = Run
01 = Rest1
10 = Rest2
11 = Rest3
OBS3-0
Set every frame
Reserved
Address: 0x2f-0x39
POWER_UP_RESET
Access: Write
Bit
Field
Address: 0x3a
Reset Value: Undefined
7
6
5
4
3
2
1
0
RST7
RST6
RST5
RST4
RST3
RST2
RST1
RST0
Data Type: 8-bit integer
USAGE: Write 0x5A to this register to reset the chip. All
settings will revert to default values.
24
Inverse_Revision_ID
Access: Read
Bit
Field
Address: 0x3e
Reset Value: 0xFD
7
6
5
4
3
2
1
0
NRID7
NRID6
NRID5
NRID4
NRID3
NRID2
NRID1
NRID0
Data Type: Inverse 8-bit unsigned integer
USAGE: This value is the inverse of the Revision_ID. It
can be used to test the SPI port.
Inverse_Revision_ID
Access: Read
Bit
Field
Address: 0x3f
Reset Value: 0xF2
7
6
5
4
3
2
1
0
NPID7
NPID6
NPID5
NPID4
NPID3
NPID2
NPID1
NPID0
Data Type: Inverse 8-bit unsigned integer
USAGE: This value is the inverse of the Product_ID. It
can be used to test the SPI port.
Motion_Burst
Access: Read
Bit
Field
Address: 0x42
Reset Value: Any
7
6
5
4
3
2
1
0
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
Data Type: Various
USAGE: Read from this register to activate burst mode.
The sensor will return the data in the Motion
register, Delta_Y, Delta_X, Squal, Shutter_Upper, Shutter_Lower, and Maximum_Pixel. A minimum of 3 bytes should be read during a burst
read. Reading the first 3 bytes clears the motion
data.
25
ADNS-3150-001
Small Form Factor Lens
Description
The ADNS-3150-001 small form factor (SFF) lens is
designed for use with Avago Technologies ADNS-3530
integrated COB sensor. Together with the LED, the ADNS3150-001 SFF lens provide the direct illumination and
optical imaging necessary for proper operation of the
sensor. ADNS-3150-001 SFF lens is a precision molded
optical component and should be handled with care to
avoid scratching of the optical surfaces.
12.90
(0.508)
1.70
(0.067)
1.66
(0.065)
9.00
(0.354)
1.90
(0.075)
4X R 0.50
(0.020)
5.60
A
A (0.220)
GATE
(MAX. 0.2 mm
PROTRUDE)
EITHER SIDE
4.35
(0.171)
1.50
(0.059)
3.00
(0.118)
CL
0.89 ± 0.15
(0.035 ± 0.006)
3.37
(0.133)
5.80
(0.228)
9.50
(0.374)
1.28
(0.050)
0.13
(0.005)
0.62
(0.024)
ILLUMINATION LENS
SURFACE 3
0.62
(0.024)
4.46
(0.176)
IMAGING LENS
SURFACE 2
IMAGING LENS
SURFACE 1
ILLUMINATION LENS
SURFACE 1
1.96
(0.077)
0.59 ± 0.15
(0.23 ± 0.006)
0.88 ± 0.15
(0.35 ± 0.006)
R 0.20
(0.008)
ILLUMINATION LENS
SURFACE 2
SECTION A–A
0.29
(0.011)
NOTES:
1. DIMENSIONS IN MILLIMETERS (INCHES).
2. DIMENSIONAL TOLERANCE: ±0.1 mm UNLESS OTHERWISE SPECIFIED.
3. ANGULAR TOLERANCE: ±3°.
4. MAXIMUM FLASH: +0.2 mm.
Figure 20. ADNS-3150-001 SFF lens outline drawings and details
26
Lens Design Optical Performance Specifications
All specifications are based on the Mechanical Assembly Requirements.
Symbol
Numerical Aperture
NA
Magnification
Min.
Typical
Max.
Units
0.1642
-1
Image at nominal location
Design Wavelength
l
639
nm
Depth of Field
DOF
±0.1
mm
0.85
mm
Die Coverage Radius
Conditions
Image circle radius
*Lens material is polycarbonate. Cyanoacrylate based adhesives should not be used as they will cause lens material
deformation.
Mounting Instructions for the ADNS-3150-001 Lens to
the Base Plate
An IGES format drawing file with design specifications
for mouse base plate features is available.
These features are useful in maintaining proper positioning and alignment of the ADNS-3150-001 when
used with the Avago Technologies Optical Sensor. This
file can be obtained by contacting your local Avago
Technologies sales representative.
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.
AV02-0249EN May 17, 2007