AD S ADS 121 ADS1212 ADS1213 1212 3 ADS1 212 ADS1 213 ADS1 213 SBAS064B – JANUARY 1996 – REVISED FEBRUARY 2004 22-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● DELTA-SIGMA A/D CONVERTER ● 22 BITS NO MISSING CODES ● 20 BITS EFFECTIVE RESOLUTION AT 10Hz AND 16 BITS AT 1000Hz ● LOW POWER: 1.4mW ● DIFFERENTIAL INPUTS ● PROGRAMMABLE GAIN AMPLIFIER ● SPI™ COMPATIBLE SSI INTERFACE The ADS1212 and ADS1213 are precision, wide dynamic range, delta-sigma Analog-to-Digital (A/D) converters with 24-bit resolution operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers or low-level voltage signals. The delta-sigma architecture is used for wide dynamic range and to ensure 22 bits of no-missing-code performance. An effective resolution of 20 bits is achieved through the use of a very low-noise input amplifier at conversion rates up to 10Hz. Effective resolutions of 16 bits can be maintained up to a sample rate of 1kHz through the use of the unique Turbo Modulator mode of operation. The dynamic range of the converters is further increased by providing a low-noise programmable gain amplifier with a gain range of 1 to 16 in binary steps. ● PROGRAMMABLE CUTOFF FREQUENCY UP TO 6.25kHz ● INTERNAL/EXTERNAL REFERENCE ● ON-CHIP SELF-CALIBRATION ● ADS1213 INCLUDES 4-CHANNEL MUX The ADS1212 and ADS1213 are designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography and portable instrumentation. Both converters include a flexible synchronous serial interface that is SPI compatible and also offers a two-wire control mode for low-cost isolation. APPLICATIONS ● ● ● ● ● ● ● INDUSTRIAL PROCESS CONTROL INSTRUMENTATION BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS The ADS1212 is a single channel converter and is offered in both DIP-18 and SO-18 packages. The ADS1213 includes a 4-channel input multiplexer and is available in DIP-24, SO-24, and SSOP-28 packages. AGND AVDD REFOUT REFIN +2.5V Reference AIN1P VBIAS XIN +3.3V Bias Generator XOUT Clock Generator DGND AIN1N DVDD Micro Controller AIN2P AINP AIN2N AIN3P MUX PGA AINN Second-Order ∆∑ Modulator Third-Order Digital Filter AIN3N AIN4P AIN4N Instruction Register Command Register Data Output Register Offset Register Full-Scale Register Modulator Control ADS1213 Only Serial Interface DSYNC ADS1212, 1213 CS MODE SCLK SDIO SDOUT DRDY PATENTS PENDING Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1996-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com SPECIFICATIONS All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise specified. ADS1212U, P/ADS1213U, P, E PARAMETER CONDITIONS ANALOG INPUT Input Voltage Range(1) Input Impedance Programmable Gain Amplifier Input Capacitance Input Leakage Current SYSTEMS PERFORMANCE No Missing Codes Integral Linearity Integral Linearity (Single-Ended) Unipolar Offset Error(4) Unipolar Offset Drift(6) Gain Error(4) Gain Error Drift(6) Common-Mode Rejection(9) Normal-Mode Rejection Output Noise Power Supply Rejection VOLTAGE REFERENCE Internal Reference (REFOUT) Drift Noise Load Current Output Impedance External Reference (REFIN) Load Current VBIAS Output Drift Load Current DIGITAL INPUT/OUTPUT Logic Family Logic Level: (all except XIN) VIH VIL VOH VOL XIN Input Levels: VIH VIL XIN Frequency Range (fXIN) Output Data Rate (fDATA) Data Format SYSTEM CALIBRATION Offset and Full-Scale Limits VFS – | VOS | 2 With VBIAS(2) G = Gain, TMR = Turbo Mode Rate User Programmable: 1, 2, 4, 8, or 16 MIN TYP 0 –10 UNITS +5 +10 V V MΩ 20/(G • TMR)(3) 1 16 5 5 At +25°C TMIN to TMAX fDATA = 10Hz fDATA = 60Hz fDATA = 100Hz, TMR of 4 fDATA = 250Hz, TMR of 8 fDATA = 500Hz, TMR of 16 fDATA = 1000Hz, TMR of 16 fDATA = 60Hz fDATA = 1000Hz, TMR of 16 MAX pF pA nA 50 1 22 19 21 20 20 18 ±0.0015 ±0.0015 At DC, TMIN to TMAX 50Hz, fDATA = 50Hz(7) 60Hz, fDATA = 60Hz(7) 50Hz, fDATA = 50Hz(7) 60Hz, fDATA = 60Hz(7) 90 160 160 100 100 DC, 50Hz, and 60Hz 60 0.01 See Note 5 1 See Note 5 4 100 Bits Bits Bits Bits Bits Bits %FSR %FSR %FSR ppm/°C ppm/°C dB dB dB dB dB See Typical Performance Curves dB 2.4 2.5 25 50 2.6 Source or Sink 1 2 2.0 Using Internal Reference 3.15 3.0 2.5 3.45 3.3 50 Source or Sink V ppm/°C µVp-p mA Ω V µA V ppm/°C 10mA TTL Compatible CMOS IOH IOL IIH = +5µA IIL = +5µA = 2 TTL Loads = 2 TTL Loads User Programmable and TMR = 1 to 16 fXIN = 500kHz fXIN = 2.5MHz User Programmable VFS = Full-Scale Differential Voltage(8) VOS = Offset Differential Voltage(8) 2.0 –0.3 2.4 DVDD +0.3 0.8 0.4 DVDD +0.3 0.8 2.5 6,250 3,125 15,625 3.5 –0.3 0.5 0.96 0.48 2.4 V V V V V V MHz Hz Hz Hz Two’s Complement or Offset Binary 0.7 • (2 • REFIN)/G 1.3 • (2 • REFIN)/G ADS1212, 1213 SBAS064A SPECIFICATIONS (Cont.) All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise specified. ADS1212U, P/ADS1213U, P, E PARAMETER CONDITIONS POWER SUPPLY REQUIREMENTS Power Supply Voltage Power Supply Current: Analog Current Digital Current Additional Analog Current with REFOUT Enabled VBIAS Enabled Power Dissipation MIN TYP 4.75 fXIN No Load At +25°C TMIN to TMAX TMR of 16 fXIN = 2.5MHz = 2.5MHz, TMR of 16 Sleep Mode TEMPERATURE RANGE Specified Storage 5.25 UNITS V 95 185 µA µA 1.8 1 1.4 1.8 8.5 mA mA mW mW mW mW mW mW +85 +125 °C °C 6 2.2 7.5 0.45 –40 –60 MAX NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential (AINN = 2 • REFIN – AINP). If the input is single-ended (AINN or AINP is fixed), then the full-scale range is one-half that of the differential range. (2) This range is set with external resistors and VBIAS (as described in the text). Other ranges are possible. (3) Input impedance is higher with lower fXIN. (4) Applies after calibration. (5) After system calibration, these errors will be of the order of the effective resolution of the converter. Refer to the Typical Performance Curves which apply to the desired mode of operation. (6) Recalibration can remove these errors. (7) The specification also applies at fDATA /i, where i is 2, 3, 4, etc. (8) Voltages at the analog inputs must remain within AGND to AVDD. (9) The commonmode rejection test is performed with 100mV differential input. ABSOLUTE MAXIMUM RATINGS Analog Input: Current ................................................ ±100mA, Momentary ±10mA, Continuous Voltage ................................... AGND –0.3V to AVDD +0.3V AVDD to DVDD ........................................................................... –0.3V to 6V AVDD to AGND ......................................................................... –0.3V to 6V DVDD to DGND ......................................................................... –0.3V to 6V AGND to DGND ................................................................................ ±0.3V REFIN Voltage to AGND ............................................ –0.3V to AVDD +0.3V Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V Lead Temperature (soldering, 10s) .............................................. +300°C Power Dissipation (Any package) .................................................. 500mW PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. For the latest package and ordering information, see the Package Option Addendum located at the end of this data sheet. ADS1212, 1213 SBAS064A 3 ADS1212 SIMPLIFIED BLOCK DIAGRAM AGND AVDD 3 16 REF OUT REF IN VBIAS 17 18 4 +2.5V Reference AINP AINN XOUT 7 +3.3V Bias Generator 8 Clock Generator 9 DGND 10 DVDD Micro Controller 1 2 XIN Second-Order ∆Σ Modulator PGA Instruction Register Command Register Data Output Register Offset Register Full-Scale Register Third-Order Digital Filter 11 Modulator Control 6 5 DSYNC ADS1212 PIN CONFIGURATION TOP VIEW 4 1 18 REFIN AINN 2 17 REFOUT AGND 3 16 AVDD VBIAS 4 15 MODE CS 5 DSYNC 6 ADS1212 14 DRDY 13 SDOUT XIN 7 12 SDIO XOUT 8 11 SCLK DGND 9 10 DVDD CS 15 14 MODE DRDY SCLK SDIO SDOUT ADS1212 PIN DEFINITIONS DIP/SOIC AINP 12 13 Serial Interface PIN NO NAME 1 AINP Noninverting Input. 2 AINN Inverting Input. 3 AGND Analog Ground. 4 VBIAS Bias Voltage Output, +3.3V nominal. 5 CS 6 DSYNC 7 XIN DESCRIPTION Chip Select Input. Control Input to Synchronize Serial Output Data. System Clock Input. 8 XOUT 9 DGND Digital Ground. 10 DVDD Digital Supply, +5V nominal. 11 SCLK Clock Input/Output for serial data transfer. 12 SDIO 13 SDOUT Serial Data Input (can also function as Serial Data Output). Serial Data Output. System Clock Output. 14 DRDY Data Ready. 15 MODE SCLK Control Input (Master = 1, Slave = 0). 16 AVDD 17 REFOUT 18 REFIN Analog Supply, +5V nominal. Reference Output, +2.5V nominal. Reference Input. ADS1212, 1213 SBAS064A ADS1213 SIMPLIFIED BLOCK DIAGRAM AGND AVDD 6 19 REFIN VBIAS 20 21 7 +2.5V Reference 4 AIN1P REFOUT XIN XOUT 10 +3.3V Bias Generator 11 Clock Generator 5 AIN1N Second-Order ∆∑ Modulator 3 AIN2N MUX 24 AIN3P PGA 22 AIN4P 23 AIN4N Modulator Control DVDD DSYNC ADS1213P AND ADS1213U PIN CONFIGURATION TOP VIEW DIP/SOIC AIN3N 1 24 AIN3P AIN2P 2 23 AIN4N AIN2N 3 22 AIN4P AIN1P 4 21 REFIN AIN1N 5 20 REFOUT AGND 6 ADS1213P ADS1213U 19 AVDD 18 MODE VBIAS 7 CS 8 17 DRDY DSYNC 9 16 SDOUT XIN 10 15 SDIO XOUT 11 14 SCLK DGND 12 13 DVDD ADS1212, 1213 14 15 16 Serial Interface 9 SBAS064A 13 Instruction Register Command Register Data Output Register Offset Register Full-Scale Register Third-Order Digital Filter 1 AIN3N DGND Micro Controller 2 AIN2P 12 8 CS 18 17 MODE DRDY SCLK SDIO SDOUT ADS1213P AND ADS1213U PIN DEFINITIONS PIN NO NAME DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS CS DSYNC XIN XOUT DGND DVDD SCLK SDIO 16 17 18 19 20 21 22 23 24 SDOUT DRDY MODE AVDD REFOUT REFIN AIN4P AIN4N AIN3P Inverting Input Channel 3. Noninverting Input Channel 2. Inverting Input Channel 2. Noninverting Input Channel 1. Inverting Input Channel 1. Analog Ground. Bias Voltage Output, +3.3V nominal. Chip Select Input. Control Input to Synchronize Serial Output Data. System Clock Input. System Clock Output. Digital Ground. Digital Supply, +5V nominal. Clock Input/Output for serial data transfer. Serial Data Input (can also function as Serial Data Output). Serial Data Output. Data Ready. SCLK Control Input (Master = 1, Slave = 0). Analog Supply, +5V nominal. Reference Output: +2.5V nominal. Reference Input. Noninverting Input Channel 4. Inverting Input Channel 4. Noninverting Input Channel 3. 5 ADS1213E PIN CONFIGURATION TOP VIEW SSOP AIN3N 1 28 AIN3P AIN2P 2 27 AIN4N AIN2N 3 26 AIN4P AIN1P 4 25 REFIN AIN1N 5 24 REFOUT AGND 6 23 AVDD VBIAS 7 NIC 8 NIC 9 CS 10 DSYNC 11 6 ADS1213E PIN DEFINITIONS 22 MODE ADS1213E 21 NIC 20 NIC 19 DRDY 18 SDOUT XIN 12 17 SDIO XOUT 13 16 SCLK DGND 14 15 DVDD PIN NO NAME DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS NIC NIC CS DSYNC XIN XOUT DGND DVDD SCLK SDIO 18 19 20 21 22 23 24 25 26 27 28 SDOUT DRDY NIC NIC MODE AVDD REFOUT REFIN AIN4P AIN4N AIN3P Inverting Input Channel 3. Noninverting Input Channel 2. Inverting Input Channel 2. Noninverting Input Channel 1. Inverting Input Channel 1. Analog Ground. Bias Voltage Output, +3.3V nominal. Not Internally Connected. Not Internally Connected. Chip Select Input. Control Input to Synchronize Serial Output Data. System Clock Input. System Clock Output. Digital Ground. Digital Supply, +5V nominal. Clock Input/Output for serial data transfer. Serial Data Input (can also function as Serial Data Output). Serial Data Output. Data Ready. Not Internally Connected. Not Internally Connected. SCLK Control Input (Master = 1, Slave = 0). Analog Supply, +5V nominal. Reference Output: +2.5V nominal. Reference Input. Noninverting Input Channel 4. Inverting Input Channel 4. Noninverting Input Channel 3. ADS1212, 1213 SBAS064A TYPICAL PERFORMANCE CURVES At TA = +25°C, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise noted. EFFECTIVE RESOLUTION vs DATA RATE (1MHz Clock) EFFECTIVE RESOLUTION vs DATA RATE (2.5MHz Clock) 24 Effective Resolution in Bits (rms) Effective Resolution in Bits (rms) 24 Turbo 16 22 Turbo 8 20 18 Turbo 1 16 Turbo 2 14 Turbo 4 12 10 100 Turbo 1 18 Turbo 2 Turbo 4 16 14 1k 1 10 100 1k Data Rate (Hz) Data Rate (Hz) EFFECTIVE RESOLUTION vs DATA RATE (1MHz Clock) EFFECTIVE RESOLUTION vs DATA RATE (2.5MHz Clock) 24 22 Effective Resolution in Bits (rms) 24 Effective Resolution in Bits (rms) Turbo 8 20 12 1 PGA 1 PGA 4 20 PGA 8 18 PGA 2 16 PGA 16 14 12 10 8 PGA 1 22 PGA 2 PGA 4 20 18 PGA 16 16 PGA 8 14 12 10 8 1 10 100 1k 1 10 100 1k Data Rate (Hz) Data Rate (Hz) LINEARITY vs TEMPERATURE (60Hz Data Rate) RMS NOISE vs INPUT VOLTAGE LEVEL (60Hz Data Rate) 8 14 –40°C +25°C +85°C 6 12 4 RMS Noise (ppm) Integral Nonlinearity (ppm) Turbo 16 22 2 0 –2 10 8 6 –4 –6 –5 –4 –3 –2 –1 0 1 2 3 Analog Input Differential Voltage (V) ADS1212, 1213 SBAS064A 4 5 4 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 Analog Input Differential Voltage (V) 7 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise noted. POWER DISSIPATION vs PGA SETTING (REFOUT Enabled) ANALOG CURRENT vs PGA SETTING (REFOUT Enabled) 15 2700 Power Dissipation (mW) 14 13.5 13 12.5 12 11.5 2500 2400 2300 2200 2100 11 2000 10.5 1900 10 1800 1 2 4 8 16 1 2 4 8 16 PGA Setting PGA Setting POWER DISSIPATION vs PGA SETTING (External Reference; REFOUT Disabled) ANALOG CURRENT vs PGA SETTING (External Reference; REFOUT Disabled) 6 980 4 3 2 Turbo 1 Turbo 2 Turbo 4 Turbo 8 Turbo 16 880 780 Analog IDD (µA) Turbo 1 Turbo 2 Turbo 4 Turbo 8 Turbo 16 5 Power Dissipation (mW) Turbo 1 Turbo 2 Turbo 4 Turbo 8 Turbo 16 2600 Analog IDD (µA) Turbo 1 Turbo 2 Turbo 4 Turbo 8 Turbo 16 14.5 680 580 480 380 280 1 180 0 80 1 2 4 PGA Setting 8 8 16 1 2 4 8 16 PGA Setting ADS1212, 1213 SBAS064A THEORY OF OPERATION The ADS1212 and ADS1213 are precision, high dynamic range, self-calibrating, 24-bit, delta-sigma A/D converters capable of achieving very high resolution digital results. Each contains a programmable gain amplifier (PGA); a second-order delta-sigma modulator; a programmable digital filter; a microcontroller including the Instruction, Command and Calibration registers; a serial interface; a clock generator circuit; and an internal 2.5V reference. The ADS1213 includes a 4-channel input multiplexer. In order to provide low system noise, common-mode rejection of 100dB and excellent power supply rejection, the design topology is based on a fully differential switched capacitor architecture. Turbo Mode, a unique feature of the ADS1212/13, can be used to boost the sampling rate of the input capacitor, which is normally 7.8kHz with a 1MHz clock. By programming the Command Register, the sampling rate can be increased to 15.6kHz, 31.2kHz, 62.5kHz, or 125kHz. Each increase in sample rate results in an increase in performance when maintaining the same output data rate. The programmable gain amplifier (PGA) of the ADS1212/ 13 can be set to a gain of 1, 2, 4, 8 or 16—substantially increasing the dynamic range of the converter and simplifying the interface to the more common transducers (see Table I). This gain is implemented by increasing the number of samples taken by the input capacitor from 7.8kHz for a gain of 1 to 125kHz for a gain of 16. Since the Turbo Mode and PGA functions are both implemented by varying the sampling frequency of the input capacitor, the combination of PGA gain and Turbo Mode Rate is limited to 16 (see Table II). For example, when using a Turbo Mode Rate of 8 (62.5kHz at 1MHz), the maximum PGA gain setting is 2. ANALOG INPUT(1) GAIN SETTING FULLSCALE RANGE (V) 1 2 4 8 16 10 5 2.5 1.25 0.625 ANALOG INPUT UTILIZING VBIAS(1,2) EXAMPLE VOLTAGE RANGE(3) (V) 0 1.25 1.88 2.19 2.34 to to to to to 5 3.75 3.13 2.81 2.66 FULLSCALE RANGE (V) EXAMPLE VOLTAGE RANGE(3) (V) 40 20 10 5 2.5 ±10 ±5 ±2.5 ±1.25 ±0.625 NOTE: (1) With a 2.5V reference, such as the internal reference. (2) This example utilizes the circuit in Figure 12. Other input ranges are possible. (3) The ADS1212/13 allows common-mode voltage as long as the absolute input voltage on AINP or AINN does not go below AGND or above AVDD. TABLE I. Full-Scale Range vs PGA Setting. TURBO MODE RATE AVAILABLE PGA SETTINGS 1 2 4 8 16 1, 2, 4, 8, 16 1, 2, 4, 8 1, 2, 4 1, 2 1 The output data rate of the ADS1212/13 can be varied from less than 1Hz to as much as 6.25kHz, trading off lower resolution results for higher data rates. In addition, the data rate determines the first null of the digital filter and sets the –3dB point of the input bandwidth (see the Digital Filter section). Changing the data rate of the ADS1212/13 does not result in a change in the sampling rate of the input capacitor. The data rate effectively sets the number of samples which are used by the digital filter to obtain each conversion result. A lower data rate results in higher resolution, lower input bandwidth, and different notch frequencies than a higher data rate. It does not result in any change in input impedance or modulator frequency, or any appreciable change in power consumption. The ADS1212/13 also includes complete on-board calibration that can correct for internal offset and gain errors or limited external system errors. Internal calibration can be run when needed, or automatically and continuously in the background. System calibration can be run as needed and the appropriate input voltages must be provided to the ADS1212/ 13. For this reason, there is no continuous system calibration mode. The calibration registers are fully readable and writable. This feature allows for switching between various configurations—different data rates, Turbo Mode Rates, and gain settings—without re-calibrating. The various settings, rates, modes, and registers of the ADS1212/13 are read or written via a synchronous serial interface. This interface can operate in either a self-clocked mode (Master Mode) or an externally clocked mode (Slave Mode). In the Master Mode, the serial clock (SCLK) frequency is one-quarter of the ADS1212/13 XIN clock frequency. The high resolution and flexibility of the ADS1212/13 allow these converters to fill a wide variety of A/D conversion tasks. In order to ensure that a particular configuration will meet the design goals, there are several important items which must be considered. These include (but are certainly not limited to) the needed resolution, required linearity, desired input bandwidth, power consumption goal, and sensor output voltage. The remainder of this data sheet discusses the operation of the ADS1212/13 in detail. In order to allow for easier comparison of different configurations, “effective resolution” is used as the figure of merit for most tables and graphs. For example, Table III shows a comparison between data rate (and –3dB input bandwidth) versus PGA setting at a Turbo Mode Rate of 1 and a clock rate of 1MHz. See the Definition of Terms section for a definition of effective resolution. TABLE II. Available PGA Settings vs Turbo Mode Rate. ADS1212, 1213 SBAS064A 9 DATA RATE (HZ) -3DB FREQUENCY (HZ) G=1 G=2 G=4 G=8 G = 16 10 25 30 50 60 100 250 2.62 6.55 7.86 13.1 15.7 26.2 65.5 20 19 19 17 17 15 12 20 19 19 17 17 15 12 20 19 18 17 17 15 12 19 18 18 17 16 15 12 18 18 17 16 16 15 12 EFFECTIVE RESOLUTION (BITS RMS) TABLE III. Effective Resolution vs Data Rate and Gain Setting. (Turbo Mode Rate of 1 and a 1MHz clock.) DEFINITION OF TERMS An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition of each term is given as follows: Analog Input Differential Voltage—For an analog signal that is fully differential, the voltage range can be compared to that of an instrumentation amplifier. For example, if both analog inputs of the ADS1212 are at 2.5V, then the differential voltage is 0V. If one is at 0V and the other at 5V, then the differential voltage magnitude is 5V. But, this is the case regardless of which input is at 0V and which is at 5V, while the digital output result is quite different. The analog input differential voltage is given by the following equation: AINP – AINN. Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 2, the positive fullscale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when the differential is –2.5V. In each case, the actual input voltages must remain within the AGND to AVDD range (see Table I). Actual Analog Input Voltage—The voltage at any one analog input relative to AGND. Full-Scale Range (FSR)—As with most A/D converters, the full-scale range of the ADS1212/13 is defined as the “input” which produces the positive full-scale digital output minus the “input” which produces the negative full-scale digital output. For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: [2.5V (positive full scale) minus –2.5V (negative full scale)] = 5V. Typical Analog Input Voltage Range—This term describes the actual voltage range of the analog inputs which will cover the converter’s full-scale range, assuming that each input has a common-mode voltage that is greater than REFIN/PGA and smaller than (AVDD – REFIN/PGA). 10 For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 2, the typical input voltage range is 1.25V to 3.75V (commonmode voltage = 2.5V). However, an input range of 0V to 2.5V (common-mode voltage = 1.25V) or 2.5V to 5V (common-mode voltage = 3.75V) would also cover the converter’s full-scale range. Voltage Span—This is simply the magnitude of the typical analog input voltage range. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 2, the input voltage span is 2.5V. Least Significant Bit (LSB) Weight—This is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. It is computed as follows: LSB Weight = Full−Scale Range 2N where N is the number of bits in the digital output. Effective Resolution—The effective resolution of the ADS1212/13 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and microvolts rms (referenced to input). Computed directly from the converter’s output data, each is a statistical calculation based on a given number of results. Knowing one, the other can be computed as follows: 10V PGA 20 • log − 1. 76 ER in Vrms ER in bits rms = 6. 02 10V PGA ER in Vrms = 6. 02 • ER in bits rms + 1. 76 20 10 The 10V figure in each calculation represents the full-scale range of the ADS1212/13 in a gain setting of 1. This means that both units are absolute expressions of resolution—the performance in different configurations can be directly compared regardless of the units. Comparing the resolution of different gain settings expressed in bits rms requires accounting for the PGA setting. Main Controller—A generic term for the external microcontroller, microprocessor, or digital signal processor which is controlling the operation of the ADS1212/13 and receiving the output data. ADS1212, 1213 SBAS064A fXIN—The frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1212/13. NORMALIZED DIGITAL FILTER RESPONSE 0 fMOD—The frequency or speed at which the modulator of the ADS1212/13 is running, given by the following equation: f XIN • Turbo Mode 128 fSAMP—The frequency or switching speed of the input sampling capacitor. The value is given by the following equation: f SAMP = –40 Gain (dB) f MOD = –20 –80 –100 –120 –140 f XIN • Turbo Mode • Gain Setting 128 fDATA, tDATA—The frequency of the digital output data produced by the ADS1212/13 or the inverse of this (the period), respectively, fDATA is also referred to as the data rate. –60 –160 0 1 2 3 4 5 6 Frequency (Hz) FIGURE 1. Normalized Digital Filter Response. FILTER RESPONSE DIGITAL FILTER The digital filter of the ADS1212/13 computes the output result based on the most recent results from the delta-sigma modulator. The number of modulator results that are used depend on the decimation ratio set in the Command Register. At the most basic level, the digital filter can be thought of as simply averaging the modulator results and presenting this average as the digital output. While the decimation ratio determines the number of modulator results to use, the modulator runs faster at higher Turbo Modes. These two items, together with the ADS1212/13 clock frequency, determine the output data rate: Gain (dB) –40 –60 –80 –100 –120 –140 –160 0 50 100 150 Frequency (Hz) 200 250 300 FILTER RESPONSE –40 –60 Gain (dB) Conversion Cycle—The term “conversion cycle” usually refers to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time period. However, each digital output is actually based on the modulator results from the last three tDATA time periods. 0 –20 –80 –100 –120 –140 –160 45 46 47 48 49 50 Frequency (Hz) 51 52 53 54 55 FIGURE 2. Digital Filter Response at a Data Rate of 50Hz. FILTER RESPONSE 0 –20 –40 Gain (dB) f DATA f XIN • Turbo Mode 1 = , t DATA = f DATA 128 • ( Decimation Ratio + 1) –60 –80 –100 –120 –140 –160 0 50 100 150 Frequency (Hz) 200 250 300 FILTER RESPONSE –40 f XIN • Turbo Mode 128 • ( Decimation Ratio + 1) Also, since the conversion result is essentially an average, the data rate determines where the resulting notches are in the digital filter. For example, if the output data rate is 1kHz, then a 1kHz input frequency will average to zero during the 1ms conversion cycle. Likewise, a 2kHz input frequency will average to zero, etc. In this manner, the data rate can be used to set specific notch frequencies in the digital filter response (see Figure 1 for the normalized response of the digital filter). For example, if the rejection of power line frequencies is desired, then the data rate can simply be set to the power line frequency. Figures 2 and 3 show the digital filter response for a data rate of 50Hz and 60Hz, respectively. ADS1212, 1213 SBAS064A Gain (dB) f DATA = –60 –80 –100 –120 –140 –160 55 56 57 58 59 60 Frequency (Hz) 61 62 63 64 65 FIGURE 3. Digital Filter Response at a Data Rate of 60Hz. If the effective resolution at a 50Hz or 60Hz data rate is not adequate for the particular application, then power line frequencies could still be rejected by operating the ADS1212/13 at 25/30Hz, 16.7/20Hz, 12.5/15Hz, etc. If a higher data rate is needed, then power line frequencies must either be rejected before conversion (with an analog notch filter) or after conversion (with a digital notch filter running on the main controller). 11 Filter Equation The digital filter is described by the following transfer function: π • f • N sin f MOD | H (f ) | = π•f N • sin f MOD 3 In a Turbo Mode Rate of 16, the ADS1212/13 can offer 16 bits of effective resolution at a 1kHz data rate. A comparison of effective resolution versus Turbo Mode Rates and output data rates is shown in Table IV while Table V shows the corresponding noise level in µVrms. where N is the Decimation Ratio. This filter has a (sin(x)/x)3 response and is referred to a sinc3 filter. For the ADS1212/13, this type of filter allows the data rate to be changed over a very wide range (nearly four orders of magnitude). However, the –3dB point of the filter is 0.262 times the data rate. And, as can be seen in Figures 1 and 2, the rejection in the stopband (frequencies higher than the first notch frequency) may only be –40dB. These factors must be considered in the overall system design. For example, with a 50Hz data rate, a significant signal at 75Hz may alias back into the passband at 25Hz. The analog front end can be designed to provide the needed attenuation to prevent aliasing, or the system may simply provide this inherently. Another possibility is increasing the data rate and then post filtering with a digital filter on the main controller. Filter Settling The number of modulator results used to compute each conversion result is three times the Decimation Ratio. This means that any step change (or any channel change for the ADS1213) will require at least three conversions to fully settle. However, if the change occurs asynchronously, then at least four conversions are required to ensure complete settling. For example, on the ADS1213, the fourth conversion result after a channel change will be valid (see Figure 4). Significant Analog Input Change or ADS1213 Channel Change Valid Data Valid Data Data not Valid Data not Valid Data not Valid Valid Data Valid Data DRDY Serial I/O tDATA FIGURE 4. Asynchronous ADS1212/13 Analog Input Voltage Step or ADS1213 Channel Change to Fully Settled Output Data. TURBO MODE The ADS1212/13 offers a unique Turbo Mode feature which can be used to increase the modulator sampling rate by 2, 4, 8, or 16 times normal. With the increase of modulator sampling frequency, there can be a substantial increase in 12 the effective resolution of the output data at a given data rate, but there is also an increase in power dissipation. For Turbo Mode Rates 2 and 4, the increase is slight. For rates 8 and 16, the increase is more substantial. See the Typical Performance Curves for more information. EFFECTIVE RESOLUTION (BITS RMS) DATA RATE (HZ) TURBO MODE RATE 1 TURBO MODE RATE 2 TURBO MODE RATE 4 TURBO MODE RATE 8 TURBO MODE RATE 16 10 20 40 50 60 100 250 1000 20 19 18 17 17 15 12 21 20 20 19 19 17 14 21 21 21 20 20 19 16 12 21 21 21 21 21 19 14 21 21 21 21 20 16 TABLE IV. Effective Resolution vs Data Rate and Turbo Mode Rate. (Gain setting of 1 and 1MHz clock.) NOISE LEVEL (µVrms) DATA RATE (Hz) TURBO MODE RATE 1 TURBO MODE RATE 2 TURBO MODE RATE 4 TURBO MODE RATE 8 TURBO MODE RATE 16 10 20 40 50 60 100 250 1000 7.6 15 30 60 60 240 1900 3.8 7.6 7.6 15 15 60 480 3.8 3.8 3.8 7.6 7.6 15 120 1900 3.8 3.8 3.8 3.8 3.8 15 480 3.8 3.8 3.8 3.8 7.6 120 TABLE V. Noise Level vs Data Rate and Turbo Mode Rate. (Gain setting of 1 and 1MHz clock.) The Turbo Mode feature allows trade-offs to be made between the ADS1212/13 XIN clock frequency, power dissipation, and effective resolution. If a 0.5MHz clock is available but a 1MHz clock is needed to achieve the desired performance, a Turbo Mode Rate of 2X will result in the same effective resolution. Table VI provides a comparison of effective resolution at various clock frequencies, data rates, and Turbo Mode Rates. DATA RATE (Hz) XIN CLOCK FREQUENCY (MHz) TURBO MODE RATE EFFECTIVE RESOLUTION (Bits rms) 60 2 2 20 60 1 4 20 60 0.5 8 20 100 2 2 19 100 1 4 19 100 0.5 8 19 TABLE VI. Effective Resolution vs Data Rate, Clock Frequency, and Turbo Mode Rate. (Gain setting of 1.) ADS1212, 1213 SBAS064A The Turbo Mode Rate (TMR) is programmed via the Sampling Frequency bits of the Command Register. Due to the increase in input capacitor sampling frequency, higher Turbo Mode settings result in lower analog input impedance; AIN Impedance (Ω) = (1MHz/fXIN)•20E6/(G•TMR) where G is the gain setting. Because the modulator rate also changes in direct relation to the Turbo Mode setting, higher values result in a lower impedance for the REFIN input: REFIN Impedance (Ω) = (1MHz/fXIN)•5E6/TMR The Turbo Mode Rate can be set to 1, 2, 4, 8, or 16. Consult the graphs shown in the Typical Performance Curves for full details on the performance of the ADS1212/13 operating in different Turbo Mode Rates. Keep in mind that higher Turbo Mode Rates result in fewer available gain settings as shown in Table II. PROGRAMMABLE GAIN AMPLIFIER The programmable gain amplifier gain setting is programmed via the PGA Gain bits of the Command Register. Changes in the gain setting (G) of the programmable gain amplifier results in an increase in the input capacitor sampling frequency. Thus, higher gain settings result in a lower analog input impedance: AIN Impedance (Ω) = (1MHz/fXIN)•20E6/(G•TMR) where TMR is the Turbo Mode Rate. Because the modulator speed does not depend on the gain setting, the input impedance seen at REFIN does not change. The PGA can be set to gains of 1, 2, 4, 8, or 16. These gain settings with their resulting full-scale range and typical voltage range are shown in Table I. Keep in mind that higher Turbo Mode Rates result in fewer available gain settings as shown in Table II. SOFTWARE GAIN The excellent performance, flexibility, and low cost of the ADS1212/13 allow the converter to be considered for designs which would not normally need a 24-bit ADC. For example, many designs utilize a 12-bit converter and a highgain INA or PGA for digitizing low amplitude signals. For some of these cases, the ADS1212/13 by itself may be a solution, even though the maximum gain is limited to 16. To get around the gain limitation, the digital result can simply be shifted up by “n” bits in the main controller— resulting in a gain of “n” times G, where G is the gain setting. While this type of manipulation of the output data is obvious, it is easy to miss how much the gain can be increased in this manner on a 24-bit converter. For example, shifting the result up by three bits when the ADS1212/13 is set to a gain of 16 results in an effective gain of 128. At lower data rates, the converter can easily provide more than 12 bits of resolution. Even higher gains are possible. The limitation is a combination of the needed data rate, desired noise performance, and desired linearity. ADS1212, 1213 SBAS064A CALIBRATION The ADS1212/13 offers several different types of calibration, and the particular calibration desired is programmed via the Command Register. In the case of Background Calibration, the calibration will repeat at regular intervals indefinitely. For all others, the calibration is performed once and then normal operation is resumed. Each type of calibration is covered in detail in its respective section. In general, calibration is recommended immediately after power-on and whenever there is a “significant” change in the operating environment. The amount of change which should cause a re-calibration is dependent on the application, effective resolution, etc. Where high accuracy is important, re-calibration should be done on changes in temperature and power supply. In all cases, re-calibration should be done when the gain, Turbo Mode, or data rate is changed. After a calibration has been accomplished, the Offset Calibration Register and the Full-Scale Calibration Register contain the results of the calibration. The data in these registers are accurate to the effective resolution of the ADS1212/13’s mode of operation during the calibration. Thus, these values will show a variation (or noise) equivalent to a regular conversion result. For those cases where this error must be reduced, it is tempting to consider running the calibration at a slower data rate and then increasing the converter’s data rate after the calibration is complete. Unfortunately, this will not work as expected. The reason is that the results calculated at the slower data rate would not be valid for the higher data rate. Instead, the calibration should be done repeatedly. After each calibration, the results can be read and stored. After the desired number of calibrations, the main controller can compute an average and write this value into the calibration registers. The resulting error in the calibration values will be reduced by the square root of the number of calibrations which were averaged. The calibration registers can also be used to provide system offset and gain corrections separate from those computed by the ADS1212/13. For example, these might be burned into E2PROM during final product testing. On power-on, the main controller would load these values into the calibration registers. A further possibility is a look-up table based on the current temperature. Note that the values in the calibration registers will vary from configuration to configuration and from part to part. There is no method of reliably computing what a particular calibration register should be to correct for a given amount of system error. It is possible to present the ADS1212/13 with a known amount of error, perform a calibration, read the desired calibration register, change the error value, perform another calibration, read the new value and use these values to interpolate an intermediate value. 13 Normal Mode Valid Data Valid Data Normal Mode Self-Calibration Mode Offset Calibration on Internal Offset(2) Full-Scale Calibration on Internal Full-Scale Analog Input Conversion Valid Data Valid Data DRDY SC(1) Serial I/O tDATA NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles. FIGURE 5. Self-Calibration Timing. Self-Calibration A self-calibration is performed after the bits 001 have been written to the Command Register Operation Mode bits (MD2 through MD0). This initiates the following sequence at the start of the next conversion cycle (see Figure 5). The DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence. The inputs to the sampling capacitor are disconnected from the converter’s analog inputs and are shorted together. An offset calibration is performed over the next three conversion periods (four in Slave Mode). Then, the input to the sampling capacitor is connected across REFIN, and a full-scale calibration is performed over the next three conversions. After this, the Operation Mode bits are reset to 000 (Normal Mode) and the input capacitor is reconnected to the input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time. On the start of the fourth cycle , DRDY goes LOW indicating valid data and resumption of normal operation. System Offset Calibration A system offset calibration is performed after the bits 010 have been written to the Command Register Operation Mode bits (MD2 through MD0). This initiates the following sequence (see Figure 6). At the start of the next conversion cycle, the DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence. The offset calibration will be performed on the differential input voltage present at the converter’s input over the next three conversion periods (four in Slave Mode). When this is done, the Operation Normal Mode Valid Data Valid Data System Offset Calibration Mode Offset Calibration on System Offset(2) Mode bits are reset to 000 (Normal Mode). A single conversion is done with DRDY HIGH. After this conversion, the DRDY signal goes LOW indicating resumption of normal operation. Normal operation returns within a single conversion cycle because it is assumed that the input voltage at the converter’s input is not removed immediately after the offset calibration is performed. In this case, the digital filter already contains a valid result. For full system calibration, offset calibration must be performed first and then full-scale calibration. In addition, the offset calibration error will be the rms sum of the conversion error and the noise on the system offset voltage. See the System Calibration Limits section for information regarding the limits on the magnitude of the system offset voltage. System Full-Scale Calibration A system full-scale calibration is performed after the bits 011 have been written to the Command Register Operation Mode bits (MD2 through MD0). This initiates the following sequence (see Figure 7). At the start of the next conversion cycle, the DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence. The full-scale calibration will be performed on the differential input voltage (2 • REFIN/G) present at the converter’s input over the next three conversion periods (four in Slave Mode). When this is done, the Operation Mode bits are reset to 000 (Normal Mode). A single conversion is done with DRDY HIGH. After this conversion, the DRDY signal goes LOW indicating resumption of normal operation. Normal Mode Normal Mode Analog Possibly Valid Input Conversion Data Possibly Valid Data Valid Data Valid Data System Full-Scale Calibration Mode Full-Scale Calibration on System Full-Scale(2) Normal Mode Analog Possibly Valid Input Conversion Data Possibly Valid Data DRDY DRDY SFSC(1) SOC(1) Serial I/O tDATA tDATA NOTES: (1) SOC = System Offset Calibration instruction. (2) In Slave Mode, this function requires 4 cycles. FIGURE 6. System Offset Calibration Timing. 14 Serial I/O NOTES: (1) SFSC = System Full-Scale Calibration instruction. (2) In Slave Mode, this function requires 4 cycles. FIGURE 7. System Full-Scale Calibration Timing. ADS1212, 1213 SBAS064A Normal operation returns within a single conversion cycle because it is assumed that the input voltage at the converter’s input is not removed immediately after the full-scale calibration is performed. In this case, the digital filter already contains a valid result. the input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time. On the next cycle, the DRDY signal goes LOW indicating valid data and resumption of normal operation. For full system calibration, offset calibration must be performed first and then full-scale calibration. The calibration error will be a sum of the rms noise on the conversion result and the input signal noise. See the System Calibration Limits section for information regarding the limits on the magnitude of the system full-scale voltage. The system offset calibration range of the ADS1212/13 is limited and is listed in the Specifications Table. For more information on how to use these specifications, see the System Calibration Limits section. To calculate VOS, use 2 • REFIN / GAIN for VFS. Pseudo System Calibration The Pseudo System Calibration is performed after the bits 100 have been written to the Command Register Operation Mode bits (MD2 through MD0). This initiates the following sequence (see Figure 8). At the start of the next conversion cycle, the DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence. The offset calibration will be performed on the differential input voltage present at the converter’s input over the next three conversion periods (four in Slave Mode). Then, the input to the sampling capacitor is disconnected from the converter’s analog input and connected across REFIN. A gain calibration is performed over the next three conversions. After this, the Operation Mode bits are reset to 000 (Normal Mode) and the input capacitor is then reconnected to Normal Mode Valid Data Normal Mode Pseudo System Calibration Mode Offset Calibration on System Offset(2) Valid Data Background Calibration The Background Calibration Mode is entered after the bits 101 have been written to the Command Register Operation Mode bits (MD2 through MD0). This initiates the following continuous sequence (see Figure 9). At the start of the next conversion cycle, the DRDY signal will not go LOW but will remain HIGH. The inputs to the sampling capacitor are disconnected from the converter’s analog input and shorted together. An offset calibration is performed over the next three conversion periods (in Slave Mode, the very first offset calibration requires four periods, and all subsequent offset calibrations require three periods). Then, the input capacitor is reconnected to the input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time. On the next cycle, the DRDY signal goes LOW indicating valid data. Full-Scale Calibration on Internal Full-Scale Analog Input Conversion Valid Data Valid Data DRDY PSC(1) Serial I/O tDATA NOTES: (1) PSC = Pseudo System Calibration instruction. (2) In Slave Mode, this function requires 4 cycles. FIGURE 8. Pseudo System Calibration Timing. Normal Mode Valid Data Valid Data Background Calibration Mode Offset Calibration on Internal Offset(2) Analog Input Conversion Full-Scale Calibration on Internal Full-Scale Analog Input Conversion Cycle Repeats with Offset Calibration DRDY BC(1) Serial I/O tDATA NOTES: (1) BC = Background Calibration instruction. (2) In Slave Mode, the very first offset calibration will require 4 cycles. All subsequent offset calibrations will require 3 cycles. FIGURE 9. Background Calibration Timing. ADS1212, 1213 SBAS064A 15 Also, during this cycle, the sampling capacitor is disconnected from the converter’s analog input and is connected across REFIN. A gain calibration is initiated and proceeds over the next three conversions. After this, the input capacitor is once again connected to the analog input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time. On the next cycle, the DRDY signal goes LOW indicating valid data, the input to the sampling capacitor is shorted, and an offset calibration is initiated. At this point, the Background Calibration sequence repeats. In essence, the Background Calibration Mode performs continuous self-calibration where the offset and gain calibrations are interleaved with regular conversions. Thus, the data rate is reduced by a factor of 6. The advantage is that the converter is continuously adjusting to environmental changes such as ambient or component temperature (due to airflow variations). The ADS1212/13 will remain in the Background Calibration Mode indefinitely. To move to any other mode, the Command Register Operation Mode bits (MD2 through MD0) must be set to the appropriate values. System Calibration Offset and Full-Scale Calibration Limits The System Offset and Full-Scale Calibration range of the ADS1212/13 is limited and is listed in the Specifications Table. The range is specified as: (VFS – | VOS |) < 1.3 • (2 • REFIN)/GAIN (VFS – | VOS |) > 0.7 • (2 • REFIN)/GAIN where VFS is the system full-scale voltage and | VOS | is the absolute value of the system offset voltage. In the following discussion, keep in mind that these voltages are differential voltages. For example, with the internal reference (2.5V) and a gain of two, the previous equations become (after some manipulation): VFS – 3.25 < VOS < VFS – 1.75 If VFS is perfect at 2.5V (positive full-scale), then VOS must be greater than –0.75V and less than 0.75V. Thus, when offset calibration is performed, the positive input can be no more than 0.75V below or above the negative input. If this range is exceeded, the ADS1212/13 may not calibrate properly. This calculation method works for all gains other than one. For a gain of one and the internal reference (2.5V), the equation becomes: VFS – 6.5 < VOS < VFS – 3.5 With a 5V positive full-scale input, VOS must be greater than –1.5V and less than 1.5V. Since the offset represents a common-mode voltage and the input voltage range in a gain of one is 0V to 5V, a common-mode voltage will cause the actual input voltage to possibly go below 0V or above 5V. The specifications also show that for the specifications to be valid, the input voltage must not go below AGND by more than 30mV or above AVDD by more than 30mV. 16 This will be an important consideration in many systems which use a 2.5V or greater reference, as the input range is constrained by the expected power supply variations. In addition, the expected full-scale voltage will impact the allowable offset voltage (and vice-versa) as the combination of the two must remain within the power supply and ground potentials, regardless of the results obtained via the range calculation shown previously. There are only two solutions to this constraint: either the system design must ensure that the full-scale and offset voltage variations will remain within the power supply and ground potentials, or the part must be used in a gain of 2 or greater. SLEEP MODE The Sleep Mode is entered after the bits 110 have been written to the Command Register Operation Mode bits (MD2 through MD0). This mode is exited by entering a new mode into the MD2-MD0 bits. The Sleep Mode causes the analog section and a good deal of the digital section to power down. For full analog power down, the VBIAS generator and the internal reference must also be powered down by setting the BIAS and REFO bits in the Command Register accordingly. The power dissipation shown in the Specifications Table is with the internal reference and the VBIAS generator disabled. To establish serial communication with the converter while it is in Sleep Mode, one of the following procedures must be used: If CS is being used, simply taking CS LOW will enable serial communication to proceed normally. If CS is not being used (tied LOW) and the ADS1212/13 is in the Master Mode, then a falling edge must be produced on the SDIO line. If SDIO is LOW, the SDIO line must be taken HIGH for 4 • tXIN periods (minimum) and then taken LOW. Alternatively, SDIO can be forced HIGH after putting the ADS1212/13 to “sleep” and then taken LOW when the Sleep Mode is to be exited. Finally, if CS is not being used (tied LOW) and the ADS1212/13 is in the Slave Mode, then simply sending a normal Instruction Register command will re-establish communication. Once serial communication is resumed, the Sleep Mode is exited by changing the MD2-MD0 bits to any other mode. When a new mode (other than Sleep) has been entered, the ADS1212/13 will execute a very brief internal power-up sequence of the analog and digital circuitry. Once this has been done, one normal conversion cycle is performed before the new mode is actually entered. At the end of this conversion cycle, the new mode takes effect and the converter will respond accordingly. The DRDY signal will remain HIGH through the first conversion cycle. It will also remain HIGH through the second, even if the new mode is the Normal Mode. If the VBIAS generator and/or the internal reference have been disabled, then they must be manually re-enabled via the appropriate bits in the Command Register. In addition, the internal reference will have to charge the external bypass capacitor(s) and possibly other circuitry. There may also be ADS1212, 1213 SBAS064A considerations associated with VBIAS and the settling of external circuitry. All of these must be taken into account when determining the amount of time required to resume normal operation. The timing diagram shown in Figure 10 does not take into account the settling of external circuitry. Change to Normal Mode Occurs Here Sleep Mode One (Other Normal Modes Conversion Start Here) Data Not Valid Valid Data(1) Valid Data(1) DRDY Serial I/O tDATA NOTE: (1) Assuming that the external circuitry has been stable for the previous three tDATA periods. FIGURE 10. Sleep Mode to Normal Mode Timing. ANALOG OPERATION ANALOG INPUT The input impedance of the analog input changes with ADS1212/13 clock frequency (fXIN), gain (G), and Turbo Mode Rate (TMR). The relationship is: the analog signal must reside within this range, the linearity of the ADS1212/13 is only ensured when the actual analog input voltage resides within a range defined by AGND – 30mV and AVDD +30mV. This is due to leakage paths which occur within the part when AGND and AVDD are exceeded. For this reason, the 0V to 5V input range (gain of 1 with a 2.5V reference) must be used with caution. Should AVDD be 4.75V, the analog input signal would swing outside of the tested specifications of the device. Designs utilizing this mode of operation should consider limiting the span to a slightly smaller range. Common-mode voltages are also a significant concern in this mode and must be carefully analyzed. An input voltage range of 0.75V to 4.25V is the smallest span that is allowed if a full system calibration will be performed (see the Calibration section for more details). This also assumes an offset error of zero. A better choice would be 0.5V to 4.5V (a full-scale range of 9V). This span would allow some offset error, gain error, power supply drift, and common-mode voltage while still providing full system calibration over reasonable variation in each of these parameters. The actual input voltage exceeding AGND or AVDD should not be a concern in higher gain settings as the input voltage range will reside well within 0V to 5V. This is true unless the common-mode voltage is large enough to place positive fullscale or negative full-scale outside of the AGND to AVDD range. AIN Impedance (Ω) = (1MHz/fXIN)•20E6/(G•TMR) Figure 11 shows the basic input structure of the ADS1212. The ADS1213 includes an input multiplexer, but this has little impact on the analysis of the input structure. The impedance is directly related to the sampling frequency of the input capacitor. The XIN clock rate sets the basic sampling rate in a gain of 1 and Turbo Mode Rate of 1. Higher gains and higher Turbo Mode Rates result in an increase of the sampling rate, while slower clock (XIN) frequencies result in a decrease. RSW (8kΩ typical) High Impedance > 1GΩ AIN Switching Frequency = fSAMP CINT 5pF Typical VCM FIGURE 11. Analog Input Structure. This input impedance can become a major point of consideration in some designs. If the source impedance of the input signal is significant or if there is passive filtering prior to the ADS1212/13, then a significant portion of the signal can be lost across this external impedance. How significant this effect is depends on the desired system performance. There are two restrictions on the analog input signal to the ADS1212/13. Under no conditions should the current into or out of the analog inputs exceed 10mA. In addition, while ADS1212, 1213 SBAS064A REFERENCE INPUT The input impedance of the REFIN input changes with clock frequency (fXIN) and Turbo Mode Rate (TMR). The relationship is: REFIN Impedance (Ω) = (1MHz/fXIN)•5E6/TMR Unlike the analog input, the reference input impedance has a negligible dependency on the PGA gain setting. The reference input voltage can vary between 2V and 3V. A nominal voltage of 2.5V appears at REFOUT, and this can be directly connected to REFIN. Higher reference voltages will cause the full-scale range to increase while the internal circuit noise of the converter remains approximately the same. This will increase the LSB weight but not the internal noise, resulting in increased signal-to-noise ratio and effective resolution. Likewise, lower reference voltages will decrease the signal-to-noise ratio and effective resolution. REFERENCE OUTPUT The ADS1212/13 contains an internal +2.5V reference. Tolerances, drift, noise, and other specifications for this reference are given in the Specification Table. Note that it is not designed to sink or to source more than 1mA of current. In addition, loading the reference with a dynamic or variable load is not recommended. This can result in small changes in reference voltage as the load changes. Finally, for designs approaching or exceeding 20 bits of effective resolution, a low-noise external reference is recommended as the internal reference may not have adequate performance. 17 R1 3kΩ ±10V AINP REFIN ±10V AINN REFOUT R2 3kΩ R3 1kΩ R4 1kΩ AGND AVDD VBIAS DVDD C1 6pF GND DGND C2 6pF AVDD AGND MODE ADS1212 DRDY CS DGND DSYNC XTAL 1.0µF SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 12. ±10V Input Configuration Using VBIAS. The circuitry which generates the +2.5V reference can be disabled via the Command Register and will result in a lower power dissipation. The reference circuitry consumes a little over 1.6mA of current with no external load. When the ADS1212/13 is in its default state, the internal reference is enabled. VBIAS The VBIAS output voltage is dependent on the reference input (REFIN) voltage and is approximately 1.33 times as great. This output is used to bias input signals such that bipolar signals with spans of greater than 5V can be scaled to match the input range of the ADS1212/13. Figure 12 shows a connection diagram which will allow the ADS1212/13 to accept a ±10V input signal (40V full-scale range). This method of scaling and offsetting the ±20V differential input signal will be a concern for those requiring minimum power dissipation. VBIAS will supply 1.68mA for every channel connected as shown. For the ADS1213, the current draw is within the specifications for VBIAS, but, at 12mW, the power dissipation is significant. If this is a concern, resistors R1 and R2 can be set to 9kΩ and R3 and R4 to 3kΩ. This will reduce power dissipation by one-third. In addition, these resistors can also be set to values which will provide any arbitrary input range. In all cases, the maximum current into or out of VBIAS should not exceed its specification of 10mA. Note that the connection diagram shown in Figure 12 causes a constant amount of current to be sourced by VBIAS. This will be very important in higher resolution designs as the voltage at VBIAS will not change with loading, as the load is constant. However, if the input signal is single-ended and one side of the input is grounded, the load will not be constant and VBIAS will change slightly with the input signal. Also, in all cases, note that noise on VBIAS introduces a common-mode error signal which is rejected by the converter. The circuitry to generate VBIAS is disabled when the ADS1212/13 is in its default state, and it must be enabled, via the Command Register, in order for the VBIAS voltage to be present. When enabled, the VBIAS circuitry consumes approximately 1mA with no external load. 18 On power-up, external signals may be present before VBIAS is enabled. This can create a situation in which a negative voltage is applied to the analog inputs (–2.5V for the circuit shown in Figure 12), reverse biasing the negative input protection diode. This situation should not be a problem as long as the resistors R1 and R2 limit the current being sourced by each analog input to under 10mA (a potential of 0V at the analog input pin should be used in the calculation). DIGITAL OPERATION SYSTEM CONFIGURATION The Micro Controller (MC) consists of an ALU and a register bank. The MC has two states: power-on reset and convert. In the power-on reset state, the MC resets all the registers to their default state, sets up the modulator to a stable state, and performs self-calibration at a 340Hz data rate. After this, it enters the Convert Mode, which is the normal mode of operation for the ADS1212/13. The ADS1212/13 has 5 internal registers, as shown in Table VII. Two of these, the Instruction Register and the Command Register, control the operation of the converter. The Data Output Register (DOR) contains the result from the most recent conversion. The Offset and Full-Scale Calibration Registers (OCR and FCR) contain data used for correcting the internal conversion result before it is placed into the DOR. The data in these two registers may be the result of a calibration routine, or they may be values which have been written directly via the serial interface. INSR DOR CMR OCR FCR Instruction Register Data Output Register Command Register Offset Calibration Register Full-Scale Calibration Register 8 Bits 24 Bits 32 Bits 24 Bits 24 Bits TABLE VII. ADS1212/13 Registers. Communication with the ADS1212/13 is controlled via the Instruction Register (INSR). Under normal operation, the INSR is written as the first part of each serial communication. The instruction that is sent determines what type of communication will occur next. It is not possible to read the INSR. ADS1212, 1213 SBAS064A The Command Register (CMR) controls all of the ADS1212/ 13’s options and operating modes. These include the PGA gain setting, the Turbo Mode Rate, the output data rate (decimation ratio), etc. The CMR is the only 32-bit register within the ADS1212/13. It, and all the remaining registers, may be read from or written to. Instruction Register (INSR) The INSR is an 8-bit register which commands the serial interface either to read or to write “n” bytes beginning at the specified register location. Table VIII shows the format for the INSR. MSB R/W LSB MB1 MB0 0 A3 A2 A1 A0 TABLE VIII. Instruction Register. R/W (Read/Write) Bit—For a write operation to occur, this bit of the INSR must be 0. For a read, this bit must be 1, as follows: Each serial communication starts with the 8-bits of the INSR being sent to the ADS1212/13. This directs the remainder of the communication cycle, which consists of n bytes being read from or written to the ADS1212/13. The read/write bit, the number of bytes n, and the starting register address are defined, as shown in Table VIII. When the n bytes have been transferred, the INSR is complete. A new communication cycle is initiated by sending a new INSR (under restrictions outlined in the Interfacing section). Command Register (CMR) The CMR controls all of the functionality of the ADS1212/ 13. The new configuration takes effect on the negative transition of SCLK for the last bit in each byte of data being written to the command register. The organization of the CMR is shown in Table X. Most Significant Bit Byte 3 DSYNC(1) BIAS REFO 0 Off DF U/B BD MSB 0 1 Write Read MB1, MB0 (Multiple Bytes) Bits—These two bits are used to control the word length (number of bytes) of the read or write operation, as follows: MD1 MD0 G2 G1 G0 MB1 MB0 0 0 1 1 0 1 0 1 1 Byte 2 Bytes 3 Bytes 4 Bytes A3-A0 (Address) Bits—These four bits select the beginning register location which will be read from or written to, as shown in Table IX. Each subsequent byte will be read from or written to the next higher location. (If the BD bit in the Command Register is set, each subsequent byte will be read from the next lower location. This bit does not affect the write operation.) If the next location is not defined in Table IX, then the results are unknown. Reading or writing continues until the number of bytes specified by MB1 and MB0 have been transferred. A1 A0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 REGISTER BYTE Data Output Register Byte 2 (MSB) Data Output Register Byte 1 Data Output Register Byte 0 (LSB) Command Register Byte 3 (MSB) Command Register Byte 2 Command Register Byte 1 Command Register Byte 0 (LSB) Offset Cal Register Byte 2 (MSB) Offset Cal Register Byte 1 Offset Cal Register Byte 0 (LSB) Full-Scale Cal Register Byte 2 (MSB) Full-Scale Cal Register Byte 1 Full-Scale Cal Register Byte 0 (LSB) Note: MSB = Most Significant Byte, LSB = Least Significant Byte TABLE IX. A3-A0 Addressing. ADS1212, 1213 SBAS064A CH1 000 Gain 1 Defaults CH0 00 Channel 1 Defaults Byte 1 SF2 SF1 SF0 DR12 DR11 000 Turbo Mode Rate of 1 A2 0 Byte 2 MD2 000 Normal Mode 0 0 0 0 0 0 0 1 1 1 1 1 1 DRDY 1 On 0 Two’s 0 Biplr 0 MSByte 0 MSB 0 SDIO NOTE: (1) DSYNC is Write only, DRDY is Read only. R/W A3 SDL DR7 DR6 DR5 DR4 DR10 DR9 DR8 00000 Defaults Byte 0 Least Significant Bit DR3 DR2 DR1 (00000) 0001 0111 (23) Data Rate of 326Hz DR0 Defaults TABLE X. Organization of the Command Register and Default Status. BIAS (Bias Voltage) Bit—The BIAS bit controls the VBIAS output state—either on (1.33 • REFIN) or off (disabled), as follows: BIAS VBIAS GENERATOR VBIAS STATUS 0 1 Off On Disabled 1.33•REFIN Default The VBIAS circuitry consumes approximately 1mA of steady state current with no external load. See the VBIAS section for full details. When the internal reference (REFOUT) is connected to the reference input (REFIN), VBIAS is 3.3V, nominal. REFO (Reference Output) Bit—The REFO bit controls the internal reference (REFOUT) state, either on (2.5V) or off (disabled), as follows: REFO INTERNAL REFERENCE REFOUT STATUS 0 1 Off On High Impedance 2.5V Default The internal reference circuitry consumes approximately 1.6mA of steady state current with no external load. See the Reference Output section for full details on the internal reference. 19 DF (Data Format) Bit—The DF bit controls the format of the output data, either Two’s Complement or Offset Binary, as follows: DF FORMAT ANALOG INPUT DIGITAL OUTPUT SDL SERIAL DATA OUTPUT PIN 0 1 SDIO SDOUT 0 Two’s Complement +Full-Scale Zero –Full-Scale 7FFFFFH 000000H 800000H 1 Offset Binary +Full-Scale Zero –Full-scale FFFFFFH 800000H 000000H Default These two formats are the same for all bits except the most significant, which is simply inverted in one format vs the other. This bit only applies to the Data Output Register—it has no effect on the other registers. U/B (Unipolar) Bit—The U/B bit controls the limits imposed on the output data, as follows: U/B MODE LIMITS 0 1 Bipolar Unipolar None Zero to +Full-Scale only Default The particular mode has no effect on the actual full-scale range of the ADS1212/13, data format, or data format vs input voltage. In the bipolar mode, the ADS1212/13 operates normally. In the unipolar mode, the conversion result is limited to positive values only (zero included). This bit only controls what is placed in the Data Output Register. It has no effect on internal data. When cleared, the very next conversion will produce a valid bipolar result. BD (Byte Order) Bit—The BD bit controls the order in which bytes of data are read, either most significant byte first or least significant byte, as follows: BD BYTE ACCESS ORDER 0 Most Significant to Least Significant Byte 1 Least Significant to Most Significant Byte MSB (Bit Order) Bit—The MSB bit controls the order in which bits within a byte of data are read, either most significant bit first or least significant bit, as follows: MSB BIT ORDER 0 1 Most Significant Bit First Least Significant Bit First Default If SDL is LOW, then SDIO will be used for both input and output of serial data—see the Timing section for more details on how the SDIO pin transitions between these two states. In addition, SDOUT will remain in a tri-state condition at all times. Important Note: Since the default condition is SDL LOW, SDIO has the potential of becoming an output once every data output cycle if the ADS1212/13 is in the Master Mode. This will occur until the Command Register can be written and the SDL bit set HIGH. See the Interfacing section for more information. DRDY (Data Ready) Bit—The DRDY bit is a read-only bit which reflects the state of the ADS1212/13’s DRDY output pin, as follows: DRDY 0 1 MEANING Data Ready Data Not Ready DSYNC (Data Synchronization) Bit—The DSYNC bit is a write-only bit which occupies the same location as DRDY. When a ‘one’ is written to this location, the effect on the ADS1212/13 is the same as if the DSYNC input pin had been taken LOW and returned HIGH. That is, the modulator count for the current conversion cycle will be reset to zero. DSYNC MEANING 0 1 No Change in Modulator Count Modulator Count Reset to Zero Default Note that when BD is clear and a multi-byte read is initiated, A3-A0 of the Instruction Register is the address of the most significant byte and subsequent bytes reside at higher addresses. If BD is set, then A3-A0 is the address of the least significant byte and subsequent bytes reside at lower addresses. The BD bit only affects read operations; it has no effect on write operations. Default The MSB bit only effects read operations; it has no affect on write operations. 20 SDL (Serial Data Line) Bit—The SDL bit controls which pin on the ADS1212/13 will be used as the serial data output pin, either SDIO or SDOUT, as follows: The DSYNC bit is provided in order to reduce the number of interface signals that are needed between the ADS1212/13 and the main controller. Consult “Making Use of DSYNC” in the Serial Interface section for more information. MD2-MD0 (Operating Mode) Bits—The MD2-MD0 bits initiate or enable the various calibration sequences, as follows: MD2 MD1 MD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 OPERATING MODE Normal Mode Self-Calibration System Offset Calibration System Full-Scale Calibration Pseudo System Calibration Background Calibration Sleep Reserved The Normal Mode, Background Calibration Mode, and Sleep Mode are permanent modes and the ADS1212/13 will remain in these modes indefinitely. All other modes are temporary and will revert to Normal Mode once the appropriate actions are complete. See the Calibration and Sleep Mode sections for more information. ADS1212, 1213 SBAS064A DATA RATE (HZ) DECIMATION RATIO DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 391 250 100 60 50 20 10 0.96 19 30 77 129 155 390 780 8000 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 Table XI. Decimation Ratios for Various Data Rates (Turbo Mode Rate of 1 and 1MHz clock). G2-G0 (PGA Control) Bits—The G2-G0 bits control the gain setting of the PGA, as follows: G2 G1 G0 GAIN SETTING 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 2 4 8 16 AVAILABLE TURBO MODE RATES 1, 2, 4, 8, 16 1, 2, 4, 8 1, 2, 4 1, 2 1 fSAMP = G • TMR • fXIN / 128 fMOD = TMR • fXIN / 128 Default The gain is partially implemented by increasing the input capacitor sampling frequency, which is given by the following equation: fSAMP = G • TMR • fXIN /128 where G is the gain setting and TMR is the Turbo Mode Rate. The product of G and TMR cannot exceed 16. The sampling frequency of the input capacitor directly relates to the analog input impedance. See the Programmable Gain Amplifier and Analog Input sections for more details. CH1-CH0 (Channel Selection) Bits—The CH1 and CH0 bits control the input multiplexer on the ADS1213, as follows: CH1 CH0 0 0 1 1 0 1 0 1 ACTIVE INPUT Channel Channel Channel Channel 1 2 3 4 The input capacitor sampling frequency and modulator rate can be calculated from the following equations: Default (For the ADS1212, CH1 and CH0 must always be zero.) The channel change takes effect when the last bit of byte 2 has been written to the Command Register. Output data will not be valid for the next three conversions despite the DRDY signal indicating that data is ready. On the fourth time that DRDY goes LOW after a channel change has been written to the Command Register, valid data will be present in the Data Output Register (see Figure 4). SF2-SF0 (Turbo Mode Rate) Bits—The SF2-SF0 bits control the input capacitor sampling frequency and modulator rate, as follows: where G is the gain setting and TMR is the Turbo Mode Rate. The sampling frequency of the input capacitor directly relates to the analog input impedance. The modulator rate relates to the power consumption of the ADS1212/13 and the output data rate. See the Turbo Mode, Analog Input, and Reference Input sections for more details. DR12-DR0 (Decimation Ratio) Bits—The DR12-DR0 bits control the decimation ratio of the ADS1212/13. In essence, these bits set the number of modulator results which are used in the digital filter to compute each individual conversion result. Since the modulator rate depends on both the ADS1212/13 clock frequency and the Turbo Mode Rate, the actual output data rate is given by the following equation: fDATA = fXIN • TMR / (128 • (Decimation Ratio + 1)) where TMR is the Turbo Mode Rate. Table XI shows various data rates and corresponding decimation ratios (with a 1MHz clock). Valid decimation ratios are from 19 to 8000. Outside of this range, the digital filter will compute results incorrectly due to inadequate or too much data. Data Output Register (DOR) The DOR is a 24-bit register which contains the most recent conversion result (see Table XII). This register is updated with a new result just prior to DRDY going LOW. If the contents of the DOR are not read within a period of time defined by 1/fDATA –24•(1/fXIN), then a new conversion result will overwrite the old. (DRDY is forced HIGH prior to the DOR update, unless a read is in progress). Most Significant Bit DOR22 DOR21 DOR20 DOR15 DOR14 DOR13 DOR12 SF2 SF1 SF0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 2 4 8 16 ADS1212, 1213 SBAS064A AVAILABLE PGA SETTINGS 1, 2, 4, 8, 16 1, 2, 4, 8 1, 2, 4 1, 2 1 DOR19 DOR18 DOR17 DOR16 DOR10 DOR9 Byte 1 DOR11 Byte 0 DOR7 TURBO MODE RATE Byte 2 DOR23 DOR6 DOR5 DOR4 DOR3 DOR8 Least Significant Bit DOR2 DOR1 DOR0 TABLE XII. Data Output Register. Default The contents of the DOR can be in Two’s Complement or Offset Binary format. This is controlled by the DF bit of the Command Register. In addition, the contents can be limited to unipolar data only with the U/B bit of the Command Register. 21 Offset Calibration Register (OCR) The OCR is a 24-bit register which contains the offset correction factor that is applied to the conversion result before it is placed in the Data Output Register (see Table XIII). In most applications, the contents of this register will be the result of either a self-calibration or a system calibration. The OCR is both readable and writeable via the serial interface. For applications requiring a more accurate offset calibration, multiple calibrations can be performed, each resulting OCR value read, the results averaged, and a more precise offset calibration value written back to the OCR. The actual OCR value will change from part-to-part and with configuration, temperature, and power supply. Thus, the actual OCR value for any arbitrary situation cannot be accurately predicted. That is, a given system offset could not be corrected simply by measuring the error externally, computing a correction factor, and writing that value to the OCR. In addition, be aware that the contents of the OCR are not used to directly correct the conversion result. Rather, the correction is a function of the OCR value. This function is linear and two known points can be used as a basis for interpolating intermediate values for the OCR. Consult the Calibration section for more details. Most Significant Bit OCR23 OCR22 Byte 2 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16 OCR10 OCR9 OCR8 The actual FCR value will change from part-to-part and with configuration, temperature, and power supply. Thus, the actual FCR value for any arbitrary situation cannot be accurately predicted. That is, a given system full-scale error cannot be corrected simply by measuring the error externally, computing a correction factor, and writing that value to the FCR. In addition, be aware that the contents of the FCR are not used to directly correct the conversion result. Rather, the correction is a function of the FCR value. This function is linear and two known points can be used as a basis for interpolating intermediate values for the FCR. Consult the Calibration section for more details. The contents of the FCR are in unsigned binary format. This is not affected by the DF bit in the Command Register. TIMING Table XV and Figures 13 through 21 define the basic digital timing characteristics of the ADS1212/13. Figure 13 and the associated timing symbols apply to the XIN input signal. Figures 14 through 20 and associated timing symbols apply to the serial interface signals (SCLK, SDIO, SDOUT, and CS) and their relationship to DRDY. The serial interface is discussed in detail in the Serial Interface section. Figure 21 and the associated timing symbols apply to the maximum DRDY rise and fall times. Byte 1 OCR15 OCR14 OCR13 OCR12 OCR11 Byte 0 OCR7 OCR6 OCR5 OCR4 tXIN t2 Least Significant Bit OCR3 OCR2 OCR1 OCR0 t3 XIN TABLE XIII. Offset Calibration Register. The contents of the OCR are in Two’s Complement format. This is not affected by the DF bit in the Command Register. Full-Scale Calibration Register (FCR) The FCR is a 24-bit register which contains the full-scale correction factor that is applied to the conversion result before it is placed in the Data Output Register (see Table XIV). In most applications, the contents of this register will be the result of either a self-calibration or a system calibration. Most Significant Bit FSR23 FSR22 Byte 2 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 FSR11 FSR10 FSR9 FSR8 Byte 1 FSR15 FSR14 FSR13 FSR12 Byte 0 FSR7 FSR6 FSR5 FSR4 FIGURE 13. XIN Clock Timing. t4 t5 t6 t8 SCLK (Internal) t7 t9 SDIO (as input) SDOUT (or SDlO as output) FIGURE 14. Serial Input/Output Timing, Master Mode. Least Significant Bit FSR3 FSR2 FSR1 FSR0 TABLE XIV. Full-Scale Calibration Register. The FCR is both readable and writable via the serial interface. For applications requiring a more accurate full-scale calibration, multiple calibrations can be performed, each resulting FCR value read, the results averaged, and a more precise calibration value written back to the FCR. t10 t11 t12 t14 SCLK (External) t13 t15 SDIO (as input) SDOUT (or SDlO as output) FIGURE 15. Serial Input/Output Timing, Slave Mode. 22 ADS1212, 1213 SBAS064A SYMBOL DESCRIPTION MIN NOM MAX UNITS fXIN XIN Clock Frequency 0.5 1 2.5 MHz tXIN XIN Clock Period 400 XIN Clock High 0.4 • tXIN t3 XIN Clock LOW 0.4 • tXIN t4 Internal Serial Clock HIGH 2 • tXIN ns t5 Internal Serial Clock LOW 2 • tXIN ns t6 Data In Valid to Internal SCLK Falling Edge (Setup) 40 t7 Internal SCLK Falling Edge to Data In Not Valid (Hold) 20 ns t8 Data Out Valid to Internal SCLK Falling Edge (Setup) 2 • tXIN –25 ns t2 2000 ns ns ns ns t9 Internal SCLK Falling Edge to Data Out Not Valid (Hold) 2 • tXIN ns t10 External Serial Clock HIGH 5 • tXIN ns t11 External Serial Clock LOW 5 • tXIN ns t12 Data In Valid to External SCLK Falling Edge (Setup) 40 ns t13 External SCLK Falling Edge to Data In Not Valid (Hold) 20 ns t14 Data Out Valid to External SCLK Falling Edge (Setup) tXIN –40 ns 4 • tXIN t15 External SCLK Falling Edge to Data Out Not Valid (Hold) t16 Falling Edge of DRDY to First SCLK Rising Edge (Mode, CS Tied LOW) 12 • tXIN ns ns t17 Falling Edge of Last SCLK for INSR to Rising Edge of First SCLK for Register Data (Master Mode) 10 • tXIN ns t18 Falling Edge of Last SCLK for Register Data to Rising Edge of DRDY (Master Mode) 6 • tXIN ns t19 Falling Edge of Last SCLK for INSR to Rising Edge of First SCLK for Register Data (Slave Mode) 13 • tXIN t20 Falling Edge of Last SCLK for Register Data to Rising Edge of DRDY (Slave Mode) 8 • tXIN t21 Falling Edge of DRDY to Falling Edge of CS (Master and Slave Mode) 3 • tXIN t22 Falling Edge of CS to Rising Edge of SCLK (Master Mode) 10 • tXIN t23 Rising Edge of DRDY to Rising Edge of CS (Master and Slave Mode) 2 • tXIN t24 Falling Edge of CS to Rising Edge of SCLK (Slave Mode) 11 • tXIN t25 Falling Edge of Last SCLK for INSR to SDIO Tri-state (Master Mode) 4 • tXIN ns t26 SDIO as Output to Rising Edge of First SCLK for Register Data (Master and Slave Modes) 4 • tXIN ns t27 Falling Edge of Last SCLK for INSR to SDIO Tri-state (Slave Mode) ns ns 10 • tXIN ns ns 12 • tXIN ns ns ns 6 • tXIN 8 • tXIN ns t28 SDIO Tri-state Time (Master and Slave Modes) 2 • tXIN ns t29 Falling Edge of Last SCLK for Register Data to SDIO Tri-State (Master Mode) 2 • tXIN ns t30 Falling Edge of Last SCLK for Register Data to SDIO Tri-state (Slave Mode) 4 • tXIN 6 • tXIN ns ns t31 DRDY Fall Time 30 t32 DRDY Rise Time 30 t33 Minimum DSYNC LOW Time 21 • tXIN ns t34 DSYNC Valid HIGH to Falling Edge of XIN (for Exact Synchronization of Multiple Converters Only) 10 ns t35 Falling Edge of XIN to DSYNC Not Valid LOW (for Exact Synchronization of Multiple Converters Only) 10 ns t36 Falling Edge of Last SCLK for Register Data to Rising Edge of First SCLK of next INSR (Slave Mode, CS Tied LOW) 41 • tXIN ns t37 Rising Edge of CS to Falling Edge of CS (Slave Mode, Using CS) 22 • tXIN ns t38 Falling Edge of DRDY to First SCLK Rising Edge (Slave Mode, CS Tied LOW) 11 • tXIN ns ns TABLE XV. Digital Timing Characteristics. ADS1212, 1213 SBAS064A 23 t16 DRDY t18 t17 SCLK SDIO IN7 IN1 IN0 INM IN1 IN0 OUT1 OUT0 OUT1 OUT0 Write Register Data IN7 SDIO IN1 IN0 OUTM Read Register Data using SDIO IN7 SDIO IN1 IN0 SDOUT OUTM Read Register Data using SDOUT FIGURE 16. Serial Interface Timing (CS LOW), Master Mode. t38 DRDY t20 t19 SCLK t36 SDIO IN7 IN1 IN0 INM IN1 IN0 IN7 OUT1 OUT0 IN7 Write Register Data SDIO IN7 IN1 IN0 OUTM Read Register Data using SDIO SDIO IN7 IN1 IN0 IN7 SDOUT OUTM OUT1 OUT0 Read Register Data using SDOUT FIGURE 17. Serial Interface Timing (CS LOW), Slave Mode. DRDY t18 t21 CS t22 t17 t23 SCLK SDIO IN7 IN1 IN0 INM IN1 IN0 OUTM OUT1 OUT0 OUT1 OUT0 Write Register Data SDIO IN7 IN1 IN0 Read Register Data using SDIO SDIO IN7 IN1 IN0 OUTM SDOUT Read Register Data using SDOUT DRDY t16 t18 CS SCLK SDIO OUTM OUT1 OUT0 Continuous Read of Data Output Register using SDIO SDOUT OUTM OUT1 OUT0 Continuous Read of Data Output Register using SDOUT FIGURE 18. Serial Interface Timing (Using CS), Master Mode. 24 ADS1212, 1213 SBAS064A DRDY t20 t21 t37 CS t24 t19 t23 SCLK IN7 SDIO IN1 IN0 t24 INM IN1 IN0 IN7 OUTM OUT1 OUT0 IN7 Write Register Data IN7 SDIO IN1 IN0 Read Register Data Using SDIO IN7 SDIO IN1 IN0 IN7 OUTM SDOUT OUT1 OUT0 Read Register Data Using SDOUT DRDY t16 t20 CS SCLK OUTM SDIO OUT1 OUT0 Continuous Read of Data Output Register using SDIO OUTM SDOUT OUT1 OUT0 Continuous Read of Data Output Register using SDOUT FIGURE 19. Serial Interface Timing (Using CS), Slave Mode. t23 t16 DRDY t18 t21 CS(1) Master Mode t26 t25 t22 SCLK t17 IN7 SDIO IN6 IN5 IN2 IN1 t27 t24 SCLK t29 OUT M IN0 OUT0 t20 t26 Slave Mode t30 IN0 IN7 SDIO OUT MSB OUT0 t28 t38 t19 SDIO is an input SDIO is an output NOTE: (1) CS is optional. FIGURE 20. SDIO Input to Output Transition Timing. t31 t32 DRDY FIGURE 21. DRDY Rise and Fall Time. ADS1212, 1213 SBAS064A 25 Synchronizing Multiple Converters A negative going pulse on DSYNC can be used to synchronize multiple ADS1212/13s. This assumes that each ADS1212/13 is driven from the same master clock and is set to the same Decimation Ratio and Turbo Mode Rate. The affect that this signal has on data output timing in general is discussed in the Serial Interface section. The concern here is what happens if the DSYNC input is completely asynchronous to this master clock. If the DSYNC input rises at a critical point in relation to the master clock input, then some ADS1212/13s may start-up one XIN clock cycle before the others. Thus, the output data will be synchronized, but only to within one XIN clock cycle. For many applications, this will be more than adequate. In these cases, the timing symbols which relate the DSYNC signal to the XIN signal can be ignored. For other multipleconverter applications, this one XIN clock cycle difference could be a problem. These types of applications would include using the DRDY and/or the SCLK output from one ADS1212/13 as the “master” signal for all converters. To ensure exact synchronization to the same XIN edge, the timing relationship between the DSYNC and XIN signals, as shown in Figure 22, must be observed. Figure 23 shows a simple circuit which can be used to clock multiple ADS1212/13s from one ADS1212/13, as well as to ensure that an asynchronous DSYNC signal will exactly synchronize all the converters. SERIAL INTERFACE The ADS1212/13 includes a flexible serial interface which can be connected to microcontrollers and digital signal processors in a variety of ways. Along with this flexibility, there is also a good deal of complexity. This section describes the trade-offs between the different types of interfacing methods in a top-down approach—starting with the overall flow and control of serial data, moving to specific interface examples, and then providing information on various issues related to the serial interface. Multiple Instructions The general timing diagrams which appear throughout this data sheet show serial communication to and from the ADS1212/13 occurring during the DRDY LOW period (see Figures 4 through 10 and Figure 36). This communication represents one instruction that is executed by the ADS1212/ 13, resulting in a single read or write of register data. However, more than one instruction can be executed by the ADS1212/13 during any given conversion period (see Figure 24). Note that DRDY remains HIGH during the subsequent instructions. There are several important restrictions on how and when multiple instructions can be issued during any one conversion period. Internal Update of DOR 24 • tXIN DRDY t34 Serial I/O XIN t35 FIGURE 24. Timing of Data Output Register Update. t33 DSYNC FIGURE 22. DSYNC to XIN Timing for Synchronizing Mutliple ADS1212/13s. The first restriction is that the converter must be in the Slave Mode. There is no provision for multiple instructions when the ADS1212/13 is operating in the Master Mode. The second is that some instructions will produce invalid results if started at the end of one conversion period and carried into the start of the next conversion period. 1/2 74HC74 Asynchronous DSYNC Strobe D Q CLK Q 1/6 74HC04 C1 6pF DSYNC XTAL DGND C2 6pF SDOUT DSYNC SDOUT DSYNC SDOUT XIN SDIO XIN SDIO XIN SDIO XOUT SCLK XOUT SCLK XOUT SCLK DGND DVDD DGND DVDD DGND DVDD ADS1212/13 ADS1212/13 ADS1212/13 FIGURE 23. Exactly Synchronizing Multiple ADS1212/13s to an Asynchronous DSYNC Signal. 26 ADS1212, 1213 SBAS064A For example, Figure 24 shows that just prior to the DRDY signal going LOW, the internal Data Output Register (DOR) is updated. This update involves the Offset Calibration Register (OCR) and the Full-Scale Register (FSR). If the OCR or FSR are being written, their final value may not be correct, and the result placed into the DOR will certainly not be valid. Problems can also arise if certain bits of the Command Register are being changed. Note that reading the Data Output Register is an exception. If the DOR is being read when the internal update is initiated, the update is blocked. The old output data will remain in the DOR and the new data will be lost. The old data will remain valid until the read operation has completed. In general, multiple instructions may be issued, but the last one in any conversion period should be complete within 24 • XIN clock periods of the next DRDY LOW time. In this usage, “complete” refers to the point where DRDY rises in Figures 17 and 19 (in the Timing Section). Consult Figures 25 and 26 for the flow of serial data during any one conversion period. Start Reading ADS1212/13 drives DRDY LOW Start Writing ADS1212/13 drives DRDY LOW CS state HIGH LOW HIGH LOW LOW CS state CS state HIGH Continuous Read Mode? Yes No ADS1212/13 generates 8 serial clock cycles and receives Instruction Register data via SDIO ADS1212/13 generates n serial clock cycles and receives specified register data via SDIO ADS1212/13 drives DRDY HIGH End ADS1212/13 generates 8 serial clock cycles and receives Instruction Register data via SDIO Use SDIO for output? Yes No SDOUT becomes active from tri-state SDIO input to output transition ADS1212/13 generates n serial clock cycles and transmits specified register data via SDOUT ADS1212/13 generates n serial clock cycles and transmits specified register data via SDIO SDOUT returns to tri-state condition SDIO transitions to tri-state condition ADS1212/13 drives DRDY HIGH End FIGURE 25. Flowchart for Writing and Reading Register Data, Master Mode. ADS1212, 1213 SBAS064A 27 Start Reading ADS1212/13 drives DRDY LOW From Read Flowchart Start Writing To Write Flowchart ADS1212/13 drives DRDY LOW CS taken high for 22 t XIN periods minimum (see text if CS tied LOW). CS state HIGH LOW CS state CS state HIGH LOW HIGH Continuous Read Mode? CS taken high for 22 t XIN periods minimum (see text if CS tied low). Yes LOW CS state No External device generates 8 serial clock cycles and transmits instruction register data via SDIO External device generates 8 serial clock cycles and receives transmits instruction register data via SDIO External device generates n serial clock cycles and transmits specified register data via SDIO Use SDIO for output? HIGH LOW Yes No ADS1212/13 drives DRDY HIGH Yes More Instructions? See text for restrictions No End Is Next Instruction a Read? No SDOUT becomes active SDIO input to output transition External device generates n serial clock cycles and receives specified register data via SDOUT External device generates n serial clock cycles and receives specified register data via SDIO SDOUT returns to tri-state condition SDIO transitions to tri-state condition Yes To Read Flowchart ADS1212/13 drives DRDY HIGH More Instructions? No End Yes See text for restrictions Is Next Instruction a Write? No Yes To Write Flowchart FIGURE 26. Flowchart for Writing and Reading Register Data, Slave Mode. 28 ADS1212, 1213 SBAS064A Using CS and Continuous Read Mode The serial interface may make use of the CS signal, or this input may simply be tied LOW. There are several issues associated with choosing to do one or the other. The CS signal does not directly control the tri-state condition of the SDOUT or SDIO output. These signals are normally in the tri-state condition. They only become active when serial data is being transmitted from the ADS1212/13. If the ADS1212/13 is in the middle of a serial transfer and SDOUT or SDIO is an output, taking CS HIGH will not tri-state the output signal. If there are multiple serial peripherals utilizing the same serial I/O lines and communication may occur with any peripheral at any time, then the CS signal must be used. The ADS1212/13 may be in the Master Mode or the Slave Mode. In the Master Mode, the CS signal is used to hold-off serial communication with a “ready” (DRDY LOW) ADS1212/13 until the main controller can accommodate the communication. In the Slave Mode, the CS signal is used to enable communication with the ADS1212/13. The CS input has another use. If the CS state is left LOW after a read of the Data Output Register has been performed, then the next time that DRDY goes LOW, the ADS1212/13 Instruction Register will not be entered. Instead, the Instruction Register contents will be re-used, and the new contents of the Data Output Register, or some part thereof, will be transmitted. This will occur as long as CS is LOW and not toggled. This mode of operation is called the Continuous Read Mode and is shown in the read flowcharts of Figures 25 and 26. It is also shown in the Timing Diagrams of Figures 18 and 19 in the Timing section. Note that once CS has been taken HIGH, the Continuous Read Mode will be enabled (but not entered) and can never be disabled. The mode is actually entered and exited as described above. Power-On Conditions for SDIO Even if the SDIO connection will be used only for input, there is one important item to consider regarding SDIO. This only applies when the ADS1212/13 is in the Master Mode and CS will be tied LOW. At power-up, the serial I/O lines of most microcontrollers and digital signal processors will be in a tri-state condition, or they will be configured as inputs. When power is applied to the ADS1212/13, it will begin operating as defined by the default condition of the Command Register (see Table X in the System Configuration section). This condition defines SDIO as the data output pin. Since the ADS1212/13 is in the Master Mode and CS is tied LOW, the serial clock will run whenever DRDY is LOW and an instruction will be entered and executed. If the SDIO line is HIGH, as it might be with an active pull-up, then the instruction is a read operation and SDIO will become an output every DRDY LOW period—for 32 serial clock cycles. When the serial port on the main controller is enabled, signal contention could result. ADS1212, 1213 SBAS064A The recommended solution to this problem is to actively pull SDIO LOW. If SDIO is LOW when the ADS1212/13 enters the instruction byte, then the resulting instruction is a write of one byte of data to the Data Output Register, which results in no internal operation. If the SDIO signal cannot be actively pulled LOW, then another possibility is to time the initialization of the controller’s serial port such that it becomes active between adjacent DRDY LOW periods. The default configuration for the ADS1212/13 produces a data rate of 326Hz—a conversion period of 2.9ms. This time should be more than adequate for most microcontrollers and DSPs to monitor DRDY and initialize the serial port at the appropriate time. Master Mode The Master Mode is active when the MODE input is HIGH. All serial clock cycles will be produced by the ADS1212/13 in this mode, and the SCLK pin is configured as an output. The frequency of the serial clock will be one-quarter of the XIN frequency. Multiple instructions cannot be issued during a single conversion period in this mode—only one instruction per conversion cycle is possible. The Master Mode will be difficult for some microcontrollers, particularly when the XIN input frequency is greater than 2MHz, as the serial clock may exceed the microcontroller’s maximum serial clock frequency. For the majority of digital signal processors, this will be much less of a concern. In addition, if SDIO is being used as an input and an output, then the transition time from input to output may be a concern. This will be true for both microcontrollers and DSPs. See Figure 20 in the Timing section. Note that if CS is tied LOW, there are special considerations regarding SDIO as outlined previously in this section. Also note that if CS is being used to control the flow of data from the ADS1212/13 and it remains HIGH for one or more conversion periods, the ADS1212/13 will operate properly. However, the result in the Data Output Register will be lost when it is overwritten by each new result. Just prior to this update, DRDY will be forced HIGH and will return LOW after the update. Slave Mode Most systems will use the ADS1212/13 in the Slave Mode. This mode allows multiple instructions to be issued per conversion period as well as allowing the main controller to set the serial clock frequency and pace the serial data transfer. The ADS1212/13 is in the Slave Mode when the MODE input is LOW. There are several important items regarding the serial clock for this mode of operation. The maximum serial clock frequency cannot exceed the ADS1212/13 XIN frequency divided by 10 (see Figure 15 in the Timing section). 29 As with the Master Mode of operation, when using SDIO as edge of the last serial clock cycle of the instruction byte, the SDIO pin will begin its transition from input to output. Between six and eight XIN cycles after this falling edge, the SDIO pin will become an output. This transition may be too fast for some microcontrollers and digital signal processors. If a serial communication does not occur during any conversion period, the ADS1212/13 will continue to operate properly. However, the results in the Data Output Register will be lost when they are overwritten by the new result at the start of the next conversion period. Just prior to this update, DRDY will be forced HIGH and will return LOW after the update. Making Use of DSYNC The DSYNC input pin and the DSYNC write bit in the Command Register reset the current modulator count to zero. This causes the current conversion cycle to proceed as normal, but all modulator outputs from the last data output to the point where DSYNC is asserted are discarded. Note that the previous two data outputs are still present in the ADS1212/13 internal memory. Both will be used to compute the next conversion result, and the most recent one will be used to compute the result two conversions later. DSYNC does not reset the internal data to zero. There are two main uses of DSYNC. In the first case, DSYNC allows for synchronization of multiple converters. In regards to the DSYNC input pin, this case was discussed under “Synchronizing Multiple Converters” in the Timing section. In regards to the DSYNC bit, it will be difficult to set all of the converter’s DSYNC bits at the same time unless all of the converters are in the Slave Mode and the same instruction can be sent to all of the converters at the same time. The second use of DSYNC is to reset the modulator count to zero in order to obtain valid data as quickly as possible. For example, if the input channel is changed on the ADS1213, the current conversion cycle will be a mix of the old channel and the new channels. Thus, four conversions are needed in order to ensure valid data. However, if the channel is changed and then DSYNC is used to reset the modulator count, the modulator data at the end of the current conversion cycle will be entirely from the new channel. After two additional conversion cycles, the output data will be completely valid. Note that the conversion cycle in which DSYNC is used will be slightly longer than normal. Its length will depend on when DSYNC was set. Reset, Power-On Reset and Brown-Out The ADS1212/13 contains an internal power-on reset circuit. If the power supply ramp rate is greater than 50mV/ms, this circuit will be adequate to ensure the device powers up correctly. (Due to oscillator settling considerations, communication to and from the ADS1212/13 should not occur for at least 25ms after power is stable). If this requirement cannot be met or if the circuit has brown-out considerations, the timing diagram of Figure 27 can be used to reset the ADS1212/13. This timing applies only when the ADS1212/13 is in the Slave Mode and accomplishes the reset by controlling the duty cycle of the SCLK input. In general, reset is required after power-up, after a brown-out has been detected, or when a watchdog timer event has occured. If the ADS1212/13 is in the Master Mode, a reset of the device is not possible. If the power supply does not meet the minimum ramp rate requirement or brown-out is of concern, low on-resistance MOSFETs or equivalent should be used to control power to the ADS1212/13. When powered down, the device should be left unpowered for at least 300ms before power is reapplied. An alternate method would be to control the MODE pin and temporarily place the ADS1212/13 in the Slave Mode while a reset is initiated as shown in Figure 27. Two-Wire Interface For a two-wire interface, the Master Mode of operation may be preferable. In this mode, serial communication occurs only when data is ready, informing the main controller as to the status of the ADS1212/13. The disadvantages are that the ADS1212/13 must have a dedicated serial port on the main controller and only one instruction can be issued per data ready period. In the Slave Mode, the main controller must read and write to the ADS1212/13 “blindly.” Writes to the internal registers, such as the Command Register or Offset Calibration Register, might occur during an update of the Data Output Register. This can result in invalid data in the DOR. A twowire interface can be used if the main controller can read and/or write to the converter either much slower or much faster than the data rate. For example, if much faster, the main controller can use the DRDY bit to determine when data is becoming valid (polling it multiple times during one conversion cycle). Thus, the controller obtains some idea of when to write to the internal registers. If much slower, then reads of the DOR might always return valid data (mulitple conversions have occurred since the last read of the DOR or since any write of the internal registers). Reset occurs at 2048 • tXIN t2 t2 t2 t1 t3 t2: > 10 • tXIN t3: > 1024 • tXIN < 1800 • tXIN SCLK t3 t1: > 512 • tXIN < 800 • tXIN t4 t4: ≥ 2048 • tXIN < 2400 • tXIN FIGURE 27. Resetting the ADS1212/13 (Slave Mode only). 30 ADS1212, 1213 SBAS064A Three-Wire Interface Figure 28 shows a three-wire interface with a 8xC32 microprocessor. Note that the Slave Mode is selected and the SDIO pin is being used for input and output. Figure 29 shows a different type of three-wire interface with an 8xC51 microprocessor. Here, the Master Mode is used. The interface signals consist of SDOUT, SDIO, and SCLK. P1.0 8xC32 P1.1 P1.2 AVDD P1.3 P1.4 AINP REFIN AINN REFOUT AGND AGND DVDD CS P1.6 AVDD VBIAS P1.5 1.0µF AGND P1.7 MODE ADS1212 DSYNC RESET DGND DRDY RXD SDOUT TXD XIN SDIO INT0 XOUT SCLK DGND DVDD INT1 DVDD R1 10kΩ T0 T1 WR DGND C1 27pF RD X2 XTAL Q Q D CLK 1/2 74HC74 Q D Q VSS C2 27pF CLK X1 1/2 74HC74 FIGURE 28. Three-Wire Interface with a 8xC32 Microprocessor. P1.0 AVDD AINP REFIN AINN REFOUT AGND AGND DVDD C1 6pF(1) C2 6pF(1) 1.0µF AGND VCC P0.0 P1.2 P0.1 P1.3 P0.2 P1.4 P0.3 P1.5 P0.4 P1.6 P0.5 P1.7 P0.6 MODE ADS1212 DRDY DSYNC XTAL DGND AVDD VBIAS CS DVDD 8xC51 P1.1 SDOUT XIN SDIO XOUT SCLK DGND DVDD R1 10kΩ DGND NOTE: (1) Acceptable capacitive load not to exceed 6pF (±30%). FIGURE 29. Three-Wire Interface with a 8xC51 Microprocessor. ADS1212, 1213 SBAS064A 31 Four-Wire Interface Figure 30 shows a four-wire interface with a 8xC32 microprocessor. Again, the Slave Mode is being used. Note that the XIN input can also be controlled. It is possible with some microcontrollers and digital signal processors to produce a continuous serial clock, which could be connected to the XIN input. The frequency of the clock is often settable over some range. Thus, the power dissipation of the ADS1212/13 could be dynamically varied by changing both the Turbo Mode and XIN input, trading off conversion speed and resolution for power consumption. Multi-Wire Interface Figures 31 and 32 show multi-wire interfaces with a 8xC51 or 68HC11 microprocessor. In these interfaces, the mode of the ADS1212/13 is actually controlled dynamically. This could be extremely useful when the ADS1212/13 is to be used in a wide variety of ways. For example, it might be desirable to have the ADS1212/13 produce data at a steady rate and to have the converter operating in the Continuous Read Mode. But for system calibration, the Slave Mode might be preferred because multiple instructions can be issued per conversion period. I/O Recovery If serial communication stops during an instruction or data transfer for longer than 4 • tDATA, the ADS1212/13 will reset its serial interface. This will not affect the internal registers. The main controller must not continue the transfer after this event, but must restart the transfer from the beginning. Note that the MODE input should not be changed in the middle of a serial transfer. This could result in misoperation of the device. A Master/Slave Mode change will not affect the output data. This feature is very useful if the main controller can be reset at any point. After reset, simply wait 8 • tDATA before starting serial communication. P1.0 8xC32 P1.1 P1.2 AVDD P1.3 P1.4 AINP REFIN AINN REFOUT AGND DVDD CS P1.6 AVDD VBIAS AGND P1.5 1.0µF AGND P1.7 MODE RESET DGND ADS1212 DRDY DSYNC RXD SDOUT TXD XIN SDIO INT0 XOUT SCLK DGND DVDD INT1 DVDD R1 10kΩ WR C1 27pF RD X2 DGND X1 Q Q D CLK 1/2 74HC74 Q D Q C2 27pF CLK XTAL VSS 1/2 74HC74 FIGURE 30. Four-Wire Interface with a 8xC32 Microprocessor. AVDD AINP REFIN AINN REFOUT P1.2 P0.1 MODE P1.3 P0.2 ADS1212 DRDY P1.4 P0.3 SDOUT P1.5 P0.4 XIN SDIO P1.6 P0.5 XOUT SCLK P1.7 P0.6 DGND DVDD DGND AVDD VBIAS DSYNC XTAL C2 6pF VCC P0.0 CS C1 6pF 8xC51 P1.1 AGND AGND P1.0 1.0µF AGND DVDD R1 10kΩ R2 10kΩ DGND FIGURE 31. Full Interface with a 8xC51 Microprocessor. 32 ADS1212, 1213 SBAS064A PB7 XIRQ PB6 RESET PB5 PC7 PB4 PC6 AINP REFIN PB3 PC5 AINN REFOUT 68HC11 AVDD PC4 AGND PB1 PC3 VBIAS PB0 PC2 CS PE0 PC1 DSYNC PE1 PC0 PE2 XTAL PB2 AGND C1 6pF XTAL DGND 1.0µF AVDD AGND MODE R1 10kΩ ADS1212 DRDY SDOUT XIN SDIO XOUT SCLK DGND DVDD R2 10kΩ DVDD C2 6pF FIGURE 32. Full Interface with a 68HC11 Microprocessor. VDD2 DRDY AINP REFIN AINN REFOUT AGND R/T2B D2B R/T1B D1B VDD2 GND ADS1212 DRDY DGND DVDD D2B SCLK D1B XOUT DGND R/T2B SDIO VSB XIN SDIN R1 100Ω GA SDOUT R/T1B C2 6pF VDD1 ISO150 DGND GND DGND MODE DSYNC XTAL VDD1 D2A CS VDD2 R/T2A VDD1 C1 6pF SDOUT AGND D1A VBIAS VDD1 1.0µF R/T1A AGND AVDD GB AVDD VSA ISO150 VSB GA D2A R/T2A D1A R/T1A DGND GB VSA DGND VDD1 SCLK DGND GND VDD2 FIGURE 33. Isolated Four-Wire Interface. Isolation The serial interface of the ADS1212/13 provides for simple isolation methods. An example of an isolated four-wire interface is shown in Figure 33. The ISO150 is used to transmit the digital signals over the isolation barrier. ADS1212, 1213 SBAS064A In addition, the digital outputs of the ADS1212/13 can, in some cases, drive opto-isolators directly. Figures 34 and 35 show the voltage of the SDOUT pin versus source or sink current under worst-case conditions. Worst-case conditions for source current occur when the analog input differential 33 SOURCE CURRENT 30 AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P +5V 25 20 IOUT (mA) –40°C 25°C +5V 85°C AIN1P REFIN AIN1N REFOUT AGND 15 +5V 10 C1 6pF XTAL 0 DGND 0 1 2 3 4 5 MODE CS DRDY DSYNC 5 C2 6pF AVDD ADS1213U, P VBIAS R1 49.9kΩ AVDD +5V SDOUT XIN SDIO XOUT SCLK DGND DVDD REF1004 +2.5V 1.0µF +5V VOH VOH P1 2kΩ 0V +5V DGND VOH (V) FIGURE 34. Source Current vs VOH for SDOUT Under Worst-Case Conditions. SINK CURRENT 30 AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P +5V 25°C –40°C 25 85°C IOUT (mA) 20 0V AIN1P REFIN AIN1N REFOUT AGND 15 +5V 10 C1 6pF XTAL DGND 0 1 2 3 4 5 VOL (V) C2 6pF AVDD MODE CS DRDY SDOUT DSYNC 5 0 ADS1213U, P VBIAS XIN SDIO XOUT SCLK DGND DVDD R1 49.9kΩ 1.0µF REF1004 +2.5V AVDD +5V +5V VOL VOL P1 2kΩ 0V +5V DGND FIGURE 35. Sink Current vs VOL for SDOUT Under Worst-Case Conditions. voltage is 5V and the output format is Offset Binary (FFFFFFH). For sink current, the worst-case condition occurs when the analog input differential voltage is 0V and the output format is Two’s Complement (000000H). Note that SDOUT is tri-stated for the majority of the conversion period and the opto-isolator connection must take this into account. Note that an asynchronous DSYNC input may cause multiple converters to be different from one another by one XIN clock cycle. This should not be a concern for most applications. However, the Timing section contains information on exactly synchronizing multiple converters to the same XIN clock cycle. tDATA Synchronization of Multiple Converters The DSYNC input is used to synchronize the output data of multiple ADS1212/13s. Synchronization involves configuring each ADS1212/13 to the same Decimation Ratio and Turbo Mode setting, and providing a common signal to the XIN inputs. Then, the DSYNC signal is pulsed LOW (see Figure 22 in the Timing section). This results in an internal reset of the modulator count for the current conversion. Thus, all the converters start counting from zero at the same time, producing a DRDY LOW signal at approximately the same point (see Figure 36). DRDY A tDATA DRDY B tDATA DRDY C DSYNC tDATA FIGURE 36. Effect of Synchronization on Output Data Timing. 34 ADS1212, 1213 SBAS064A LAYOUT POWER SUPPLIES The ADS1212/13 requires the digital supply (DVDD) to be no greater than the analog supply (AVDD) +0.3V. In the majority of systems, this means that the analog supply must come up first, followed by the digital supply. Failure to observe this condition could cause permanent damage to the ADS1212/13. Inputs to the ADS1212/13, such as SDIO, AIN, or REFIN, should not be present before the analog and digital supplies are on. Violating this condition could cause latch-up. If these signals are present before the supplies are on, series resistors should be used to limit the input current (see the Analog Input and VBIAS sections of this data sheet for more details concerning these inputs). The best scheme is to power the analog section of the design and AVDD of the ADS1212/13 from one +5V supply and the digital section (and DVDD) from a separate +5V supply. The analog supply should come up first. This will ensure that AIN and REFIN do not exceed AVDD and that the digital inputs are present only after AVDD has been established, and that they do not exceed DVDD. The requirements for the digital supply are not as strict. However, high frequency noise on DVDD can capacitively couple into the analog portion of the ADS1212/13. This noise can originate from switching power supplies, very fast microprocessors or digital signal processors. For either supply, high frequency noise will generally be rejected by the digital filter except at interger multiplies of fMOD. Just below and above these frequencies, noise will alias back into the passband of the digital filter, affecting the conversion result. If one supply must be used to power the ADS1212/13, the AVDD supply should be used to power DVDD. This connection can be made via a 10Ω resistor which, along with the decoupling capacitors, will provide some filtering between DVDD and AVDD. In some systems, a direct connection can be made. Experimentation may be the best way to determine the approprate connection between AVDD and DVDD. GROUNDING The analog and digital sections of the design should be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. AGND should be connected to the analog ground plane as well as all other analog grounds. DGND should be connected to the digital ground plane and all digital signals referenced to this plane. For a single converter system, AGND and DGND of the ADS1212/13 should be connected together, underneath the converter. Do not join the ground planes, but connect the two with a moderate signal trace. For multiple converters, ADS1212, 1213 SBAS064A connect the two ground planes at one location as central to all of the converters as possible. In some cases, experimentation may be required to find the best point to connect the two planes together. The printed circuit board can be designed to provide different analog/digital ground connections via short jumpers. The initial prototype can be used to establish which connection works best. DECOUPLING Good decoupling practices should be used for the ADS1212/ 13 and for all components in the design. All decoupling capacitors, but specifically the 0.1µF ceramic capacitors, should be placed as close as possible to the pin being decoupled. A 1µF to 10µF capacitor, in series with a 0.1µF ceramic capacitor, should be used to decouple AVDD to AGND. At a minimum, a 0.1µF ceramic capacitor should be used to decouple DVDD to DGND, as well as for the digital supply on each digital component. SYSTEM CONSIDERATIONS The recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system. Achieving 20 bits or more of effective resolution is a great deal more difficult than achieving 12 bits. In general, a system can be broken up into four different stages: Analog Processing Analog Portion of the ADS1212/13 Digital Portion of the ADS1212/13 Digital Processing For the simplest system consisting of minimal analog signal processing (basic filtering and gain), a self-contained microcontroller, and one clock source, high-resolution could be achieved by powering all components by a common power supply. In addition, all components could share a common ground plane. Thus, there would be no distinctions between “analog” and “digital” power and ground. The layout should still include a power plane, a ground plane, and careful decoupling. In a more extreme case, the design could include: multiple ADS1212/13s; extensive analog signal processing; one or more microcontrollers, digital signal processors, or microprocessors; many different clock sources; and interconnections to various other systems. High resolution will be very difficult to achieve for this design. The approach would be to break the system into a many different parts as possible. For example, each ADS1212/13 may have its own analog processing front end, its own “analog” power and ground (possibly shared with the analog front end), and its own “digital” power and ground. The converter’s “digital” power and ground would be separate from the power and ground for the system’s processors, RAM, ROM, and “glue” logic. 35 APPLICATIONS The ADS1212/13 can be used in a broad range of data acquisition tasks. The following application diagrams show the ADS1212 and/or ADS1213 being used for bridge transducer measurements, temperature measurement, and 4-20mA receiver applications. 1/2 OPA1013 AVDD AGND 3kΩ AINP REFIN AINN REFOUT AGND AGND AGND DVDD C1 6pF MODE C2 6pF AGND ADS1212 DRDY DSYNC XTAL DGND VBIAS CS 1.0µF AVDD SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 37. Bridge Transducer Interface with Voltage Excitation. R1 6kΩ +In 10kΩ 3 5 1 RG INA118 6 8 –In 2 7 100µA 6 5 C1 6pF REF200 O 100µA I B C DGND 1 2 3 4 REFOUT CS AVDD AGND MODE ADS1212 DRDY DSYNC C2 6pF 1.0µF AVDD VBIAS DVDD XTAL A REFIN AINN AGND AGND 8 AINP DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND AGND FIGURE 38. Bridge Transducer Interface with Current Excitation. 36 ADS1212, 1213 SBAS064A REF200 100µA 100µA A B 3 +In 7 5 1 RG INA118 8 R2 100Ω R1 100Ω 4 2 –In 6 REFOUT AGND CS C1 6pF XTAL C2 6pF AVDD AGND MODE ADS1212 DRDY DSYNC AGND 1.0µF AVDD VBIAS DVDD DGND REFIN AINN AGND AGND R3 14kΩ AINP DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 39. PT100 Interface. +15V +In 15 3 4–20mA CT 2 14 RCV420 13 –In 5 1 AINP REFIN AINN REFOUT AGND AGND –15V DVDD C2 6pF AVDD AGND MODE ADS1212 DRDY DSYNC XTAL DGND VBIAS CS C1 6pF AVDD 1.0µF DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 40. Complete 4-20mA Receiver. +In 3 7 5 1 RG –In Termination R1 10kΩ 8 2 INA128 6 4 REFIN AINN REFOUT AGND AGND AGND DVDD C2 6pF +5V AGND MODE ADS1212 DRDY DSYNC XTAL 1.0µF AVDD VBIAS CS C1 6pF DGND AINP DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 41. Single Supply, High-Accuracy Thermocouple. ADS1212, 1213 SBAS064A 37 +In 3 7 5 1 RG –In 8 INA128 6 4 2 REFIN AINN REFOUT AGND AGND R1 10kΩ AINP AVDD VBIAS –5V DVDD CS C1 6pF AGND C2 6pF DGND +5V AGND MODE ADS1212 DRDY DSYNC XTAL 1.0µF DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 42. Dual Supply, High-Accuracy Thermocouple. +In 3 7 RG –In R1 10kΩ INA118 8 2 AGND 5 1 6 4 AGND AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P AIN1P REFIN AIN1N REFOUT AGND AGND 1N4148 AGND VBIAS R2 13kΩ DVDD CS 1.0µF AVDD +5V AGND MODE DRDY DGND C1 6pF DSYNC XTAL DGND ADS1213U, P AGND C2 6pF SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 43. Single Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation. 38 ADS1212, 1213 SBAS064A 3 +In 7 5 1 RG R1 10kΩ INA118 6 8 4 2 –In AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P AIN1P REFIN AIN1N REFOUT AGND –5V AGND AGND AGND 1N4148 AGND DVDD AGND MODE CS DRDY DGND C1 6pF DSYNC XTAL DGND +5V AVDD ADS1213U, P VBIAS R2 13kΩ 1.0µF C2 6pF SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 44. Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation. R1 6kΩ –In +In 10kΩ AINP REFIN AINN REFOUT AGND AVDD 8 6 7 100µA AGND DVDD 5 C1 6pF REF200 O 100µA I B C DGND 1 2 3 4 C2 6pF AVDD AGND MODE ADS1212 DRDY DSYNC XTAL A AVDD VBIAS CS 1.0µF SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND AGND FIGURE 45. Low-Cost Bridge Transducer Interface with Current Excitation. ADS1212, 1213 SBAS064A 39 TOPIC INDEX TOPIC PAGE FEATURES ..................................................................................... APPLICATIONS ............................................................................. DESCRIPTION ............................................................................... SPECIFICATIONS .......................................................................... TOPIC PAGE 1 ANALOG OPERATION ................................................................. 17 1 ANALOG INPUT ....................................................................................... 17 1 REFERENCE INPUT ................................................................................ 17 2 REFERENCE OUTPUT ............................................................................ 17 ABSOLUTE MAXIMUM RATINGS ............................................................. 3 VBIAS ..................................................................................................................................................... 18 ELECTROSTATIC DISCHARGE SENSITIVITY ........................................ 3 DIGITAL OPERATION .................................................................. 18 PACKAGE INFORMATION ........................................................................ 3 SYSTEM CONFIGURATION .................................................................... 18 ORDERING INFORMATION ...................................................................... 3 Instruction Register (INSR) ................................................................... 19 ADS1212 SIMPLIFIED BLOCK DIAGRAM ................................................ 4 Command Register (CMR) .................................................................... 19 ADS1212 PIN CONFIGURATION .............................................................. 4 Data Output Register (DOR) ................................................................. 21 ADS1212 PIN DEFINITIONS ..................................................................... 4 Offset Calibration Register (OCR) ........................................................ 22 ADS1213 SIMPLIFIED BLOCK DIAGRAM ................................................ 5 Full-Scale Calibration Register (FCR) ................................................... 22 ADS1213P and ADS1213U PIN CONFIGURATION ................................. 5 TIMING ..................................................................................................... 22 ADS1213P and ADS1213U PIN DEFINITIONS ........................................ 5 Synchronizing Multiple Converters ........................................................ 26 ADS1213E PIN CONFIGURATION ........................................................... 6 SERIAL INTERFACE ............................................................................... 26 ADS1213E PIN DEFINITIONS ................................................................... 6 Multiple Instructions ............................................................................... 26 TYPICAL PERFORMANCE CURVES ........................................... 7 THEORY OF OPERATION ............................................................ 9 Using CS and Continuous Read Mode ................................................ 29 DEFINITION OF TERMS ......................................................................... 10 Master Mode .......................................................................................... 29 DIGITAL FILTER ...................................................................................... 11 Slave Mode ............................................................................................ 29 Filter Equation ....................................................................................... 12 Making Use of DSYNC ......................................................................... 30 Filter Settling .......................................................................................... 12 Reset, Power-On Reset, and Brown-Out ............................................. 30 TURBO MODE ......................................................................................... 12 Two-Wire Interface ................................................................................ 30 PROGRAMMABLE GAIN AMPLIFIER ..................................................... 13 Three-Wire Interface .............................................................................. 30 SOFTWARE GAIN ................................................................................... 13 Four-Wire Interface ................................................................................ 30 CALIBRATION .......................................................................................... 13 Multi-Wire Interface ............................................................................... 32 Self-Calibration ...................................................................................... 14 I/O Recovery .......................................................................................... 32 System Offset Calibration ..................................................................... 14 Isolation ................................................................................................. 33 Power-On Conditions for SDIO ............................................................. 29 System Full-Scale Calibration ............................................................... 14 Synchronization of Multiple Converters ................................................ 34 Pseudo System Calibration ................................................................... 15 LAYOUT ........................................................................................ 35 Background Calibration ......................................................................... 15 POWER SUPPLIES ................................................................................. 35 System Calibration Offset and Full-Scale Calibration Limits ................ 16 GROUNDING ............................................................................................ 35 SLEEP MODE .......................................................................................... 16 DECOUPLING .......................................................................................... 35 SYSTEM CONSIDERATIONS ................................................................. 35 APPLICATIONS ............................................................................ 36 40 ADS1212, 1213 SBAS064A FIGURE INDEX TABLE INDEX FIGURE TITLE TABLE TITLE Figure 1 Normalized Digital Filter Response ......................................... 11 Table I Full-Scale Range vs PGA Setting ............................................. 9 Figure 2 Digital Filter Response at a Data Rate of 50Hz ..................... 11 Table II Available PGA Settings vs Turbo Mode Rate .......................... 9 Figure 3 Digital Filter Response at a Data Rate of 60Hz ..................... 11 Table III Effective Resolution vs Data Rate and Gain Setting ............. 10 Figure 4 Asynchronous ADS1212/13 Analog Input Voltage Step or ADS1213 Channel Change to Fully Settled Output Data .. 12 Self-Calibration Timing ............................................................ 14 Table IV Effective Resolution vs Data Rate and Turbo Mode Rate ..... 12 Figure 5 PAGE PAGE Table V Noise Level vs Data Rate and Turbo Mode Rate .................. 12 Table VI Effective Resolution vs Data Rate, Clock Frequency, and Turbo Mode Rate .................................................................... 12 Figure 6 System Offset Calibration Timing ........................................... 14 Figure 7 System Full-Scale Calibration ................................................. 14 Table VII ADS1212/13 Registers ............................................................ 18 Figure 8 Pseudo System Calibration Timing ......................................... 15 Table VIII Instruction Register .................................................................. 19 Figure 9 Background Calibration ........................................................... 15 Table IX A3-A0 Addressing .................................................................... 19 Figure 10 Sleep Mode to Normal Mode Timing ...................................... 17 Table X Organization of the Command Register and Default Status .. 19 Figure 11 Analog Input Structure ............................................................. 17 Table XI Decimation Ratios vs Data Rates ........................................... 21 Figure 12 ±10V Input Configuration Using VBIAS .................................................... 18 Table XII Data Output Register ............................................................... 21 Figure 13 XIN Clock Timing ...................................................................... 22 Table XIII Offset Calibration Register ...................................................... 22 Figure 14 Serial Input/Output Timing, Master Mode ............................... 22 Table XIV Full-Scale Calibration Register ................................................ 22 Figure 15 Serial Input/Output Timing, Slave Mode ................................. 22 Table XV Digital Timing Characteristics .................................................. 23 Figure 16 Serial Interface Timing (CS LOW), Master Mode ................... 24 Figure 17 Serial Interface Timing (CS LOW), Slave Mode ..................... 24 Figure 18 Serial Interface Timing (Using CS), Master Mode .................. 24 Figure 19 Serial Interface Timing (Using CS), Slave Mode .................... 25 Figure 20 SDIO Input to Output Transition Timing ................................. 25 Figure 21 DRDY Rise and Fall Time ....................................................... 25 Figure 22 DSYNC to XIN Timing for Synchronizing Multiple ADS1212/13s ........................................................................... 26 Figure 23 Exactly Synchronizing Multiple ADS1212/13s to Asynchronous DSYNC Signal ............................................. 26 Figure 24 Timing of Data Output Register Update ................................. 26 Figure 25 Flowchart for Writing and Reading Register Data, Master Mode 27 Figure 26 Flowchart for Writing and Reading Register Data, Slave Mode .. 28 Figure 27 Resetting the ADS1212/13 (Slave Mode Only) ...................... 30 Figure 28 Three-Wire Interface with an 8xC32 Microprocessor ............. 31 Figure 29 Three-Wire Interface with an 8xC51 Microprocessor ............. 31 Figure 30 Four-Wire Interface with an 8xC32 Microprocessor ............... 32 Figure 31 Full Interface with an 8xC51 Microprocessor ......................... 32 Figure 32 Full Interface with a 68HC11 Microprocessor ........................ 33 Figure 33 Isolated Four-Wire Interface .................................................... 33 Figure 34 Source Current vs VOH for SDOUT Under Worst-Case Conditions ............................................................ 34 Figure 35 Sink Current vs VOL for SDOUT Under Worst-Case Conditions ............................................................ 34 Figure 36 Effect of Synchronization on Output Data Timing .................. 34 Figure 37 Bridge Transducer Interface with Voltage Excitation .............. 36 Figure 38 Bridge Transducer Interface with Current Excitation .............. 36 Figure 39 PT100 Interface ....................................................................... 37 Figure 40 Complete 4-20mA Receiver .................................................... 37 Figure 41 Single Supply, High-Accuracy Thermocouple ......................... 37 Figure 42 Dual Supply, High-Accuracy Thermocouple ........................... 38 Figure 43 Single Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation ........................................... 38 Figure 44 Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation ........................................... 39 Figure 45 Low-Cost Bridge Transducer Interface with Current Excitation ..... 39 ADS1212, 1213 SBAS064A 41 PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS1212P ACTIVE PDIP N 18 20 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS1212PG4 ACTIVE PDIP N 18 20 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS1212U ACTIVE SOP DTC 18 43 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1212U/1K ACTIVE SOP DTC 18 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1212U/1KG4 ACTIVE SOP DTC 18 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1212UG4 ACTIVE SOP DTC 18 43 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1213E ACTIVE SSOP DB 28 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1213E/1K ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1213E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS1213EG4 ACTIVE SSOP DB 28 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1213P ACTIVE PDIP NTG 24 15 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS1213PG4 ACTIVE PDIP NTG 24 15 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS1213U ACTIVE SOIC DW 24 33 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1213U/1K ACTIVE SOIC DW 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1213U/1KG4 ACTIVE SOIC DW 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1213UG4 ACTIVE SOIC DW 24 CU NIPDAU Level-2-260C-1 YEAR 33 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDS095 – APRIL 2001 DTC (R-PDSO-G18) –A– PLASTIC SMALL-OUTLINE 0.4625 (11,75) C 0°–8° 0.4469 (11,35) 10 18 0.050 (1,27) 0.016 (0,40) D –B– 0.2992 (7,60) 0.2914 (7,40) 0.419 (10,65) 0.394 (10,00) 0.010 (0,25) M B M Index Area 1 9 E E 0.0118 (0,30) 0.004 (0,10) 0.050 (1,27) 0.029 (0,75) 0.010 (0,25) x 45° 0.1043 (2,65) 0.0926 (2,35) Base Plane Seating Plane –C– 0.0125 (0,32) 0.020 (0,51) 0.013 (0,33) 0.010 (0,25) 0.0091 (0,23) 0.004 (0,10) M C A M BS 4202498/A 03/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body length dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.006 (0,15) per side. D. Body width dimension does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010 (0,25) per side. E. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the cross-hatched area. F. Falls within JEDEC MS-013-AB. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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