BB DAC729JH

DAC729
DAC
729
Ultra-High Resolution
18-BIT DIGITAL-TO-ANALOG CONVERTER
FEATURES
● 16-BIT LINEARITY GUARANTEED
(K Grade)
● USER ADJUSTABLE TO 18-BIT
LINEARITY
● PRECISION INTERNAL REFERENCE
● FAST SETTLING, LOW NOISE INTERNAL
OP AMP
● LOW DRIFT
● HERMETIC 40-PIN CERAMIC PACKAGE
● IOUT OR VOUT OPERATION
1
40
2
39
3
38
4
37
5
36
6
35
Precision
10V
Reference
7
DESCRIPTION
The DAC729 sets the standard in very high accuracy
digital-to-analog conversion. It is supplied from the
factory at a guaranteed linearity of 16 bits, and is useradjustable to 18-bit linearity (1LSB = FSR/262144).
To attain this high level of accuracy, the design takes
advantage of Burr-Brown’s thin-film monolithic DAC
process, dielectric op amp process, hybrid capabilities,
and advanced test and laser-trim techniques.
The DAC729 hybrid layout is specifically partitioned
to minimize the effects of external load-currentinduced thermal errors. The op amp design consists of
a fast settling precision op amp with a current buffer
within the feedback loop. This buffer isolates the load
from the precision op amp, which results in a fast
settling (8µs to 16 bits) output. The standard 40-pin
package offers full hermeticity, contributing to the
excellent reliability of the DAC729.
34
8
18-Bit
IOUT
33
9
DAC
32
10
Servo-Loop
Amplifier
31
11
30
12
29
5kΩ
13
28
5kΩ
14
27
5kΩ
15
5kΩ
26
16
25
17
24
18
23
19
22
20
21
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1988 Burr-Brown Corporation
PDS-749C
Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VCC = ±15V, VDD = +5V, using internal reference op amp, unless otherwise noted. COB = ±10V FSR, CSB = 0V to +10V FSR.
DAC729JH
PARAMETER
MIN
DIGITAL INPUT
Resolution
Digital Inputs(1): VIH
VIL
I IH, VIN = +2.7V
I IL, VIN = +0.4V
+2.4
0
DAC729KH
TYP
MAX
MIN
+VL
+0.8
+5
–300
*
*
18
TYP
MAX
UNITS
*
*
*
*
Bits
V
V
µA
µA
*
TRANSFER CHARACTERISTICS(2)
ACCURACY
Linearity Error(3)
Differential Linearity Error
Gain Error(5)
Offset Error:(5)Voltage, COB(6)
CSB(6)
Current, COB
CSB
Power Supply Sensitivity, Unipolar: ±15VDC
+5VDC
Bipolar Offset: ±15VDC
+5VDC
Bipolar Gain: ±15VDC
+5VDC
Output Noise (10Hz to 100kHz), Voltage: Bipolar Offset
Bipolar Gain
Current: Bipolar Offset
Bipolar Gain
Monotonicity (0°C to +70°C)
Differential Linearity Adjustment Resolution(7)
±0.05
±5
±3
15
DRIFT (Over Specification Temperature Range)
Gain Drift (Excluding Reference Drift)
Offset Drift (Excluding Reference Drift): COB (Bipolar)
CSB (Unipolar)
Linearity Error (at 0°C and +70°C)
Differential Linearity Error (at 0°C and +70°C)
±0.0001
±0.0001
±0.0004
±0.0001
±0.0005
±0.0001
29
37
2.9
3
16
18
±0.0015
±0.003
±0.10
±10
±5
±5
±1
±0.0005
±0.0005
±0.0015
±0.0005
±0.0015
±0.0005
±3
±2
±2
±0.3
±0.5
STABILITY, LONG TERM (at +25°C)
Gain (Exclusive of Reference)
Offset: COB (Exclusive of Reference)
CSB
Linearity
Reference
*
*
*
16
±5
±5
±3
±1
±2
*
*
*
*
*
*
*
*
*
*
17
*
*
*
*
±0.3
±0.5
±0.00076
±0.0015
*
*
*
*
*
*
*
*
*
*
*
% of FSR(4)
% of FSR
%
mV
mV
µA
µA
% of FSR/%VS
% of FSR/%VS
% of FSR/%VS
% of FSR/%VS
% of FSR/%VS
% of FSR/%VS
µVrms
µVrms
nArms
nArms
Bits
Bits
*
*
*
±0.5
±1
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
±5
±5
±5
±2
±5
±5
±5
±5
±2
±5
ppm/1000hr
ppm of FSR/1000hr
ppm of FSR/1000hr
ppm of FSR/1000hr
ppm/1000hr
±2.5, ±5, ±10
0 to +10, 0 to +5
*
*
V
V
mA
Ω
OUTPUT
VOLTAGE OUTPUT MODE
Ranges: COB
CSB
Output Current
Output Impedance
Short Circuit Duration
CURRENT OUTPUT MODE
COB Ranges
Output Impedance
CSB Ranges
Output Impedance
Output Current Tolerance
Compliance Voltage
SETTLING TIME (To ±0.00076% of FSR)(8)
Voltage (Load = 2kΩ || 100pF): Full-Scale Step
1LSB Step (Major Carry) (9)
Slew Rate
Switching Transient Peak
Switching Transient Energy
Current Full-Scale Step (2mA X 10Ω || 1pF)
DAC729
±5
*
0.15
Indefinite to Common
*
Indefinite to Common
±1
2.86
0 to –2
4.0
*
*
*
*
±0.1
–1 to +5
5
4
20
500
0.45
300
2
*
*
8
7
*
*
*
*
*
*
*
*
mA
kΩ
mA
kΩ
% of FSR
V
µs
µs
V/µs
mV
V-µs
ns
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = +25°C, VCC = ±15V, VDD = +5V, using internal reference op amp, unless otherwise noted. COB = ±10V FSR, CSB = 0V to +10V FSR.
DAC729JH
PARAMETER
DAC729KH
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
+9.990
+10.000
+10.010
*
*
*
V
*
*
mA
ppm/°C
REFERENCE
Output (pin 32) :Voltage
Source Current(10)
Temperature Coefficient
Short-Circuit Duration
Power Supply Sensitivity
+4
±2
±4
Indefinite to Common
0.00025
0.003
*
Indefinite to Common
*
*
%/V
POWER SUPPLY REQUIREMENTS
Voltage: +VCC
–VCC
VDD
Current: +VCC
–VCC
VDD
Power Dissipation (Rated Supplies)
+13.5
–16.5
+4.75
+15
–15
+5
+30
–45
+18
1.22
+16.5
–13.5
+5.25
+40
–60
+25
1.63
*
*
*
+70
+150
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
V
V
V
mA
mA
mA
W
*
*
°C
°C
ENVIRONMENTAL SPECIFICATIONS
Temperature Range: Specification
Storage
0
–60
* Specifications same as DAC729JH.
NOTES: (1) TTL- and CMOS-compatible. (2) Specified for VOUT mode using the internal op amp. (3) ±0.00076% of full-scale range is 1/2LSB for 16-bit resolution. (4)
FSR means full-scale range, 20V for ±10V range, etc. (5) Adjustable to zero error with an external potentiometer. (6) COB is complementary offset binary (bipolar); CSB
is complementary straight binary (unipolar). (7) Using the MSB adjustment circuit, the user may improve the DAC linearity to 1/2LSB of this specification with gain and
offset errors adjusted to zero at 25°C. (8) Maximum represents 3σ limit, not 100% production tested. (9) At the major carry; 20000 to 1FFFFHEX and from 1FFFF to
20000HEX. (10) Maximum with no degradation in specifications. External loads must be constant.
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS(1)
PRODUCT
VDD to Common ........................................................................ 0V to +7V
+VCC to Common .................................................................... 0V to +18V
–VCC to Common .................................................................... 0V to –18V
Digital Data Inputs (pins 1-18) to Common ............................ –0.5V to VDD
Reference Voltage In (pin 31) ................................................ +9V to +11V
Reference Out (pin 32) to Common ............... Indefinite Short to Common
External Voltage Applied to D/A Output (pin 29) ..................... –5V to +5V
External Voltage Applied to Feedback Resistors
(pins 25, 26, 27, 28) .......................................................... –15V to +15V
VOUT (pin 23) ................................................... Indefinite Short to Common
Power Dissipation ........................................................................ 3000mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
DAC729JH
DAC729KH
DAC729KH-BI
PACKAGE
TEMPERATURE RANGE
40-Pin Hermetic DIP
40-Pin Hermetic DIP
40-Pin Hermetic DIP
0°C to +70°C
0°C to +70°C
0°C to +70°C
PACKAGE INFORMATION
PRODUCT
DAC729JH
DAC729KH
DAC729KH-BI
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE
PACKAGE DRAWING
NUMBER(1)
40-Pin Hermetic DIP
40-Pin Hermetic DIP
40-Pin Hermetic DIP
214
214
214
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
3
DAC729
PIN CONNECTIONS
Top View
DIP
(MSB) Bit 1
1
40 VPOT
Bit 2
2
39 Bit 1 Adjust
Bit 3
3
38 Bit 2 Adjust
Bit 4
4
37 Bit 3 Adjust
Bit 5
5
36 Bit 4 Adjust
Bit 6
6
35 Reference Adjust
Bit 7
7
34 Gain Adjust
Bit 8
8
33 Reference Common
Bit 9
9
32 Reference Out
Bit 10 10
31 Reference In
Bit 11 11
30 Analog Common
Bit 12 12
29 IOUT
Bit 13 13
28 5kΩ Feedback
Bit 14 14
27 5kΩ Feedback
Bit 15 15
26 10kΩ Feedback
Bit 16 16
25 10kΩ Feedback
Bit 17 17
24 Summing Junction
(LSB) Bit 18 18
23 VOUT
VDD (5V) 19
22 +VCC (15V)
Digital Common 20
21 –VCC (15V)
DAC729
4
ELECTROSTATIC
DISCHARGE SENSITIVITY
gain is well over 500,000V/V. Since thermal feedback is the
major limitation of gain for mono op amps, the amplifier
was designed as a high gain, fast settling mono op amp,
followed by a monolithic, unity-gain current buffer to isolate
the thermal effects of external loads from the input stage
gain transistors. The op amp and buffer are separated from
the DAC chip, minimizing thermally-induced linearity errors in the DAC circuit. The op amp, like the reference, is
not dedicated to the DAC729. The user may want to add a
network, or select a different amplifier. The DAC729 internal op amp is intended to be the best choice for accuracy,
settling time, and noise.
Any integral circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
THE DAC CHIP
BURN-IN SCREENING
The heart of the DAC729 is a monolithic current source and
switch integrated circuit. The absolute linearity, differential
linearity, and the temperature performance of the DAC729
are the result of the design, which utilizes the excellent
element matching of the current sources and switch transistors to each other, and the tracking of the current setting
resistors to the feed back resistors. Older discrete designs
cannot achieve the performance of this monolithic DAC
design.
Burn-in screening is an option available for the DAC729
family of products. Burn-in duration is 160 hours at 100°C
(or equivalent combination of time and temperature).
All units are tested after burn-in to ensure that grade specifications are met.
THEORY OF OPERATION
The two most significant bits are binarily weighted interdigitated current sources. The currents for bits 3 through 18
are scaled with both current source weighting and an R-2R
ladder. The circuit design is optimized for low noise and low
superposition error, with the current sources arranged to
minimize both code-dependent thermal errors and IR drop
errors. As a result, the superposition errors are typically less
than 20µV.
The DAC729 is an 18-bit digital-to-analog converter system, including a precision reference, low noise, fast settling
operational amplifier, and an 18-bit current source/DAC
chip contained in a hermetic 40-pin ceramic dual-in-line
package. Refer to Figure 11 for a schematic diagram of the
DAC729.
THE INTERNAL REFERENCE
The DAC chip is biased from a servo amplifier feeding into
the base line of the current sources. This servo amplifier sets
the collector current to be mirrored and scaled in the DAC
chip current sources, as shown in Figure 11. The reference
current for the servo is established by the reference voltage
applied to pin 31 feeding an internal resistor (20kΩ) to the
virtual ground of the servo amplifier.
The reference consists of a very low temperature coefficient
closed-loop reference zener circuit that has been temperature-drift-compensated by laser-trimming a zener current to
achieve less than 1ppm/°C temperature drift of VREF.
By strapping pin 32 (Reference Out) to pin 31 (Reference
In), the DAC will be properly biased from the internal
reference. The internal reference may be fine adjusted using
pin 35 as shown in Figure 7. The reference has an output
buffer that will supply 4mA for use external to the DAC729.
This load must remain constant because changing load on
the reference may change the reference current to the DAC.
DISCUSSION
OF SPECIFICATIONS
DIGITAL INPUT CODES
In systems where several components need to track the same
system reference, the DAC729 may be used with an external
10V reference, however, the internal reference has lower
noise (6µVp-p) and better stability than other references
available.
The DAC729 accepts complementary digital input codes in
either binary format (CSB for Unipolar or COB for Bipolar;
see Table I).
DAC ANALOG OUTPUT
DIGITAL INPUT
THE OPERATIONAL AMPLIFIER
To support a DAC of this accuracy, the operational amplifier
must have a maximum gain-induced error of less than
1/3LSB, independent of output swing (the op amp must be
linear!) To support 15 bits (1/2-bit linearity), the op amp
must have a gain of 130,000V/V. For 18 bits, the minimum
COB
20V FSR
CSB
10V FSR
00 0000 0000 0000 0000 + Full Scale 9.999924V + Full Scale 9.999962V
11 1111 1111 1111 1111 – Full Scale
–10V
– Full Scale
0V
TABLE I. Digital Input Coding.
5
DAC729
ACCURACY
COMPLIANCE VOLTAGE
Linearity
This specification describes one of the most important measures of performance of a D/A converter. Linearity error is
the deviation of the analog output versus code transfer
function from a straight line drawn through the end points
(all bits ON point and all bits OFF point).
Compliance voltage applies only to the current output mode
of operation. It is the maximum voltage swing allowed on
the output current pin while still being able to maintain
specified linearity.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
change in a power supply voltage on the D/A converter fullscale output. It is defined as a percent of FSR change in the
output per percent of change in either the positive supply
(+VCC), negative supply (–VCC), or logic supply (VDD) about
the nominal power supply voltages (see Figure 1). It is
specified for DC or low frequency changes. The typical
performance curve in Figure 1 shows the effect of high
frequency changes in power supply voltages using internal
reference, DAC, and op amp.
Differential Linearity Error
Differential Linearity Error (DLE) of a D/A converter is the
deviation from an ideal 1LSB change in the output from one
adjacent output state to the next. A differential linearity error
specification of ±1/2LSB means that the output step sizes
can be between 1/2 LSB and 3/2LSB when the input changes
from one adjacent input state to the next. A negative DLE
specification of no more than –1LSB (–0.0015% for 16-bit
resolution) insures monotonicity to 16 bits.
Monotonicity
Monotonicity assures that the analog output will increase or
remain the same for increasing input digital codes. The
DAC729KH is specified to be monotonic to 16 bits over the
entire specification temperature range.
DRIFT
Gain Drift
Gain drift is a measure of the change in the full-scale range
output over temperature expressed in parts per million per
degree centigrade (ppm/°C). Gain drift is measured by: (1)
testing the end point differences for each D/A at tMIN, +25°C,
and tMAX; (2) calculating the gain error with respect to the
+25°C value; and (3) dividing by the temperature change.
Offset Drift
Offset drift is a measure of the change in the output with
3FFFFH applied to the digital inputs over the specified
temperature range. The maximum change in offset at tMIN or
tMAX is referenced to the offset error at +25°C and is divided
by the temperature change. This drift is expressed in parts
per million of full-scale range per degree centigrade (ppm of
FSR/°C).
FIGURE 1. Power Supply Sensitivity vs Frequency Using
Internal Reference and Op Amp.
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown in Figure 2.
These capacitors (1µF to 10µF tantalum recommended)
should be located at the DAC729.
SETTLING TIME
Settling time of the D/A is the total time required for the
analog output to settle within an error band around its final
value after a change in digital input. Settling time includes
the slew time of the op amp.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external offset
and gain potentiometers. Connect these potentiometers as
shown in Figure 3 and adjust as described below. TCR of
the potentiometers should be 100ppm/°C or less. The 3.9MΩ
and 510kΩ resistors (20% carbon or better) should be
located close to the DAC729 to prevent noise pickup. If it
is not convenient to use these high-value resistors, an
equivalent “T” network, as shown in Figure 4, may be
substituted in place of the 3.9MΩ. A 0.001µF to 0.01µF
capacitor should be connected from Gain Adjust (pin 34) to
Voltage Output
Settling times are specified to ±0.00076% of FSR scale
range change of 20V (COB) or 10V (CSB) and a 1LSB
change at the “major carry,” the point at which the worstcase settling time occurs. (This is the worst-case point since
all of the input bits change when going from one code to the
next.)
Current Output
Settling times are specified to ±0.00076% of FSR for a fullscale range change with an output load resistance of 10Ω.
DAC729
6
GAIN ADJUSTMENT
common to shunt noise pickup. This capacitor should be a
low leakage film type (such as Mylar™ or Teflon™).
For either unipolar or bipolar configurations, apply the
digital input that should give the maximum positive output
voltage. Adjust the gain potentiometer for this positive fullscale voltage. See Table II for positive full-scale voltages
and Figure 3 for gain adjustment connections.
Refer to Figures 5 and 6 for relationship of offset and gain
adjustments to unipolar and bipolar D/A converters.
OFFSET ADJUSTMENT
For unipolar (CSB) configurations, apply the digital input
code that should produce zero potential output and adjust the
offset potentiometer for zero output.
GAIN ADJUST
OUTPUT
CONNECT CONNECT CONNECT
RANGE CODE PIN 23
PIN 31
PIN 24
16-BITS
18-BITS
For bipolar (COB) configurations, apply the digital input
code that should produce the maximum negative output
voltage. See Table II for corresponding codes and Figures 2
and 3 for offset adjustment connections. Offset adjust should
be made prior to gain adjust.
to Pin 26
to Pin 26
to Pin 26
0 to 10V
CSB
0 to 5V
CSB
to Pins
25 & 26
to Pins
27 & 28
9.9969V
4.9998V
2.4992V
9.99992V
9.99996V
2.49998V
N/C
to Pin 29
to Pin 29
to Pins
29 & 25
to Pin 29
9.9998V
9.99996V
N/C
to Pin 29
4.9999V
4.99998V
40
1
40
2
39
2
39
3
38
3
38
4
37
4
37
5
36
5
36
6
35
6
35
7
34
7
34
9
33
18-Bit
DAC
Reference Common
32
8
33
9
32
10
31
11
30
11
30
12
29
12
29
13
28
13
28
27
14
27
15
26
15
26
16
25
16
25
17
24
17
24
18
23
18
23
19
22
20
21
19
20
10kΩ
31
10kΩ
10
14
1µF
to Pin 25
to Pin 27
to Pin 27
1
8
+
COB
COB
COB
TABLE II. Output Range Connections and Gain Adjust
Voltage.
Mylar™, Teflon™ E.I. du Pont de Nemours & Co.
+5V VLOGIC
±10V
±5V
±2.5V
Analog
Common
+5V
+15V
22
–15V
21
+
1µF
Digital Common
Gain Adjust
+VCC
270kΩ
10kΩ to
100kΩ
(1)
0.0022µF
–VCC
+VCC
3.9M
10kΩ to
100kΩ
–VCC
Offset Adjust
+VCC = 15V
–VCC = 15V
1µF
+
NOTE: (1) Mylar™ or Teflon™ Film.
FIGURE 2. Ground Connections and Supply Bypass.
FIGURE 3. Gain and Offset Adjust Hook-Up.
7
DAC729
3.9MΩ
180kΩ
much more critical as the accuracy of the system increases.
The DAC729 has been designed to minimize these applications problems to a large degree. The basics of “Kelvin
sensing” and “holy point” grounding will be the most important considerations in optimizing the absolute accuracy of
the system. Figure 9 shows the proper connection of the
DAC with the holy-point ground and the Kelvin-sensedoutput connection at the load.
180kΩ
10kΩ
FIGURE 4. Equivalent Resistances.
The DAC729 has three separate supply common (ground)
pins. Reference common (pin 33) carries the return current
from the internal reference and the output I/V converter
common. The current in pin 33 is stable and independent of
code or load. Digital common (pin 20) carries the variable
currents of the biasing circuits. Analog common (pin 30) is
the termination of the R-2R ladder and also carries the
“waste current” from the off side of the current switches.
These three ground pins must be star connected to system
ground for the DAC to bias properly and accurately. Good
ground connections are essential, because an IR drop of just
39µV completely swamps out a 10V FSR 18-bit LSB.
+ Full
Scale
Full Scale
Range
Analog Output
1LSB
Range of
Gain Adj.
Input =
3FFFFH
Gain Adjustment
Rotates the Line
Offset Adj.
Translates
the Line
Input =
00000H
When the application is such that the DAC must control
loads of greater than ±5mA with rated accuracy, it is recommended that an external op amp or op amp buffer combination be used to dissipate the variable power external to the
DAC729. This minimizes the temperature variations on the
precision D/A converter. Figure 10 illustrates a method of
connecting the external amplifier for ±10V operation, while
using an external reference.
Digital Input
FIGURE 5. Relationship of Offset and Gain Adjustments for
a Unipolar D/A Converter.
1LSB
Analog Output
+ Full Scale
Input =
3FFFFH
Full Scale
Range
Bipolar V
Offset
When driving loads to greater than ±10V, care must be taken
that the internal resistors are never exposed to greater than
±10V, and that the summing junction is clamped to insure
that the voltage never exceeds ±5V. Clamping the summing
junction with diodes (parallel opposing connection) to ground
will give the best transient response and settling times.
Range of
Gain Adj.
Gain Adjustment
Rotates the Line
MSB on,
All Others Off
Input =
00000H
TRUE 18-BIT PERFORMANCE
(Differential Linearity Adjustment)
To take full advantage of the DAC729’s accuracy, the four
MSBs have adjustment capabilities. A simplified schematic
(Figure 11) shows the internal structure of the DAC current
source and the adjustment input terminal. The suggested
network for adjusting the linearity is shown in Figure 12.
This circuit has nearly twice the range that is required for the
DAC729JH. The range is intentionally narrow so as to
minimize the effect of temperature drift or stability problems
in the potentiometers. The potentiometers are biased in an
identical fashion to the internal DAC current sources to
minimize power supply sensitivity and drift over temperature. Low leakage capacitors such as Mylar or Teflon film
are essential.
Range of
Offset Adj.
–Full Scale
Offset Adj.
Translates
the Line
Digital Input
FIGURE 6. Relationship of Offset and Gain Adjustments for
a Bipolar D/A Converter.
REFERENCE ADJUSTMENT
The internal reference may be fine adjusted using pin 35 as
shown in Figure 7. Adjusting the reference has a similar
effect on the DAC as gain adjust, except the transfer characteristic rotates around bipolar zero for a bipolar connection
as shown in Figure 8.
The linearity adjustment requires a digital voltmeter with 7
digits of resolution on the 10V range (1µV resolution) and
excellent linearity. For the DAC, 1LSB of the 0V to 10V
scale (10 FSR) is 38µV. To be 1/2LSB linear, the measurement must resolve 19µV. The meter must be properly
calibrated and linear to 1ppm of range.
LAYOUT/APPLICATIONS SUGGESTIONS
Obviously, the management of IR drops, power supply
noise, thermal stability, and environmental noise becomes
DAC729
8
1
40
2
39
3
38
4
37
5
36
6
Ref. Adj.
35
RS = 1MΩ
Gives 20mV
Adjustment Range
RS
1MΩ
1
40
2
39
3
38
4
37
5
36
6
35
7
34
34
8
8
Ref. Out
9
Ref. In
33
Holy Point
Ground Connection
32
9
Ref. Out
10
Ref. In
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
20kΩ
12
29
13
28
14
IOUT
26
16
25
17
24
18
23
19
22
1µF 20
21
+15V
–15V
+
1µF
1µF
+
Digital Common
FIGURE 7. VREF Adjust.
RL
27
15
+5V VDD
+
31
Analog
30 Common
10kΩ
11
32
11
31
10
Common
33
18-Bit
DAC
10kΩ
7
FIGURE 9. Typical Hook-Up Diagram with “Holy Point”
Ground and Kelvin Sense Load, Using Internal
Op Amp and Reference.
Range of
Gain Adjust
With the DAC connected for 0 to 10V output (Figure 13),
the adjustment procedure is to set the DAC code and measure as follows:
+ Full Scale
Analog Output
Gain Adjust
Rotates
the Line
Offset Adjust
Translates
the Line
FOURTH MSB ADJUSTMENT (Pin 36)
1. Set Code = 11 1100 0000 0000 0000
Input = 3FFFFH
2. Measure VOUT
3. Set Code = 11 1011 1111 1111 1111
00000H
4. Measure VOUT and record the difference.
MSB On,
All Others Off 2FFFFH
5. Adjust 4th MSB potentiometer to make difference +38µV.
– Full Scale
THIRD MSB ADJUSTMENT (Pin 37)
6. Repeat steps 1 through 5 to confirm.
1. Set Code = 11 1000 0000 0000 0000
Digital Input
2. Measure VOUT
FIGURE 8. Effect of VREF Adjust on a COB Connected
DAC729.
3. Set Code = 11 0111 1111 1111 1111
4. Measure VOUT and record the difference.
5. Adjust 3rd MSB potentiometer to make difference +38µV.
6. Repeat steps 1 through 5 to confirm.
9
DAC729
SECOND MSB ADJUSTMENT (Pin 38)
1. Set Code = 11 0000 0000 0000 0000
1
40
2
39
3. Set Code = 10 1111 1111 1111 1111
3
38
4. Measure VOUT and record the difference.
4
37
5
36
6
35
7
34
8
9
10
18-Bit
DAC
Ref. In
From System
Reference
MSB ADJUSTMENT (Pin 39)
1. Set Code = 10 0000 0000 0000 0000
2. Measure VOUT
31
12
29
13
28
10kΩ
6. Repeat steps 1 through 5 to confirm.
32
30
10kΩ
5. Adjust 2nd MSB potentiometer to make difference +38µV.
33
11
14
2. Measure VOUT
OPA633
3. Set Code = 01 1111 1111 1111 1111
RL
4. Measure VOUT and record the difference.
OPA602
5. Adjust the MSB potentiometer to make difference +38µV.
6. Repeat steps 1 through 5 to confirm.
27
15
26
16
25
17
24
18
23
19
22
DIGITAL AUDIO
20
21
The excellent linearity and differential linearity are ideal for
PCM professional audio and waveform generation applications.
APPLICATIONS
From System
Reference
The DAC729 is the DAC of choice for applications requiring very high resolution, accuracy, and wide dynamic range.
FIGURE 10. Using an External Op Amp with Buffer and
External Reference for ±10V Output.
FIGURE 11. DAC729 Simplified Schematic.
DAC729
10
40
150kΩ
150kΩ
150kΩ
150kΩ
1.0MΩ
40
2
39
3
38
4
37
5
36
6
35
7
34
100kΩ
0.01µF(1)
–VCC
1.0MΩ
Bit 2 38
Adjust
0.01µF(1)
–VCC
1.0MΩ
37
Bit 3
Adjust
0.01µF(1)
–VCC
1.0MΩ
36
Bit 4
Adjust
0.01µF(1)
–VCC
21
–VCC
100kΩ
100kΩ
8
9
100kΩ
NOTE: (1) Low leakage film type.
FIGURE 12. Differential Linearity Adjustment Circuit for the
4MSBs.
ERMS
=
ERMS
31
11
30
12
29
13
28
27
15
26
16
25
17
24
18
23
19
22
20
21
VOUT
The DAC729 has demonstrated THD of 0.0009% at full
scale (at 1kHz). This is the level of distortion that is desired
to test other professional audio products, making the DAC729
ideal for professional audio test equipment.
The ability to adjust the linearity of the 4MSBs, the 18-bit
resolution, fast settling and low noise give the DAC729
unmatched performance.
AUTOMATIC TEST EQUIPMENT
The pin functions of the DAC729 are convenient for use in
automatic test equipment systems. The ability to use internal
or external reference and internal or external op amp means
versatility for the system designer. For example, in automatic test systems with several DACs and ADCs, it is
desirable to operate all of the high accuracy converters from
the same reference, improving the tracking characteristics of
those components to one another. The reference in the
DAC729 is a very stable precision reference, and is suitable
for use as the system reference.
where n is the number of samples in one cycle of any given
sine wave, EL(i) is the linearity error of the DAC729 at each
sampling point, and EQ(i) is the quantization error at each
sampling point. The THD can then be expressed as
εRMS
32
FIGURE 13. 0 to 10V FSR.
Total harmonic distortion (THD) is the measure of the
magnitude and distribution of the linearity error, differential
linearity error, noise, and quantization error. The THD is
defined as the ratio of the square root of the sum of the
squares of the harmonics to the values of the input fundamental frequency. The rms value of a DAC error can be
shown to be
1 n
εRMS =
∑ [E (i) + EQ(i)]2
n i =1 L
n
1
∑ [EL(i) + EQ(i)]2
n i =1
33
18-Bit
DAC
10
14
The DAC729 offers superb dynamic range. Dynamic range
is a measure of the ratio of the smallest signals the converter
can produce to the full-scale range, usually expressed in
decibels (dB). The theoretical dynamic range of a converter
is approximately 6dB per bit. For the DAC729 the theoretical range is 108dB! The actual dynamic range is limited by
noise (signal-to-noise) and linearity errors. The DAC729’s
6µV typical noise floor, fast settling op amp, and adjustable
18-bit linearity minimize the limitation.
THD =
1
10kΩ
Bit 1 39
Adjust
10kΩ
VPOT
X x 100%(2)
where E rms is the rms signal-voltage level.
Test systems, and other large systems are the ideal application for a DAC of this accuracy, because the DAC will be
calibrated in the environment in which it will be used. Since
the environment is very stable, the manual calibration (Figure 12) may be adequate. However, highly automated systems will go to an automatic calibration routine. Replacing
This expression indicates that, in general, there is a correlation between the THD and the square root of the sum of the
squares of the linearity errors at each digital word of interest.
However, this expression does not mean that the worst-case
linearity error of the D/A is directly correlated to the THD.
11
DAC729
the potentiometers in Figure 12 with VOUT DACs, and using
sample and difference measurements, the major carry bit
weights can be measured, and external DACs used to adjust
the differential linearity of the DAC729. A successive approximation routine yields the fastest calibration. The output
voltage of the external DACs will have to be level shifted,
as the bit adjustment potentiometer must be able to achieve
–VCC to give the full adjust range.
The feedback resistors of the DAC are the input scaling
resistors of the ADC. An OPA602 and an OPA633 make an
excellent buffer for the input signal, giving a very high input
impedance to the signal (minimizing IR drop) while maintaining the linearity.
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
9
10
31
11
30
12
29
13
28
14
With the DAC out of the way, the comparator is the toughest
part of the ADC design. To resolve an 18-bit LSB, and
interface to a TTL-logic device, the comparator must have a
gain of 500kV/V (5X actual) as well as low hysteresis, low
noise, and low thermally induced offsets. With this much
gain, a slow comparator may be desired to reduce the risk of
instability.
32
10kΩ
THE HEART OF AN 18-BIT ADC
The DAC729 makes a good building block in ADC applications. The key to ADC accuracy is differential linearity of
the DAC. The ability to adjust to 18-bit linearity, coupled
with the fast settling time of the DAC729 makes the design
cycle for an 18-bit successive approximation ADC much
faster, and the production more consistent. Figure 15 shows
the DAC as the heart of a successive approximation ADC.
The clock and successive approximation register could be
implemented in 7400 series TTL, as a simple gate-array or
standard cell, or part of a local processor.
33
18-Bit
DAC
10kΩ
Because the DAC729 feedback resistors have a tolerance of
±0.1%, the output range can be rescaled slightly with smallvalue fixed external resistors to give convenient ranges. A
popular range is 0V to +10.24V which gives even 5mV steps
at 11 bits. In this case, the LSB size is 39.06µV. Figure 14
shows how to connect two 240Ω resistors in series with the
internal 10kΩ resistors to give a 0V to 10.24V full-scale
range. Another convenient range might be 0V to +10.48576V
which gives an even 40µV LSB step size.
27
15
26
16
25
17
24
18
23
19
22
20
21
240Ω
240Ω
0 to 10.24V
FIGURE 14. 0V to 10.24V Using Internal Op Amp and
Internal Reference.
DAC729
OPA633
10kΩ
OPA602
Custom Design
Comparator
10kΩ
10MΩ
≈2kΩ
Ref In
Ref Out
To Holy
Point Ground
18-Bits
Clock
SAR
FIGURE 15. Block Diagram of an 18-Bit Resolution ±10VIN ADC.
DAC729
12