BB PCM1750P/PCM1750U

®
PCM1750P
PCM1750U
Dual CMOS 18-Bit Monolithic Audio
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● DUAL 18-BIT LOW-POWER CMOS AUDIO
A/D CONVERTER
● FAST 4.5µs MIN CONVERSION TIME
INCLUDING S/H
● TWO CO-PHASE SAMPLED, ±2.75V
AUDIO INPUTS
● CAPABLE OF 4X PER CHANNEL
OVERSAMPLING RATE
The PCM1750 is a low cost, dual 18-bit CMOS
analog-to-digital converter optimized for dynamic signal applications. The PCM1750 features true co-phased
inputs with an internal sample/hold function for each
channel. The PCM1750 also comes complete with an
internal reference. Total power dissipation is less than
300mW max using ±5V voltage supplies. Low maximum Total Harmonic Distortion + Noise (–88dB max)
is 100% tested. The very fast PCM1750 is capable
of 4X x audio bandwidth oversampling rates on both
input channels simultaneously, providing greater freedom to designers in selecting input anti-aliasing filters.
● RUNS ON ±5V SUPPLIES AND
DISSIPATES 300mW MAX
● COMPACT 28-PIN PLASTIC DIP OR SOIC
PCM1750 outputs serial data in a format that is compatible with many digital filter chips and comes packaged in a space saving 28-pin plastic DIP or SOIC.
● VERY LOW MAX THD+N: –88dB Without
External Adjust
● COMPLETE WITH INTERNAL
REFERENCE AND DUAL S/H FUNCTION
MSB Adj Left
Reference
Offset Adj Left
S/H
VIN Left
CDAC
Left
Comp
S OUT Left
18-Bit SAR
Latch
Shift Register
Control Logic
SOUT Right
VIN Right
Offset Adj Right
Clock
Convert
Latch
Comp
S/H
18-Bit SAR
CDAC
Right
Reference
MSB Adj Right
International Airport Industrial Park • Mailing Address: PO Box 11400
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-1084B
®
1
Printed in U.S.A. October, 1993
PCM1750
SPECIFICATIONS
ELECTRICAL
At 25°C, and ±VA = ±5.0V; +VD = +5.0V, unless otherwise noted. Where relevant, specifications apply to both left and right input/output channels.
PCM1750P, U
PARAMETER
CONDITIONS
MIN
THD + N at –60dB Referred to Full Scale
+88
RESOLUTION
TYP
MAX
18
DYNAMIC RANGE
ANALOG INPUT
Input Range
Input Capacitance
Aperture Delay
Aperture Uncertainty (Jitter)
Full Power Input Bandwidth
DIGITAL INPUT/OUTPUT
Logic Family
Logic Level: VIH
VIL
VOH
VOL
Output Data Format
Convert Command
Convert Command Pulse Width
Conversion Time
UNITS
Bits
+90
dB
±2.75
20
10
50
500
V
pF
ns
psrms
kHz
CMOS Compatible
IIH = ±5µA
IIL = ±5µA
ISOURCE = 1.0mA
ISINK = 3.2mA
Throughput Including Sample/Hold(2)
+3.5
–0.3
+2.7
+VD + 0.3
+1.5
+4.7
+0.2
+0.4
Serial, MSB First, BTC(1)
Positive Edge
81
4.5
5.2
20.8
V
V
V
V
ns
µs
DYNAMIC CHARACTERISTICS (20Hz to 24kHz; 4X data decimated to 1X)
Signal-to-Noise Ratio(3)
Total Harmonic Distortion + N(7)
fIN = 1kHz (0dB)
fIN = 1kHz (–20dB)
fIN = 1kHz (–60dB)
Channel Separation
fs = 192kHz(4); fIN = 1kHz (0dB)(5)
Without External Adjustments
fs = 192kHz
fs = 192kHz
fs = 192kHz
fs = 192kHz; fIN = 1kHz (0dB) and 0V
dB(6)
+88
+90
–88
–68
–28
+96
–90
–70
–30
+108
dB
dB
dB
dB
±5
±2.0
Channel to Channel
±2
±0.5
±2
±3
±0.002
±0.003
1
%
%
mV
mV
% of FSR(10)
% of FSR
ms
DRIFT (With Internal Reference)
Gain
Bipolar Zero
0°C to 70°C
0°C to 70°C
±50
±10
ppm/°C
ppm of FSR/°C
DRIFT (Exclusive of Internal Reference)
Gain
Bipolar Zero
0°C to 70°C
0°C to 70°C
±10
±3
ppm/°C
ppm of FSR/°C
0°C to 70°C
+2.75
±100
0.2
±25
±50
V
µA
Ω
mV
ppm/°C
363 || 120
Ω || pF
0.03
%/%
ACCURACY
Gain Error
Gain Mismatch
BPZ (Bipolar Zero) Error(8)
BPZ Error Mismatch
BPZ Differential Linearity Error(9)
Linearity Error
Warm-up Time
REFERENCE
VREF Output (Pins 19, 24):
Voltage
Current
Impedance
Accuracy
Drift
VREF Input (Pins 18, P25):
Impedance(11)
POWER SUPPLY REJECTION
POWER SUPPLY REQUIREMENTS
±VA Supply Voltage Range
+VD Supply Voltage Range
+IA; +ID Combined Supply Current
–IA Supply Current
Power Dissipation
Channel to Channel
% of VIN / % of VSUPPLY (12)
±4.75
+4.75
+VA; +VD = +5.0V
–VA = –5.0V
±VA = ±5.0V; +VD = +5.0V
TEMPERATURE RANGE
Specification
Operating
Storage
0
–40
–60
±5.00
+5.00
+28
–13
210
±5.25
+5.25
300
V
V
mA
mA
mW
+70
+85
+100
°C
°C
°C
NOTES: (1) Binary Two’s Complement coding. (2) The PCM1750 is tested and guaranteed at 5.2µs, however it will operate at 4.5µs. The dynamic performance is not
guaranteed or tested at this conversion rate. (3) Ratio of SignalRMS / (DistortionRMS + NoiseRMS). (4) A/D converter sample frequency (4 x 48kHz; 4X oversampling per
channel). (5) A/D converter input frequency (signal level). (6) Referred to input signal level. (7) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (8) Externally adjustable
to zero error. (9) Differential non-linearity error at bipolar major carry input code. Externally adjustable to zero error. (10) Full scale range (5.50V). (11) Refer to equivalent
circuit in Figure 1. (12) Worst case operating condition. Refer to typical performance curves.
®
PCM1750
2
PIN ASSIGNMENTS
ABSOLUTE MAXIMUM RATINGS
PIN
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
–5V Analog Supply Voltage
+5V Analog Supply Voltage
Serial Output (Left Channel)
External Clock Input
+5V Analog Supply Voltage
+5V Digital Voltage Supply
+5V Digital Voltage Supply
Digital Common Connection
Analog Common Connection
Digital Common Connection
Convert Command Input
Serial Output (Right Channel)
+5V Analog Supply Voltage
–5V Analog Supply Voltage
Offset Adjust (Right Channel)
MSB Adjust (Right Channel)
Analog Voltage Input (Right Channel; ±2.75V)
Reference Voltage Input (Right Channel)
Reference Voltage Output (Right Channel)
Analog Common Connection
Reference Voltage Decouple
Reference Common Connection
Analog Common Connection
Reference Voltage Output (Left Channel)
Reference Voltage Input (Left Channel)
Analog Voltage Input (Left Channel; ±2.75V)
MSB Adjust (Left Channel)
Offset Adjust (Left Channel)
MNEMONIC
Analog Input Voltage (VIN) .................................. –VA –0.3V to +VA + 0.3V
+VA; +VD to ACOM/DCOM ............................................................ 0 to +7V
–VA to ACOM/DCOM .................................................................... 0 to –7V
–VA to +VA; +VD ......................................................................... 0 to +14V
ACOM to DCOM .................................................................................. ±1V
Digital Inputs (pins 4, 11) to DCOM ........................... –0.3V to +VD + 0.3V
Power Dissipation .......................................................................... 400mW
Lead Temperature, (soldering 10s) ................................................ +300°C
Max Junction Temperature .............................................................. 165°C
Thermal Resistance, θJA: Plastic DIP ............................................ 80°C/W
Thermal Resistance, θJA: Plastic SOIC ....................................... 100°C/W
–VA
+VA
SOUTL
CLK
+VA
+VD
+VD
DCOM
ACOM
DCOM
CONVERT
SOUTR
+VA
–VA
OFFADJR
MSBADJR
VINR
VREFINR
VREFOUTR
ACOM
VREFCAP
RCOM
ACOM
VREFOUTL
VREFINL
VINL
MSBADJL
OFFADJL
NOTE: Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE INFORMATION
MODEL
PCM1750P
PCM1750U
PACKAGE
PACKAGE DRAWING
NUMBER(1)
28-Pin Plastic DIP
28-Pin Plastic SOIC
215
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
TYPICAL PERFORMANCE CURVES
At 25°C, and ±VA = ±5.0V; +VD = +5V, unless otherwise noted. Where relevant, specifications apply to both left and right input output channels.
THD+N vs FREQUENCY
(Without 4X Digital Filter)
THD+N vs FREQUENCY
(With 4X Digital Filter)
–20
–20
VIN = –60dB
VIN = –60dB
–40
VIN = –40dB
THD+N (dB)
THD+N (dB)
–40
–60
VIN = –20dB
VIN = –40dB
–60
VIN = –20dB
VIN = 0dB
–80
–80
V IN = 0dB
–100
–100
0
4
8
12
16
20
0
24
20
40
60
80
100
Frequency (kHz)
Frequency (kHz)
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
PCM1750
TYPICAL PERFORMANCE CURVES
(CONT)
At 25°C, and ±VA = ±5.0V; +VD = +5.0V, unless otherwise noted. Where relevant, specifications apply to both left and right input-output channels.
THD vs FREQUENCY
(With 4X Digital Filter)
THD vs FREQUENCY
(Without 4X Digital Filter)
–70
–70
–80
–80
THD (dB)
THD (dB)
VIN = 0dB
VIN = 0dB
–90
–100
–100
–110
–110
0
4
8
12
16
20
24
0
60
PSR vs FREQUENCY
(–5V SUPPLY)
PSR vs FREQUENCY
(+5V SUPPLIES)
1
0.1
0.1
0.01
% of VIN /% of V SUPPLY
At BPZ:
% of FSR / % of VSUPPLY
80
100
100k
1M
% of VIN /% of V SUPPLY
0.01
At BPZ:
% of FSR / % of VSUPPLY
0.001
0.0001
0.0001
1
10
100
1k
10k
100k
1
1M
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
V REF vs TEMPERATURE
(VREF Outputs)
FFT 850Hz (24kHz BW; 2048 POINTS)
2.80
0
2.78
–25
Amplitude (dB)
VREF (V)
40
Frequency (kHz)
1
0.001
20
Frequency (kHz)
%/%
%/%
–90
2.76
2.74
2.72
–50
–75
–100
–125
2.70
–150
–40
–20
0
20
40
60
80
0
100
Temperature in °C
10
15
Frequency (kHz)
®
PCM1750
5
4
20
24
TYPICAL PERFORMANCE CURVES
(CONT)
At 25°C, and ±VA; +VD = ±5V, unless otherwise noted. Where relevant, specifications apply to both left and right input-output channels.
FFT 17kHz and 21kHz (24kHz BW; 16384 POINTS)
0
–25
–25
–6dB
Amplitude (dB)
Amplitude (dB)
FFT 20kHz (24kHz BW; 2048 POINTS)
0
–50
–75
–100
–50
–75
–100
–125
–125
–150
–150
0
5
10
15
20
0
24
5
15
20
24
FFT 52kHz (96kHz BW; 2048 POINTS)
0
0
–25
–25
Amplitude (dB)
Amplitude (dB)
FFT 3.7kHz (96kHz BW; 2048 POINTS)
–50
–75
–100
–125
–50
–75
–100
–125
–150
–150
0
20
40
60
80
96
0
20
Frequency (kHz)
40
60
80
96
Frequency (kHz)
FFT 92kHz (96kHz BW; 2048 POINTS)
FFT 88kHz and 92kHz (96kHz BW; 16384 POINTS)
0
0
–25
–25
–50
Amplitude (dB)
Amplitude (dB)
10
Frequency (kHz)
Frequency (kHz)
–75
–100
–125
–6dB
–50
–75
–100
–125
–150
0
20
40
60
80
–150
96
0
Frequency (kHz)
20
40
60
80
96
Frequency (kHz)
®
5
PCM1750
THEORY OF OPERATION
OVERVIEW
co-phase sampling which means that both S/H circuits are
switched at the same time into the HOLD mode to capture
their respective input signals simultaneously. This eliminates phasing errors produced by alternative architecture
ADCs which do not sample the two input channels at the
same time.
The PCM1750 is a dual 18-bit successive approximation
CMOS analog-to-digital converter with serial data outputs
designed especially for digital audio and similar applications. The single-chip converter is fabricated on a 3µ P-well
CMOS process which includes poly-poly capacitors, lasertrimmable nichrome resistors, and two layers of interconnect
metal. The dual converter employs a switched capacitor
architecture which provides separate, simultaneous S/H
(sample/hold) functions for each input channel. The separate
S/H for each channel results in a desired feature called
VREF
Switched binary-weighted poly-poly capacitors are used in
CDAC (capacitive digital-to-analog converter) configurations to form the successive approximation converter sec-
CDAC
H1
S1
VIN
S2
S3
C1 (MSB)
20PF
AZ 3
AZ 1
H2
CAZ 3
CAZ 1
A1
Latch
A2
C2
10PF
CAZ 2
AZ 2
Comparator
Data Out
CAZ 4
AZ 4
L
C3
5PF
Auto-Zeroed Comparator
P18, P25
P19, P24
VREF = 2.75V
C1T
Ra
VREFIN
VREFOUT
150k Ω
R1a
47k Ω
Rb
S1T
13.25k Ω
C2T
TDAC
R1b
500 Ω
5k Ω
R2a
+VA (+5V)
+VA (+5V)
S 2T
C 3T
600Ω
P18, P25
R2b
P16, P27
R 3a
VREFIN
917Ω
0 to 120pF
(Code
dependent)
47k Ω
25k Ω
S 3T
MSB Adj
R 3b
.01µF
Simplified
VREFIN Circuit
C12T
R12a
+VA (+5V)
S12T
Coff
R12b
P15, P28
Roffa
25k Ω
100mV
Soff
Off Adj
13.25kΩ
5k Ω
R offb
500Ω
.01µF
Optional External
Adjustment Circuitry
FIGURE 1. PCM1750 Simplified Circuit Diagram.
®
PCM1750
6
tions of the PCM1750. Two other switched-capacitor TDACs
(trim-DACs, which employ laser-trimmed nichrome resistors) are also used to provide small correction voltages to the
latching comparators. These small correction voltages compensate for ratio matching errors of the binary-weighted
capacitors in the CDAC. The comparators contain autozeroed
preamplifier stages ahead of the latching amplifier stage to
produce a one bit, serial data stream that controls the
successive approximation algorithm for each channel of the
PCM1750.
input channel, provide binary-two’s-complement coded output to an optional external digital decimation filter when
over sampling operation is desired. The use of the optional
companion digital filter, the DF1750, is described later in
the installation and application sections of this product data
sheet. A separate product data sheet is also available for the
Burr-Brown DF1750 giving all the specifications and performance diagrams associated with this digital filter.
To simplify user application, the PCM1750 includes an
internal band-gap reference with fast settling buffer amplifiers to drive the CDACs. The dual converters operate synchronously (to minimize digital noise conversion errors)
using an external system clock (normally at 1X, 2X or 4X
the standard 48kHz audio sampling rate). By operating at a
2X or 4X oversampling rate the roll-off requirement for the
input anti-aliasing filters is relaxed. For example, 1X systems typically use a 9 to 11 pole LPF (low pass filter)
whereas a 4X system can use a 6th (or smaller) order filter
when an appropriate digital filter such as the DF1750 is used
in conjunction with the sampling system. Oversampling also
has the added benefit of improved signal to noise ratio and
total harmonic distortion. Two serial outputs, one for each
After each conversion, the dual ADC returns to the SAMPLE
mode in order to track the input signals. The switches shown
in the simplified circuit diagram of Figure 1 will then be in
the following states: S1 connects VIN to C1 ; S2 to S18
connect C2 to C18 to VREF; H1 and H2 connect the top
plates of the capacitor arrays to analog common; and the
latching comparator is switched into its auto-zero mode by
closing AZ1 to AZ4. Notice that C1 serves two purposes: it
samples and stores the input signal VIN and it is the MSB of
the CDAC. Storing VREF on C2 to C18 creates a bipolar
offset, enabling VIN to cover a span from –VREF to +VREF.
SAMPLE (TRACKING) MODE
The 1/f noise as well as the DC input offset voltage of the
comparator are removed by an autozeroing cycle which
64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2
*Master
System
Clock
P11 (CONVERT)
3
2
1
16
4
17
18
19
P4 (EXT CLK IN)
INTERNAL
S/H
CONTROL
SR1
HOLD
SAMPLE
Bit 1 test time
SR2
Bit 2 test time
SR3
Bit 3 test time
P3 (SOUT L)
Bit 1
MSB
Bit 2
Bit 3
Bit 4
Bit 16
Bit 17
Bit 18
LSB
P12 (SOUT R)
Bit 1
MSB
Bit 2
Bit 3
Bit 4
Bit 16
Bit 17
Bit 18
LSB
* Clock from optional digital filter chip (DF1750 4x decimation filter).
FIGURE 2. PCM1750 Input/Output Timing Diagram.
®
7
PCM1750
occurs during the SAMPLE period (see the timing diagram
shown in Figure 2). These errors are stored on the AC
coupling capacitors (CAZ1 to CAZ4, shown in Figure 1)
between the gain stages. During the SAMPLE period the
inputs to gain stages A1 and A2 and the latch are grounded
by switches H1, H2, and AZ1 to AZ4. Capacitors CAZ1 and
CAZ2 track the amplified offset voltage of gain stage A1
and capacitors CAZ3 and CAZ4 do the same for A2. At the
beginning of a conversion cycle, the autozeroing switches
open and the instantaneous amplified value of both the DC
offset voltage and the low-frequency flicker noise is stored
on the coupling capacitors to produce zero comparator offset
during a conversion cycle.
analog common (see Figure 1). This terminates the comparator auto-zero cycle and simultaneously switches (cophase sampling) both converters from tracking their respective input signals into the HOLD mode, thus capturing the
instantaneous value of VIN (with a small delay specified as
the aperture time).
At the start of a conversion cycle when S1 is switched to
analog common, the sampled input signal VIN will appear at
the comparator input as –VIN/2 due to the 2-to-1 capacitive
divider action of Cl = C2 + C3 + ... C18. In a somewhat
similar manner, VREF is transferred to the comparator input
as –VREF/2 to create a bipolar offset.
The 19-bit shift register, shown in Figure 4, controls testing
of the bits of the dual ADCs beginning with bit-1 (MSB) and
proceeding one bit at a time to bit-18 (LSB), leaving ON
those bits that don’t cause the cumulative value of the
CDAC to exceed the original input value and leaving OFF
those bits that do. Since the bits of both channels are tested
together, only one shift register is required to control both
ranks of 18 data latches.
SUCCESSIVE APPROXIMATION
CONVERSION PROCESS
The timing diagram in Figure 2 illustrates the successive
approximation routine of the PCM1750. Control signals
CONVERT and CLK are derived from a master system
clock which comes from a 256fS (256 X the base sampling
frequency of 48kHz) clock used by the optional digital filter.
There are 64 clocks shown in the timing diagram because the
PCM1750 is shown operating at 4 times the standard 48kHz
sample rate (192kHz).
For example, the testing of bit-2 proceeds in the following
manner. The positive pulse from the second shift register
element SR2, (see Figure 2 and 4) is applied to the bit-2 data
latch and NOR gate. The NOR gate in turn drives S2 and
switches bit-2 at the beginning of the bit-2 test interval. Note
that the bit interval must be long enough to allow both the
comparator input to settle and the comparator to respond. On
Several events occur on the rising edge of the CONVERT
command. Switches AZ1 to AZ4, H1 and H2 open and
switch S1 reconnects the MSB capacitor, C1, from VIN to
TREF
54 55 56 57 58 59 60
61 62 63 64
1
2
3
4
7
6
5
8
10 11 12
9
*Optional
Digital Filter
T1
Convert
T4
T2
18
Ext Clk In
T3
T5
1
19
T6
3
2
T7
SOUT
Bit 17
Bit 18
LSB
Bit 1
MSB
T8
PARAMETER
T1
(1 x TREF)
T2
(6 x TREF)
T3
(4 x TREF)
T4
(3 x TREF)
T5
(1 x TREF)
T6
(2 x TREF)
T7
T8
T9
TCONV (64 x TREF)
TREF (Sample Rate /64)
Bit 2
T9
DESCRIPTION
MIN
NOMINAL
MAX
UNITS
Convert Command High
S/H Acquisition Time
Convert to Clock time
Master Clock Input
Clock High
Clock Low
Data Hold Time
Data Setup Time
Data Valid Time
Conversion Throughput Time
Ext Digital Filter Clock
24
420
281
211
24
45
10
33
486
326
244
33
67
55
1302
977
55
76
120
4.5
70
154
5.2
81
100
1212
20.8
326
% of T4
ns
ns
ns
% of T4
% of T4
ns
ns
ns
µs
ns
Note: The nominal timing shown in this diagram is all done automatically by the DF1750 digital filter. Only the
optional digital filter clock is required when the DF1750 is used.
FIGURE 3. PCM1750 Setup and Hold Timing Diagram.
®
PCM1750
8
the next rising edge of CLKIN, at the end of the test interval,
the comparator latch is strobed, providing a feedback logic
level which tells the second data latch if bit-2 should be kept
or rejected. This logic level is stored in the data latch and is
passed on to switch S2 via the NOR gate on the falling edge
of the pulse from SR2. This decision to keep or reject bit-2
moves the comparator input closer to a null condition,
namely, zero potential. This sequential process continues for
bit-3 through bit-18 and nulls the comparator inputs to
within a value limited by the total system noise and the
resolution/speed of the comparator.
controlled process, ratio matching is typically 0.1% — a
very respectable number for an untrimmed component. Even
more impressive is their ratio tracking versus temperature of
approximately 0.1ppm/°C.
Achieving DLE (differential linearity error) of less than 1/2
LSB at the 16-bit level requires ratio matching of the more
significant bits to about 0.001%. Since the untrimmed ratio
matching of poly capacitors is about two orders of magnitude larger than this requirement, a one-time factory calibration of the upper bits is required as described in the next
section. Next, consider the effect of temperature due to the
ratio tracking of 0.lppm/°C. Over a 50°C span, DLE will
change less than 1LSB at 18-bits; therefore, recalibration at
temperature extremes is not necessary. Because of this
excellent stability versus temperature (and versus time, also),
the one-time factory calibration to correct initial DLE is
more than satisfactory in meeting the accuracy requirements
of the PCM1750.
Notice from the timing diagram in Figure 2 that the successive approximation algorithm operates synchronously with
an external clock to minimize digitally-coupled switching
noise from corrupting either the sample-to-hold operation or
the critical comparator bit decisions. The two serial output
data streams are derived synchronously from the respective
latched comparator outputs and are available after a delay of
one CLKIN cycle as illustrated in Figure 2. The serial output
driver cells are TTL and CMOS compatible.
TDAC OPERATION
Operation of the TDAC (trim DAC), which is laser trimmed
at the wafer level, is described using bit-1 as an example.
Switch S1T (see Figure 1) operates between two voltage
levels—a reference level set by voltage divider Ra, Rb and
a laser trimmable level set by R1a, R1b. The differences of
these two levels is coupled by capacitor C1T to the minus
input of the comparator to generate a correction voltage for
DIFFERENTIAL LINEARITY CALIBRATION
To understand the calibration of the PCM1750 it is necessary to discuss some of the characteristics of poly-poly
capacitors. Poly capacitors are known to have equal or better
stability and matching properties when compared to other
precision components such as thin film resistors. On a well
Serial Data
From Latching
Comparator
To MSB
Switches Left
D
Data
Latches
Left Channel
19-Bit
Shift
Register
Data
Latches
Right Channel
D
Q
To Bit 18
Switches Left
D
Q
L R
L R
L R
D
Q
SR1
S
D
Q
SR2
R
D
Q
SR18
R
L R
L R
L R
D
Serial Data
From Latching
Comparator
Q
To Bit 2
Switches Left
Q
D
Q
D
To MSB
Switches Right
To Bit 2
Switches Right
D
Q
SR19
R
Control
Logic
Q
To Bit 18
Switches Right
FIGURE 4. PCM1750 Successive Approximation Logic Diagram.
®
9
PCM1750
bit-1. The switches of the CDAC and the switches of the
TDAC operate concurrently with each other, that is, when a
decision is made to keep or reject bit-1, the same decision is
made for the correction voltage for bit-1. Even though the
ratio stability of the nichrome resistors used in the TDAC
may not be as good as the poly capacitors, it is inconsequential because the correction voltage of each bit has a limited
range of adjustment.
A Gain Change
Rotates
Transfer
Function
1FFFFH
Digital Output
1FFFEH
The DLE at the major carry (a code change from 111...111
to 000...000; in binary two’s complement coding) is typically ±1/2 LSB at the 16-bit level, which is sufficient to
provide 90dB SNR and –30dB low level distortion (–60dB
input). For applications requiring less DLE at the major
carry, a pin is provided for each channel to make an external
MSB adjustment.
00001H
00000H
3FFFFH
–2.75
–20.98µV
Offset Change
Shifts
Transfer
Function
+2.749979
0.00V
20001H
20000H
* Gain drift (mostly due to reference drift) rotates the transfer function
around the bipolar zero code (00000HEX ).
DISCUSSION
OF SPECIFICATIONS
NOTE: As the power supply voltages change (mostly due to the +V
supply), the transfer function rotates around BPZ. See the power
supply rejection specification in the spec table.
RESOLUTION AND DYNAMIC RANGE
FIGURE 5. Analog Input to Digital Output Diagram.
The theoretical resolution of the PCM1750 is 18-bits. The
maximum possible number of output codes or counts at 18bits is 262,144 or 108dB (calculated by raising 2 to the 18th
power). The relative accuracy of any A/D converter, however, is more a function of it’s absolute linearity and signalto-noise ratio than how many bits of resolution it has. These
more pertinent specifications are described later in this
section.
From Figure 5, the effects of offset and gain errors can be
visualized. These errors can change value in response to
changes in temperature and/or supply voltage. In addition,
gain error (or the full scale range, FSR) changes in direct
proportion to the VREFIN voltage value.
SAMPLE AND HOLD PARAMETERS
Aperture Delay and Uncertainty
Dynamic range, as it is usually defined for digital audio
converters, is the measure of THD+N at an effective input
signal level of –60dB referred to 0dB. For the PCM1750 this
value is typically 90dB and a minimum of 88dB (for audio
bandwidth = 20Hz to 24kHz, THD+N at –60db = –30 db typ,
–28dB max; fIN = 1kHz and fS = 192kHz). Resolution is also
commonly used as a theoretical measure of dynamic range,
but it does not take into account the effects of distortion and
noise at low signal levels.
Aperture delay is the time required to switch from the
SAMPLE to HOLD mode. This time is typically 10ns for the
PCM1750 and it is constant. Aperture uncertainty (jitter) is
the amount of uncertainty associated with the aperture delay.
Aperture uncertainty affects the overall accuracy of the
converter and is greatest at the maximum input frequency of
the converter. The formula for determining the maximum
input frequency (fMAX) for a given error contribution due to
aperture uncertainty is: fMAX = (2 X π X tjitter X 2N)–1 where
tjitter is the RMS aperture uncertainty and 2N is the desired
SNR (signal-to-noise ratio) expressed in total number of
quantization levels. A 15-bit SNR, therefore, would be
expressed as 215 or 32768. Using the typical PCM1750
aperture jitter of 50psrms and an SNR at the 15-bit level, fMAX
= (2 X π X 50ps X 32768)–1 or 97.1kHz. This matches very
closely with the rated dynamic accuracy of the PCM1750
where THD+N = –88dB max. This means the typical aperture jitter of PCM1750 only becomes a factor when input
signals to it exceed 97kHz and/or an SNR greater than 15
bits is desired.
ANALOG INPUT RANGE
The analog input range for the PCM1750 is a bipolar ±2.75V
(nominal). Table I gives the precise input/output and voltage/code relationships for the PCM1750. Figure 5 shows
these same relationships in a graphical format. It should be
noted that the computed voltage input levels represent center
values (the midpoint between code transitions). Output coding is in binary two’s complement.
DIGITAL OUTPUT
262144 LSBs
1 LSB
1FFFFHEX
00000HEX
3FFFFHEX
20000HEX
ANALOG INPUT
VOLTAGE INPUT
Full Scale Range
Minimum Step Size
+Full Scale
Bipolar Zero
Bipolar Zero –1LSB
–Full Scale
5.50000000V
20.98083496µV
+2.74997902V
0.00000000V
–0.00002098V
–2.75000000V
Input Bandwidth
The full power bandwidth of the PCM1750 is that input
frequency above which significant distortion is observed
(THD+N > 10-bits or –60dB for a full scale input signal). In
the data sheet, this number is specified as typically being
500kHz. In wideband operation (when no digital filter is
used) the additional full power bandwidth of the PCM1750
TABLE I. Analog Input to Digital Output Relationships.
®
PCM1750
10
can be used to purposely alias a band-limited signal down
into the baseband of the converter. This technique is called
undersampling and can be used to directly down-convert an
intermediate frequency riding on a much higher carrier
frequency.
Clock Lockout
Any number of clocks can be given to the PCM1750 beyond
the 19 required for normal operation. If a continuous clock
is used, all clocks beyond the 19th are gated off by the
PCM1750’s internal logic until the next positive going edge
of the convert command. The converter also goes into the
sample (track) mode starting on the positive edge of the 19th
clock until the next positive edge of the convert command,
regardless of how many additional clocks are offered. The
ideal operation of the converter stops the clock input after
the 19th during this critical signal acquisition time. This is
the timing shown in Figure 3 . The critical timing aspect that
must be observed if a clock input other than the recommended is used, is that ample time following the positive
edge of convert command proceed the next rising clock
edge. If this time is shortened, the most important bit-1
(MSB) decision, which is finalized on the first clock edge
after convert command, will be adversely affected. In other
words, the clock input cannot have a rising edge during the
time interval T3 shown in Figure 3.
DIGITAL I/O AND TIMING
Input/Output Logic Compatibility
Digital logic on the PCM1750 is CMOS compatible. Digital
outputs on the PCM1750 are capable of driving a minimum
of two standard TTL input loads.
Digital output coding is in binary two’s complement. Table I
gives the precise input/output voltage/code relationships for
the PCM1750. Figure 5 shows these same relationships in a
graphical format.
Convert Command and External Clock Input
A conversion is initiated on its positive going edge of the
convert command. Although the convert command can return low at any time (prior to 50ns before the rising edge of
the 19th clock), a typical convert command pulse width of
81ns (as called out in Figure 3) is specified for a 192kHz
sample rate (fS). The reason for a pulse width spec is to
reduce problems associated with digital logic feedthrough
noise. The return of convert command to a logic low level in
the specified time interferes least with the successive approximation process. Also, it should be noted that putting
fast logic edges (<5ns) on convert command (P11) and the
external clock input (P4) may cause logic feedthrough to the
analog stages in the converter and will result in added
distortion during the sampling and conversion process.
Using the optional DF1750 digital filter provides adequately
slow transitions to maintain full specification performance.
If necessary, an external RC, on the convert command line
may be used to slow fast logic edges.
SIGNAL-TO-NOISE RATIO
Another specification for A/D converters is signal-to-noise
ratio (SNR). For this measurement, a full-scale 1kHz signal
is applied and the sampling rate of the PCM1750 is set at
192kHz. An FFT is performed on the digital output and the
noise power in the non-harmonic audio-bandwidth frequency
bins (20Hz to 24kHz) is summed and expressed in relation
to the full-scale input signal.
One advantage of using the PCM1750 in this oversampled
mode with the optional DF1750 digital decimation filter is
that the converter noise is spread over the full 0Hz to 96kHz
passband and then suppressed by the digital filter stopband
attenuation (from 24kHz to 96kHz). This effectively increases the SNR of the PCM1750 by 6dB when it is used as
an audio bandwidth converter. The other advantage is that
the need for a higher-order anti-aliasing input filtering is
greatly reduced.
As with the convert command, the external clock input is
positive edge triggered and is not duty-cycle dependent
other than to improve digital feedthrough noise immunity. A
50% duty cycle clock can be used instead of 33% if desired.
Refer to Figure 3 for recommended timing relationships.
Regardless of what clock duty cycle is used, all operations
relating to valid data clocking should be synchronized to the
rising edge of the clock input.
THD + N
The key specification for the PCM1750 is total harmonic
distortion plus noise (THD+N). In terms of signal measurement, THD+N is the ratio of DistortionRMS + NoiseRMS /
SignalRMS expressed in dB. For the PCM1750, THD+N is
100% tested at all three specified input levels using the
production test setup shown in Figure 6. For this measurement, as with the SNR test, a full-scale 1kHz signal is
applied and the sampling rate of the PCM1750 is set at
192kHz (which is 4X the standard digital audio sample rate
of 48kHz). An FFT is performed on the digital output and
the total power in all audio-bandwidth frequency bins (20Hz
to 24kHz) is summed and expressed in relation to the fullscale input signal.
Although there is a maximum conversion time called out in
the specification table, the PCM1750 can have a considerably longer conversion cycle. Droop of the internal capacitors will ultimately determine what the true maximum
conversion time can be. The min/typ/max times shown in
Figure 3 are based on minimum sample rate of 48kHz, a
typical of 192kHz, and a maximum of 222kHz. All specifications are tested at 192kHz. The minimum sample rate
assumption is based on clock periods that increase as time
between convert commands increases. Any sample rate
down to near DC can be utilized by observing maximum
clock cycle requirements and spacing convert commands to
achieve lower sample rates. This means that the time interval
T2 shown in Figure 3 does not have a maximum value.
For the audio band, the THD+N of the PCM1750 is essentially flat for all frequencies and input signal levels. In the
Typical Performance Curves THD+N versus Frequency
®
11
PCM1750
plots are shown at four different input signal levels (with and
without a 4X decimation filter): 0dB, –20dB, –40dB, and –
60dB.
No Missing Codes Operation
A no missing codes specification is not given for the
PCM1750 for the same reasons as given above. The
PCM1750, however, typically has fewer than 16 codes (less
than 0.01%) missing at a 14-bit resolution level. A 100% no
missing codes specification cannot be maintained above the
12-bit level, although this has very little impact on overall
dynamic performance (THD+N). The few missing codes
that do occur at higher resolution levels are at the bit-2 and
lower major carry transitions of the converter. There are
typically no missing codes (at 14 bits) around the critical
bipolar zero operation zone (±1/8 of full scale range around
bipolar zero or 0V). The critical bipolar differential linearity
error can be reduced from its initial value to zero using the
optional MSB adjustment circuitry shown in the connection
diagram (Figure 7).
CHANNEL SEPARATION
To test channel separation a 1kHz signal sampled at 192kHz
is placed on one input of the PCM1750 while the other input
is held at 0V. An FFT is performed on the idle (0V) channel
and the result checked to insure that the 1kHz tone is
suppressed by a minimum of 96dB.
GAIN AND OFFSET ERRORS
Initial gain and bipolar offset errors are laser trimmed at the
wafer level and 100% final tested to insure compliance with
the electrical specifications. Bipolar offset errors can be
further reduced to zero by using the optional offset adjustment circuitry shown in the connection diagram (Figure 7).
Gain errors can be adjusted by varying VREF to either
channel of the converter. This is accomplished by either
using an adjustable external reference or by placing buffer
amplifiers with adjustable gain between VREFOUT and
VREFIN as shown in Figure 8a.
REFERENCE
The gain drift of the PCM1750 is primarily due to the drift
associated with the reference. Better drift performance can
be achieved using an external reference like the ones explained in the applications section (Figures 8b, 8c). The
Typical Performance Curves plot of VREF Output versus
Temperature shows the full range of operation including
initial error and typical gain drift. Pertinent performance
data are found in the electrical specification table.
INTEGRAL AND DIFFERENTIAL LINEARITY
DC Linearity Testing
The absolute linearity of the PCM1750 is on the order of 15
bits or more as can be seen from the THD versus Frequency
plots in the Typical Performance Curves. Not every code in
the converter must be 15-bit linear to achieve the specified
THD+N performance, but a very high percentage will be
that linear. The same observation also applies to differential
linearity errors in the PCM1750. Because the PCM1750 is
not 100% tested for DC linearity specifications, no minimum or maximum specifications are given for integral or
differential linearity errors.
Reference Bypass
Both P18 and P25 (VREFIN) should be bypassed with a
10µF to 47µF tantalum capacitor. If there are important
system reasons for using the PCM1750 reference externally,
the outputs of P19 and P24 must be appropriately buffered,
and bypassed (see Figure 8).
fs = 192kHz
Timing
Control
High
Accuracy
Sine Wave
Generator
PCM1750
Low Pass
Filter
V INR
fIN = 1kHz
Serial Data Left
Serial Data Right
FTT
Analyzer
Parametric
Tester
FIGURE 6. PCM1750 Production Test Setup.
®
PCM1750
V INL
12
POWER SUPPLY REJECTION
Because of the architecture of the PCM1750, power supply
rejection varies with input signal size. The spec table value
is expressed in the relative terms of percent of VIN per
percent change of the supply voltage. The PSR versus
Frequency plot in the Typical Performance Curves show
PSR expressed versus an increase in power supply ripple
frequency.
Dynamic Performance
PERFORMANCE OVER TEMPERATURE
Specification Temperatures
INSTALLATION
Dynamic performance is predominated by the absolute linearity of the PCM1750. Because of the excellent ratio
tracking versus temperature of poly-poly capacitors, there is
virtually no change in dynamic performance of the converter
over temperature (primarily THD+N). The dynamic specifications over temperature cannot be guaranteed, however, as
they are not 100% tested.
ANTI-ALIASING FILTER
To prevent unwanted input signals from being aliased into
the passband of the converter, it is necessary to suppress all
out of band signals above 1/2 the sampling frequency of the
ADC by using a low-pass filter. The requirement for an antialiasing filter, however, can be reduced by using oversampling
techniques. By raising the sample rate of the converter by a
factor of 2 or even 4, the roll off of the anti-aliasing filter can
be reduced. In Figure 9, a 6th order, linear-phase, antialiasing filter is implemented using low-cost dual audio op
amps. This filter will suppress frequencies above 96kHz by
80dB. For many applications a 4th or 2nd order anti-aliasing
filter will be adequate when using the PCM1750 in the 4x
oversampling mode.
All critical specifications are tested at 25°C. The drift
specification temperature range is from 0°C to +70°C. The
PCM1750 will operate over the wider temperature range of
–40°C to +85°C.
Gain and Offset Drift
Although the PCM1750 is primarily meant for use in dynamic applications, specifications are also given for more
traditional DC drift parameters such as temperature gain and
offset drift. The primary cause of drift in the PCM1750 is the
bandgap reference. Much lower gain drift can be realized if
necessary by using any circuit similar to the external reference circuits shown in Figure 8. Also, refer to the Typical
Performance Curves of VREF Output versus Temperature.
Optional External Adjust
10µF*
10Ω
1
2
+
3
Offset Adj Left
–V A
MSB Adj Left
+V A
28
150kΩ
0.01µF
25kΩ
27
0.01µF
SOUT Left
VIN Left
26
Ref In Left
25
Ext Clk In
5
+V D
Ref Out Left
24
6
+V D
ACOM
23
7
+V D
Ref Com
22
8
DCOM
Ref Bypass
21
9
ACOM
ACOM
20
10
DCOM
Ref Out Right
19
+
11
Convert
12
SOUT Right
25kΩ
+ 10µF*
or
47µF
10µF*
+5V
150Ω
220pF
4
Ref In Right
18
VIN Right
17
0.1µF
(low
leakage,
ceramic)
10µF*
or
47µF
Optional External Adjust
+
150Ω
220pF
13
+V A
MSB Adj Right
16
14
–V A
Offset Adj Right
15
10Ω
–5V
* High quality tantalum.
47kΩ
47kΩ
150kΩ
47kΩ
47kΩ
25kΩ
0.01µF
25kΩ
0.01µF
= Connect directly to ground plane
FIGURE 7. PCM1750 Connection Diagram.
®
13
PCM1750
INPUT SIGNAL CONDITIONING
RC Input Circuit
MSB Adjust
The MSB adjust pin connects to the center of the R1a/R1b
resistive divider for bit-1. After laser trimming this point is
nominally 100mV. All the MSB and offset adjust pins
should be connected to ground using a 0.01µF capacitor,
especially if traces to the potentiometers are long. If the
adjust pins are not used, they should still be bypassed to
ground.
Note the 150Ω resistors and 220pF capacitors on each
analog input as shown in the connection diagram (Figure 7).
This input circuit configuration is required to achieve optimum SNR performance of the PCM1750. Various other
component values will yield satisfactory results, but the
resistor should never exceed 200Ω.
Since there are internal 5kΩ resistors and clamp diodes to
both ground and +5V on the MSB and offset adjust pins,
there are obvious limits to their range of adjustment. With a
nominal internal voltage on these points of +100mV, there
will be a greater limitation in making negative adjustments
than positive. A negative voltage at either adjustment pin,
however, is acceptable up to one diode drop (–0.6V) below
ground.
Buffer Amplifier
To avoid introducing distortion, the PCM1750 input must be
driven by a low active impedance source (op amps such as
the NE5532, Burr-Brown OPA2604, or equivalent are ideal).
EXTERNAL ADJUSTMENTS
The simplified circuit diagram (see Figure 1) shows one of
two complete channels on the PCM1750. The input switched
capacitors, trim DAC and comparator are detailed. The trim
DAC switches are activated whenever the corresponding bit
is chosen during the successive approximation routine. The
first 12 bits of the ADC have corresponding trim DAC
circuits. The R1a to R12a and R1b to R12b resistors can be
laser trimmed at the wafer level if necessary to correct for
any nonlinearities. The nominal voltage for the internally
generated VREF is 2.75V and it is a relatively low impedance, buffered voltage output. It should be noted that just
the act of connecting the optional adjustment circuits will
affect the MSB DLEs and bipolar offsets since it is unlikely
that the initial potentiometer settings (even if centered)
would match the factory trimmed null potentials. If connected, the potentiometers must be properly adjusted.
VREF INR
18
+
The preferred method of MSB DLE adjustment is to input a
small level signal and adjust for minimum THD+N.
Offset Adjust
The offset adjust switch (SOFF) position is controlled by
whether the ADC is in the sample or hold mode. Switching
from sample to hold effectively allows any charge offsets
associated with the sampling process to be eliminated.
Grounding the input to the converter as far ahead of the A/D
as possible (in front of the anti-aliasing filter for example)
and then adjusting the bipolar zero error will remove the
offsets associated with the entire sampling system.
LAYOUT CONSIDERATIONS
Power Requirements
Noise on the power supply lines can degrade converter
performance, especially noise and spikes from a switching
power supply. Appropriate supplies or filters must be used.
Although the PCM1750 positive supplies have separate
digital and analog +5V, for most applications the +5V
digital supply pins should be connected to the +5V analog
supply. If they aren’t connected together, a potential latchup
condition can occur when the power supplies are not turned
on at the same time. If one supply pin is powered and the
other is not, the PCM1750 may latch up and draw excessive
current. In normal operation, this is not a problem because
both +VA and +VD should be connected together. However,
during evaluation, incoming inspection, repair, etc., where
the potential of a “hot” socket exists, care should be taken to
power the PCM1750 only after it has been socketed.
10µF
1kΩ
VREF OUTR
19
+
1µF
VREF INL
25
+
1/2 5532
10µF
1kΩ
VREF OUTL
24
+
1µF
+5V
39kΩ
1/2 5532
39kΩ
All supplies should be bypassed as shown in Figure 7. The
bypass capacitors should placed as close to their respective
supply pins as possible. Additional .01µF capacitors may be
placed in parallel with the larger value capacitors to increase
high-frequency rejection, but generally they are not required
when high quality tantalums are used. The 0.1µF capacitor
between P21 and P22 should be a low leakage type (such as
ceramic) and must be put as close to these pins as possible
to reduce noise pickup.
+5V
50kΩ
50kΩ
–5V
–5V
FIGURE 8a. Circuit for External Gain Adjustment Using the
Internal Reference.
®
PCM1750
14
The PCM1750 is sensitive to supply voltages outside the
absolute maximum ratings shown in the specification tables.
Do not exceed –8V on the negative supplies at any time or
irreversible damage may occur. Note the 10Ω resistors in
series with each –5V supply line (shown in Figure–7) to help
protect the part from severe damage if the supplies are overranged momentarily.
Coupling between analog input and digital lines should be
minimized by careful layout. For instance, if the lines must
cross, they should do so at right angles. Parallel analog and
digital lines should be separated from each other by a pattern
connected to common.
If external MSB and offset adjust potentiometers are used,
the potentiometers and related resistors should be located as
close to the PCM1750 as possible.
Grounding Requirements
Because of the high resolution and linearity of the PCM1750,
system design problems such as ground path resistance and
contact resistance become very important.
Minimizing “Glitches”
Coupling of external transients into an analog-to-digital
converter can cause errors which are difficult to debug. Care
should be taken to avoid glitches during critical times in the
sampling and conversion process. Since the PCM1750 has
an internal sample/hold function, the signal that switches it
into the HOLD state (CONVERT going HIGH) is critical, as
it would be on any sample/hold amplifier. The CONVERT
rising edge should have minimal ringing, especially during
the 20ns after it rises.
The ACOM and DCOM pins are separated internally on the
PCM1750. To eliminate unwanted ground loops, all commons (both analog and digital) should be connected to the
same low-impedance ground plane. This should be an analog ground plane separate from other high-frequency digital
ground planes on the same board. If the analog and digital
commons of the PCM1750 are connected to different ground
planes, care should be taken to keep them within 0.6V of
each other to insure proper operation of the converter.
APPLICATIONS
A ground plane is usually the best solution for preserving
dynamic performance and reducing noise coupling into
sensitive converter circuits. Where any compromises must
be made, the common return of the analog input signals
should be referenced to the ACOM pins. This will prevent
voltage drops in the power supply returns from appearing in
series with the input signal.
10kΩ
1/2 5532
2.5V
MC1403
2
VREF OUTR
VREF OUTR
19
+
1µF
19
+
1µF
1kΩ
+5V
1
USING A DIGITAL FILTER
A 4x decimation filter is available for the PCM1750 called
the DF1750. It is available in a 28-pin DIP or a 40-pin SOIC
package. The use of this filter greatly eases the implementation of the PCM1750 in audio band applications.
909Ω
+
1/2 5532
+15
VREF INR
2.75V
18
+
10µF
2
10V
1µF
6
REF102
10kΩ
8
1kΩ
10kΩ
3
1/2 5532
909Ω
0.1µF
1µF
+
4
VREF INR
2.75V
18
+
10µF
26.36kΩ
+
1µF
1/2 5532
VREF INL
2.75V
25
+
10µF
VREF INL
2.75V
25
+
10µF
VREF OUTL
VREF OUTL
24
+
1µF
24
+
1µF
FIGURE 8b. External Reference Circuit Using Standard
2.5V Reference.
FIGURE 8c. Low Noise, Low Drift External Reference
Circuit.
®
15
PCM1750
FIGURE 9. Complete Sampling A/D Circuit with Anti-aliasing and Digital Filter, (44.1kHz output data rate).
®
PCM1750
16
A1*
5
A4*
5
1000pF
3.48k Ω
1000pF
2
3
A4*
1.33k Ω
A1*
1
1
7
1000pF
3
2
7
1
3.92kΩ
A6*
5
6
7.32k Ω
7.32k Ω
1
3.92k Ω
5
6
7.32kΩ
7.32kΩ
A3*
A5*
A2*
1000pF
3
2
A3*
1000pF
3.48k Ω
1000pF
2
3
A6*
1000pF
1.33kΩ
1000pF
3.48k Ω
1000pF
2
3
1000pF
1
5
6
1
1.33k Ω
A5*
5
6
7
A2*
7
*A1 - A6 = 1/2 Burr-Brown OPA2604 with ±15V supplies (or NE5532 equivalent with ±5V supplies).
7
6
7.32k Ω
7.32kΩ
3.92kΩ
1000pF
3.48k Ω
1000pF
2
6
Left Channel
Analog Input
7
3
1.33k Ω
7.32kΩ
7.32kΩ
3.92kΩ
Right Channel
Analog Input
25k Ω
150Ω
150Ω
25k Ω
10 µF
0.1µ F
10 µF
25k Ω
47k Ω
150k Ω
0.01µ F
47k Ω 0.01µ F
220pF
220pF
+
+
150k Ω
47kΩ
0.01µF
0.01µF
47k Ω
25kΩ
AGND
28 OFF ADJ
27 MSB ADJ
26 VINL
25 VREF IN
–VA 14
+VA 13
10Ω
10Ω
+5V
+
–5V
10µF + 10µF
–VA 1
+VA 2
SOUTL 3
CLK 4
+VD 5
+VD 6
+VD 7
DCOM 8
ACOM 9
DCOM 10
CONVERT 11
SOUTR 12
DGND
24 VREF OUT
23 ACOM
22 REF COM
21 REF CAP
20 ACOM
19 VREF OUT
18 VREF IN
17 VINR
16 MSB ADJ
15 OFF ADJ
PCM1750P
+5V
CC
DINR
VSS2
IMOD
2DS
TEST
SCSL2
SCSL1
CKO
14 VDD2
13 DINL
12 IBO
11 IBCK
10 BBC
9
8
7
6
5
4
3
2
1
OW20
FSEN
LRCK
LRPOL
OBPOL
WDCK
VSS1
BCK
DOUT
MUTE
XTI
XTO
CKEN
VDD1
DF1750P
(28-PIN DIP PKG)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
10pF
+5V
Interleaved
Digital Output
10pF
16.9344 MHz
1.00M Ω
USING AN EXTERNAL REFERENCE
Normally VREFOUT is connected directly to VREFIN. The
typical value for VREF versus Temperature is shown in the
Typical Performance Curves. If better drift or power supply
rejection performance is desired, one of the external reference circuits shown in Figures 8b and 8c can be used. Note
that the decoupling capacitors are still connected to VREFIN.
External gain adjustment is now possible by using the
variable output options available on some precision voltage
references or by varying the gain on external buffer amplifiers. The range of acceptable external references is from
+2.0V to +VA – 2.0V, with 2.5V types being the most
commonly available. Full scale input voltage range will be
±VREFIN (a +2.5V VREFIN results in a ±2.5V input range).
the DF1750P. Not shown on this schematic, but included on
the demo fixture, are latched parallel data outputs with
strobe and a serial digital interface format (SPDIF) data
transmitter. Also included on the DEM1133 are user breadboard areas for application specific circuit implementation.
CONNECTION TO DSP WITH DIGITAL FILTER
The PCM1750 and DF1750 combination can be connected to
the serial ports of most popular DSP processor ICs (such as
those made by AT&T, Motorola, TI, and AD) by adding a
small amount of external glue logic. Figures 10 and 11 show
the timing diagram and schematic for this interface.
To use this interface, the DSP processor IC must be configured
for 32-bit word inputs. The glue logic generates a flag bit, as
the first bit of the 32-bit word, that signifies either left or right
channel data. The flag bit will be low for left channel data and
high for right channel data.
If an external reference is used, P19 and P24 must be
bypassed with at least 1µF capacitors.
SAMPLING A/D SYSTEM
Figure 9 is a partial schematic of the demonstration fixture
for the PCM1750 (orderable by model number DEM1133).
It shows the implementation of (1) a 6th order, linear-phase,
anti-aliasing filter (22kHz low-pass); (2) the PCM1750P
A/D converter; and (3) a 4x digital decimation filter called
The DF1750 can be configured for either 16- or 20-bit data,
although only 16-bit data is shown in Figure 10. After the data
is transferred into the DSP processor IC, it must be shifted
toward the LSB by one bit in order to compensate for a clock
delay in the glue logic.
LRCK
(LRPOL = H)
WDCK
Frame Syn L
Flag Enable
Bit Clock
Data to DSP
DATA
DATA
Channel Flag (Right Channel)
FIGURE 10. PCM1750/DF1750 To DSP IC Timing Diagram.
®
17
PCM1750
FIGURE 11. PCM1750/DF1750 to DSP IC Schematic.
®
PCM1750
18
+5V
+5V
LRCK
BCK
WDCK
LRPOL
OBPOL
LRCK
BCK
WDCK
DOUT
DF1750
LRPOL
OBPOL
DOUT
DF1750
1
1
U1
74HC04
U1
74HC04
2
2
3
2
3
2
D
D
Q
Q
1
+5V
+5V
U2
74HC74
5
C Q 6
CL
PR
4
1
C Q 6
CL
PR
4
U2
74HC74
5
13
C Q 8
CL
+5V
11
13
C Q 8
CL
+5V
10 U2
74HC74
PR
12
9
D
Q
11
10 U2
74HC74
PR
12
9
D
Q
3
2
3
2
D
D
Q
5
Q
5
1
C Q 6
CL
PR
4
1
C Q 6
CL
PR
4
+5V
+5V
U3
74HC74
+5V
+5V
U3
74HC74
+5V
13
C Q 8
CL
+5V
+5V
11
13
C Q 8
CL
+5V
10 U3
74HC74
PR
12
9
D
Q
11
10 U3
74HC74
PR
12
9
D
Q
U4
4 74HC08
6
5
U4
1 74HC08
3
2
U4
4 74HC08
6
5
U4
1 74HC08
3
2
U5
1 74HC32
3
2
U5
1 74HC32
3
2
Bit
Clock
Data In
Frame
Sync
TMS32020/C20/C25
DSP56001
ADSP-2102/2105
ICK
Data In
ILD
DSP16/DSP32C