OPA734, OPA2734 OPA735, OPA2735 SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 0.05µV/°C max, SINGLE-SUPPLY CMOS OPERATIONAL AMPLIFIERS Zer∅-Drift Series FEATURES D D D D D D D D DESCRIPTION The OPA734 and OPA735 series of CMOS operational amplifiers use auto-zeroing techniques to simultaneously provide low offset voltage (5µV max) and near-zero drift over time and temperature. These miniature, high-precision, low quiescent current amplifiers offer high input impedance and rail-to-rail output swing within 50mV of the rails. Either single or bipolar supplies can be used in the range of +2.7V to +12V (±1.35V to ±6V). They are optimized for low-voltage, single-supply operation. LOW OFFSET VOLTAGE: 5µV (max) ZERO DRIFT: 0.05µV/°C max QUIESCENT CURRENT: 750µA (max) SINGLE-SUPPLY OPERATION LOW BIAS CURRENT: 200pA (max) SHUTDOWN MicroSIZE PACKAGES WIDE SUPPLY RANGE: 2.7V to 12V The OPA734 family includes a shutdown mode. Under logic control, the amplifiers can be switched from normal operation to a standby current that is 9µA (max) and the output placed in a high-impedance state. APPLICATIONS D D D D D D TRANSDUCER APPLICATIONS TEMPERATURE MEASUREMENTS ELECTRONIC SCALES MEDICAL INSTRUMENTATION BATTERY-POWERED INSTRUMENTS HANDHELD TEST EQUIPMENT The single version is available in the MicroSIZE SOT23-5 (SOT23-6 for shutdown version) and the SO-8 packages. The dual version is available in the MSOP-8 and SO-8 packages (MSOP-10 only for the shutdown version). All versions are specified for operation from −40°C to +85°C. VREF = 15V G=1+2 REF102 R3 RG 10V R1 1kΩ C1 1nF 1/2 OP A2735 R3 10kΩ C4 1nF C2 10nF RG C4 1nF R3 10kΩ R2 1kΩ 1/2 OP A2735 C3 1nF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2003-2005, Texas Instruments Incorporated ! ! www.ti.com "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.2V Signal Input Terminals, Voltage(2) . . . . . . . . . . . (V−) − 0.5V to (V+) + 0.5V Current(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C ESD Rating (Human Body Model), OPA734 . . . . . . . . . . . . . . . . . . . . 1000V ESD Rating (Human Body Model), OPA735, OPA2734, OPA2735 . . . . 2000V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. (3) Short-circuit to ground, one amplifier per package. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY SOT23-6 ″ SO-8 ″ MSOP-10 ″ DBV ″ D ″ DGS ″ −40°C to +85°C ″ −40°C to +85°C ″ −40°C to +85°C ″ NSB ″ OPA734A ″ BGO ″ OPA734AIDBVT OPA734AIDBVR OPA734AID OPA734AIDR OPA2734AIDGST OPA2734AIDGSR Tape and Reel, 250 Tape and Reel, 3000 Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 SOT23-5 ″ SO-8 ″ SO-8 ″ MSOP-8 ″ DBV ″ D ″ D ″ DGK ″ −40°C to +85°C ″ −40°C to +85°C ″ −40°C to +85°C ″ −40°C to +85°C ″ NSC ″ OPA735A ″ OPA2735A ″ BGN ″ OPA735AIDBVT OPA735AIDBVR OPA735AID OPA735AIDR OPA2735AID OPA2735AIDR OPA2735AIDGKT OPA2735AIDGKR Tape and Reel, 250 Tape and Reel, 3000 Rails, 100 Tape and Reel, 2500 Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 Shutdown Version OPA734 ″ OPA734 ″ OPA2734 ″ Non-Shutdown Version OPA735 ″ OPA735 ″ OPA2735 ″ OPA2735 ″ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS: VS = ±5V (VS = +10V) Boldface limits apply over the specified temperature range, TA = −40°C to +85°C. At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. OPA734, OPA2734, OPA735, OPA2735 PARAMETER OFFSET VOLTAGE Input Offset Voltage vs Temperature vs Power Supply Long-Term Stability Channel Separation, dc INPUT BIAS CURRENT Input Bias Current over Temperature Input Offset Current NOISE Input Voltage Noise, f = 0.01Hz to 1Hz Input Voltage Noise, f = 0.1Hz to 10Hz Input Voltage Noise Density, f = 1kHz Input Current Noise Density, f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio CONDITIONS VOS dVOS/dT PSRR MIN VS = 2.7V to 12V, VCM = 0V IB VCM = VS/2 IOS VCM = VS/2 UNIT 1 0.01 0.2 Note (1) 0.1 5 0.05 1.8 µV µV/°C µV/V µV/V (V−) − 0.1V < VCM < (V+) − 1.5V (V−) − 0.1 115 OPEN-LOOP GAIN Open-Loop Voltage Gain AOL (V−) + 100mV < VO < (V+) − 100mV FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate GBW SR G = +1 115 RL = 10kΩ f = 1MHz, IO = 0 CLOAD ENABLE/SHUTDOWN tOFF tON(2) VL (amplifier is shutdown) VH (amplifier is active) IQSD (per amplifier) Input Bias Current of Enable Pin 130 (V+) − 1.5 V dB 2 10 pF pF 130 dB 1.6 1.5 MHz V/µs 20 50 ±20 125 See Typical Characteristics ISC pA pA pA µVPP µVPP nV/√Hz fA/√Hz 0.8 2.5 135 40 INPUT CAPACITANCE Differential Common-Mode OUTPUT Voltage Output Swing from Rail Short-Circuit Current Open-Loop Output Impedance Capacitive Load Drive MAX ±100 ±200 See Typical Characteristics ±200 ±300 en en en in VCM CMRR TYP 1.5 150 V− (V−) + 2 4 3 (V−) + 0.8 V+ 9 mV mA Ω µs µs V V µA µA POWER SUPPLY Operating Voltage Range VS Quiescent Current (per amplifier) IQ TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SOT23-5, SOT23-6 MSOP-8, MSOP-10, SO-8 2.7 to 12 (±1.35 to ±6) 0.6 IO = 0 −40 −40 −65 qJA 200 150 V 0.75 mA +85 +150 +150 °C °C °C °C/W °C/W °C/W (1) 300-hour life test at 150°C demonstrated randomly distributed variation in the range of measurement limits—approximately 1µV. (2) Device requires one complete auto-zero cycle to return to V OS accuracy. 3 "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 PIN CONFIGURATIONS Out 1 V− 2 +IN 3 OPA2735 OPA735 OPA735 5 4 V+ −IN 1 8 V+ V+ −IN A 2 7 OUT B 6 OUT +IN A 3 6 −IN B 5 NC(1) V− 4 5 +IN B NC(1) 1 8 NC(1) −IN 2 7 +IN 3 V− 4 OUT A SOT23−5 SO−8, MSOP−8 SO−8 1 V− +IN NSB Out OPA2734 OPA734 OPA734 6 V+ 2 5 Enable 3 4 −IN NC(1) 1 8 Enable −IN 2 7 V+ +IN 3 6 OUT V− 4 5 NC(1) SOT23−6(2) OUT A 10 V+ −IN A 2 9 OUT B +IN A 3 8 −IN B V− 4 7 +IN B Enable A 5 6 Enable B SO−8 (1) NC = No Connection (2) Pin 1 of the SOT23-6 is determined by orienting the package marking as shown in the diagram. 4 1 MSOP−10 "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±5V (same as +10V). OUTPUT VOLTAGE DRIFT PRODUCTION DISTRIBUTION OUTPUT VOLTAGE PRODUCTION DISTRIBUTION Offset Voltage (µV) 0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 −5.0 −4.5 −4.0 −3.5 −3.0 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 Population Population Absolute Value; Centered Around Zero Offset Voltage Drift (µV/_ C) OUTPUT VOLTAGE SWING TO RAIL vs OUTPUT CURRENT INPUT BIAS CURRENT vs TEMPERATURE 6 1000 4 −1000 Input Bias Current (pA) VOUT Voltage Swing (V) 0 2 +85_ C +25_C 0 −40_C −2 −IB −2000 −3000 −4000 −5000 10 Representative Units −6000 −7000 −4 −8000 −6 −10000 −9000 0 5 10 15 20 25 30 +IB VCM = V− −50 35 −25 0 VCM = VS/2 600 +I B 400 200 0 −200 −I B −400 75 85 100 125 800 Supply Current (µA) Input Bias Current (pA) 800 50 SUPPLY CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs TEMPERATURE 1000 25 Temperature (_C) Output Current (mA) 10 Representative Units −600 600 ±6V 400 ±1.35V 200 −800 −1000 0 −50 −25 0 25 50 Temperature (_ C) 75 85 100 125 −50 −25 0 25 50 75 100 125 Temperature (_ C) 5 "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±5V (same as +10V). 180 160 160 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 0 Output Voltage (2V/div) LARGE−SIGNAL RESPONSE 180 Phase Margin (_) AOL (dB) OPEN−LOOP GAIN AND PHASE MARGIN vs FREQUENCY −20 −20 −40 0.1 1 10 100 1k 10k 100k 1M −40 10M Time (5µs/div) Frequency (Hz) SMALL−SIGNAL RESPONSE POSITIVE OVERVOLTAGE RECOVERY Voltage (2V/div) Output Voltage (10mV/div) Output 10 kΩ 1 0kΩ +5V OPA735 Input − 5V Time (250ns/div) Time (2.5µs/div) COMMON−MODE REJECTION RATIO vs FREQUENCY NEGATIVE OVERVOLTAGE RECOVERY 140 1 0kΩ 120 10kΩ +5 V Input − 5V Output CMRR (dB) Voltage (2V/div) 100 OPA 73 5 80 60 40 20 0 Time (2.5µs/div) 1 10 100 1k 10k Frequency (Hz) 6 100k 1M 10M "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±5V (same as +10V). VOLTAGE NOISE vs FREQUENCY POWER−SUPPLY REJECTION RATIO vs FREQUENCY 1k 160 140 +PSRR Noise (nV/√Hz) 100 80 −PSRR 60 100 40 20 10 0 1 10 100 1k 10k 100k 1 1M 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) SAMPLING FREQUENCY vs TEMPERATURE 0.1Hz TO 10Hz NOISE 20.0 Sampling Frequency (kHz) 19.5 1µV/div 19.0 VS = 12V 18.5 18.0 17.5 17.0 VS = 2.7V 16.5 16.0 −50 1s/div −25 0 25 50 75 100 125 150 Temperature (_C) SMALL−SIGNAL OVERSHOOT vs CAPACITIVE LOAD 50 40 Overshoot (%) PSRR (dB) 120 30 20 10 0 1 10 100 1000 Capacitance (pF) 7 "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 APPLICATIONS INFORMATION The OPA734 and OPA735 series of op amps are unity-gain stable and free from unexpected output phase reversal. They use auto-zeroing techniques to provide low offset voltage and demonstrate very low drift over time and temperature. Good layout practice mandates the use of a 0.1µF capacitor placed closely across the supply pins. For lowest offset voltage and precision performance, circuit layout and mechanical conditions should be optimized. Avoid temperature gradients that create thermoelectric (Seebeck) effects in thermocouple junctions formed from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring that they are equal on both input terminals: 1. Use low thermoelectric-coefficient connections (avoid dissimilar metals). 2. Thermally isolate components from power supplies or other heat sources. 3. Shield op amp and input circuitry from air currents such as cooling fans. Following these guidelines will reduce the likelihood of junctions being at different temperatures, which can cause thermoelectric voltages of 0.1µV/°C or higher, depending on the materials used. The logic input is a CMOS input. Separate logic inputs are provided for each op amp on the dual version. For battery-operated applications, this feature can be used to greatly reduce the average current and extend battery life. The enable time is 150µs, which includes one full auto-zero cycle required by the amplifier to return to VOS accuracy. Prior to returning to full accuracy, the amplifier may function properly, but with unspecified offset voltage. Disable time is 1.5µs. When disabled, the output assumes a high-impedance state. The disable state allows the OPA734 to be operated as a gated amplifier, or to have the output multiplexed onto a common analog output bus. INPUT VOLTAGE The input common-mode range extends from (V−) − 0.1V to (V+) − 1.5V. For normal operation, the inputs must be limited to this range. The common-mode rejection ratio is only valid within the specified input common-mode range. A lower supply voltage results in lower input commonmode range; therefore, attention to these values must be given when selecting the input bias voltage. For example, when operating on a single 3V power supply, commonmode range is from 0.1V below ground to half the power-supply voltage. Normally, input bias current is approximately 100pA; however, input voltages exceeding the power supplies can cause excessive current to flow in or out of the input pins. Momentary voltages greater than the power supply can be tolerated if the input current is limited to 10mA. This is easily accomplished with an input resistor, as shown in Figure 1. OPERATING VOLTAGE The OPA734 and OPA735 op amp family operates with a power-supply range of +2.7V to +12V (±1.35V to ±6V). Supply voltages higher than +13.2V (absolute maximum) can permanently damage the amplifier. Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section of this data sheet. OPA734 ENABLE FUNCTION The enable/shutdown digital input is referenced to the V− supply voltage of the op amp. A logic HIGH enables the op amp. A valid logic HIGH is defined as > (V−) + 2V. The valid logic HIGH signal can be up to the positive supply, independent of the negative power supply voltage. A valid logic LOW is defined as < 0.8V above the V− supply pin. If dual or split power supplies are used, be sure that logic input signals are properly referred to the negative supply voltage. The Enable pin is connected to internal pull-up circuitry and will enable the device if this pin is left open circuit. 8 Current−limited resistor required if input voltage exceeds supply rails by ≥ 0.5V. +5V IOVERLOAD 10mA max 50Ω OPA735 VOUT VIN Figure 1. Input Current Protection INTERNAL OFFSET CORRECTION The OPA734 and OPA735 series of op amps use an auto-zero topology with a time-continuous 1.6MHz op amp in the signal path. This amplifier is zero-corrected every 100µs using a proprietary technique. Upon power-up, the amplifier requires one full auto-zero cycle of approximately 100µs in addition to the start-up time for the bias circuitry to achieve specified VOS accuracy. Prior to this time, the amplifier may function properly but with unspecified offset voltage. "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 Low-gain (< 20) operation demands that the auto-zero circuitry correct for common-mode rejection errors of the main amplifier. Because these errors can be larger than 0.1% of a full-scale input step change, one calibration cycle (100µs) can be required to achieve full accuracy. The term clock feedthrough describes the presence of the clock frequency in the output spectrum. In auto-zeroed op amps, clock feedthrough may result from the settling of the internal sampling capacitor, or from the small amount of charge injection that occurs during the sample-and-hold of the op amp offset voltage. Feedthrough can be minimized by keeping the source impedance relatively low (< 1kΩ) and matching the source impedance on both input terminals. If the source resistance is high (> 1kΩ) feedthrough can generally be reduced with a capacitor of 1nF or greater in parallel with the source or feedback resistors. See the circuit application examples. 1nF VEX R1 +10V R R R R VOUT OPA734 R1 VREF 1nF Figure 2. Single Op Amp Bridge Amplifier Circuit LAYOUT GUIDELINES Attention to good layout practices is always recommended. Keep traces short. When possible, use a PCB ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1µF capacitor closely across the supply pins. These guidelines should be applied throughout the analog circuit to improve performance and provide benefits such as reducing the electromagnetic-interference (EMI) susceptibility. VREF = 15V 2 G=1+2 REF102 10V 6 4 R1 1kΩ R R R R R3 RG C1(1) 1nF 1 /2 OP A 2 7 35 R3 10kΩ C4 1nF C2(1) R 10nF G C4 1nF R3 10kΩ R2 1kΩ 1 /2 OP A 2 7 35 C3(1) 1nF NOTE: (1) Place close to input pins. Figure 3. Differential Output Bridge Amplifier 9 "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 C2 = 1nF R4 = 10kΩ +5V R1 RF 300Ω VIN ADS8342 ADS8325 ADS1100 OPA735 R2 CF 500pF 0.1V to 4.9V VREF C1 1nF R3 10kΩ Optional filter for use with SAR−type converters operating at sampling rates of 50kHz and below. VIN VREF R1 R2 ±10V ±5V 0V to 10V 0V to 5V 5V 5V 5V 5V 42.2kΩ 20.8kΩ 20.8kΩ 10.5kΩ 14.7kΩ 19.6kΩ 5.11kΩ 10kΩ Figure 4. Driving ADC R4 10kΩ C4 1µF C3 1µF R9 10kΩ R5 1.5MΩ +5V R2 1kΩ +5V C2 100nF OPA735 R7 10kΩ −5V −5V REF1112 R1 22kΩ −5V TPS434 Thermopile 1/2 OPA2703 R3 6.8kΩ R6 11kΩ +5V 1/2 OPA2703 R8 10kΩ −5V NOTE: The TPS434, by Perkin Elmer Optoelectronics, is a thermopile detector with integrated thermistor for cold−junction reference. Figure 5. Thermopile Non-Contact Surface Temperature Measurement 10 VOUT "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 +5V R1 536kΩ R1 536kΩ C3 10nF −5V R3 268kΩ C1 5nF VOUT OPA735 C2 5nF fn = R = R 1 = R2 = 2R3 1 ; where C = C 1 = C2 = C3/2 2 π RC (f n = 60Hz for values shown) Figure 6. Twin-T Notch Filter C2 68.0nF R1 10.6kΩ R2 2.64kΩ 1/2 R3 20.8kΩ OP A2 735 1/2 VIN C3 6.80nF C1 15.0nF O PA2735 VOUT Cutoff frequency = 2kHz for values shown. NOTE: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The program can be used to easily determine component values for other cutoff frequencies or filter types. Figure 7. High DC Accuracy, 3-Pole Low-Pass Filter C1 1nF R1 = 10 kΩ R3 10 kΩ R2 10 kΩ 1/2 OP A27 35 VOUT VIN C1 1nF D1 NOTE: Dynamic range of the circuit is not reduced by the diode voltage drop since the diode is not in the signal path. Application Bulletin Precision Absolute Value Circuits (SBOA068) is available at www.ti.com and provides further information about rectifier circuits. 1/2 OP A27 35 Figure 8. Precision Full-Wave Rectifier with Full Dynamic Range 11 "#$% &"#$ "#'% &"#' www.ti.com SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 1nF 1kΩ 49kΩ Enable A G = 50 OPA734 VIN A VOUT Enable B G=1 OPA734 VIN B Enable inputs are CMOS logic compatible. Figure 9. High-Precision 2-Input MUX for Programmable Gain +VS 2.7V to 12V Load OPA735 Shunt RS 10mΩ VOUT = 1V/A (referred to ground) IL R1 100Ω R2 10kΩ C1 1nF Figure 10. Low-Side Power-Supply Current Sensing 12 PACKAGE OPTION ADDENDUM www.ti.com 8-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA2734AIDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2734AIDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2734AIDGST ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2734AIDGSTG4 ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AID ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AIDG4 ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AIDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AIDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AIDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AIDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA2735AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AID ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AIDBVR ACTIVE SOT-23 DBV 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AIDBVRG4 ACTIVE SOT-23 DBV 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AIDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AIDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AIDG4 ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA734AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA735AID ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA735AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA735AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA735AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA735AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 8-Feb-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA735AIDG4 ACTIVE SOIC D 8 100 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA735AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA735AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 17-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OPA2734AIDGST DGS 10 MLA 330 12 5.3 3.4 1.4 8 12 PKGORN T1TR-MS P OPA734AIDBVR DBV 6 MLA 180 8 6.83 7.42 1.88 8 12 PKGORN T3TR-MS P OPA734AIDBVT DBV 6 MLA 180 8 6.83 7.42 1.88 8 12 PKGORN T3TR-MS P OPA735AIDBVR DBV 5 MLA 180 8 6.83 7.42 1.88 8 12 PKGORN T3TR-MS P OPA735AIDBVT DBV 5 MLA 180 8 6.83 7.42 1.88 8 12 PKGORN T3TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) OPA2734AIDGST DGS 10 MLA 346.0 346.0 61.0 OPA734AIDBVR DBV 6 MLA 0.0 0.0 0.0 OPA734AIDBVT DBV 6 MLA 190.0 212.7 31.75 OPA735AIDBVR DBV 5 MLA 190.0 212.7 31.75 OPA735AIDBVT DBV 5 MLA 190.0 212.7 31.75 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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