TSC2046E SBAS417 − JUNE 2007 Low Voltage I/O TOUCH SCREEN CONTROLLER FEATURES D D D D D D D D D D D DESCRIPTION Same Pinout as ADS7846 2.2V to 5.25V Operation 1.5V to 5.25V Digital I/O Internal 2.5V Reference Direct Battery Measurement (0V to 6V) On-Chip Temperature Measurement Touch-Pressure Measurement QSPI and SPI 3-Wire Interface Auto Power-Down Exceeds IEC 61000-4-2 ESD Requirements − +15kV Contact Discharge − No External Components Needed Available In TSSOP-16, QFN-16, and VFBGA-48 Packages The TSC2046E is the next-generation version of the ADS7846 4-wire touch screen controller, supporting a low-voltage I/O interface from 1.5V to 5.25V. The TSC2046E is 100% pin-compatible with the existing ADS7846, and drops into the same socket. This design allows for an easy upgrade of current applications to the new version. The TSC2046E also has an on-chip 2.5V reference that can be used for the auxiliary input, battery monitor, and temperature measurement modes. The reference can also be powered down when not used to conserve power. The internal reference operates down to a supply voltage of 2.7V, while monitoring the battery voltage from 0V to 6V. The low-power consumption of < 0.75mW typ at 2.7V (reference off), high-speed (up to 125kHz sample rate), and on-chip drivers make the TSC2046E an ideal choice for battery-operated systems such as personal digital assistants (PDAs) with resistive touch screens, pagers, cellular phones, and other portable equipment. The TSC2046E is available in TSSOP-16, QFN-16, and VFBGA-48 packages and is specified over the –40°C to +85°C temperature range. APPLICATIONS D D D D D D Personal Digital Assistants Portable Instruments Point-of-Sale Terminals Pagers Touch Screen Monitors Cellular Phones US Patent No. 6246394 PENIRQ P e n D e tec t +VCC X+ T e m pe ra ture X− SAR Se n sor IOVDD Y+ DOUT TSC2046E Y− BUSY Comparator 6−Channel MUX VBAT CDAC Serial Data In/Out CS DCLK Battery Monitor DIN AUX Internal 2.5V Reference VRE F Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola Inc. Microwire is a trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. Copyright 2007, Texas Instruments Incorporated ! ! www.ti.com "#$%&' www.ti.com SBAS417 − JUNE 2007 ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VCC and IOVDD to GND . . . . . . . . . . . . . . . . . . . . . −0.3V to +6V Analog Inputs to GND . . . . . . . . . . . . . . . . . −0.3V to +VCC + 0.3V Digital Inputs to GND . . . . . . . . . . . . . . . . . −0.3V to IOVDD + 0.3V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Temperature Range . . . . . . . . . . . . . . . . −40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . −65°C to +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C IEC Contact Discharge (X+, X−, Y+, Y−)(2) . . . . . . . . . . . . . . . ±15kV (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Test method based on IEC standard 61000−4−2. Contact Texas Instruments for test details. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT TSC2046E (1) 2 NOMINAL PENIRQ PULLUP RESISTOR VALUES 50kΩ MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ±2 PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING TSSOP-16 PW −40°C to +85°C TSC2046EI 4x4, 0.8mm Thin QFN-16 RGV −40°C to +85°C TSC2046E 4x4 VFBGA-48 ZQC −40°C to +85°C BC2046E ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TSC2046EIPW Rails, 100 TSC2046EIPWR Tape and Reel, 2500 TSC2046EIRGVT Tape and Reel, 250 TSC2046EIRGVR Tape and Reel, 2500 TSC2046EIZQCR Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at www.ti.com. "#$%&' www.ti.com SBAS417 − JUNE 2007 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, and +VCC must be • IOVDD, unless otherwise noted. PARAMETER ANALOG INPUT Full-Scale Input Span Absolute Input Range CONDITION MIN Positive Input−Negative Input Positive Input Negative Input 0 −0.2 −0.2 Capacitance Leakage Current SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Offset Error Gain Error Noise Power-Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Channel-to-Channel Isolation SWITCH DRIVERS On-Resistance Y+, X+ Y−, X− Drive Current(2) BATTERY MONITOR Input Voltage Range Input Impedance Sampling Battery Battery Monitor Off Accuracy TEMPERATURE MEASUREMENT Temperature Range Resolution Accuracy (1) (2) (3) (4) (5) (6) (7) MAX UNITS VREF +VCC + 0.2 +0.2 V V V pF µA 25 0.1 12 11 ±2 ±6 ±4 External VREF Including Internal VREF 70 70 12 3 125 500 30 100 100 VIN = 2.5VPP at 50kHz 5 6 Duration 100ms REFERENCE OUTPUT Internal Reference Voltage Internal Reference Drift Quiescent Current REFERENCE INPUT Range Input Impedance TSC2046E TYP 50 2.45 2.50 15 500 Ω Ω mA +VCC 1 V GΩ 250 Ω 6.0 V +2 +3 kΩ GΩ % % 10 1 −2 −3 −40 Differential Method(3) TEMP0(4) Differential Method(3) TEMP0(4) CLK Cycles CLK Cycles kHz ns ns ps dB V ppm/°C µA 0.5 VBAT = 0.5V to 5.5V, External VREF = 2.5V VBAT = 0.5V to 5.5V, Internal Reference LSB LSB µVrms dB 2.55 1.0 SER/DFR = 0, PD1 = 0 Internal Reference Off Internal Reference On Bits Bits LSB(1) +85 1.6 0.3 ±2 ±3 °C °C °C °C °C LSB means Least Significant Bit. With VREF = +2.5V, 1 LSB is 610µV. Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. Difference between TEMP0 and TEMP1 measurement, no calibration necessary. Temperature drift is −2.1mV/°C. TSC2046E operates down to 2.2V. IOVDD must be − (+VCC). Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0. 3 "#$%&' www.ti.com SBAS417 − JUNE 2007 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (continued) At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, and +VCC must be • IOVDD, unless otherwise noted. PARAMETER DIGITAL INPUT/OUTPUT Logic Family Capacitance VIH VIL VOH VOL CONDITION All Digital Control Input Pins | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = −250µA IOL = 250µA MIN CMOS 5 IOVDD • 0.7 −0.3 IOVDD • 0.8 IOVDD(6) Quiescent Current(7) Power Dissipation TEMPERATURE RANGE Specified Performance (1) (2) (3) (4) (5) (6) (7) 4 MAX UNITS 15 IOVDD + 0.3 0.3 • IOVDD pF V V V V 0.4 Straight Binary Data Format POWER-SUPPLY REQUIREMENTS +VCC(5) TSC2046E TYP Specified Performance Operating Range 2.7 2.2 1.5 Internal Reference Off Internal Reference On fSAMPLE = 12.5kHz Power-Down Mode with CS = DCLK = DIN = IOVDD +VCC = +2.7V 280 780 220 −40 LSB means Least Significant Bit. With VREF = +2.5V, 1 LSB is 610µV. Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. Difference between TEMP0 and TEMP1 measurement, no calibration necessary. Temperature drift is −2.1mV/°C. TSC2046E operates down to 2.2V. IOVDD must be − (+VCC). Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0. 3.6 5.25 +VCC 650 3 V V V µA µA µA µA 1.8 mW +85 °C "#$%&' www.ti.com SBAS417 − JUNE 2007 PIN CONFIGURATION Top View Top View TSSOP VFBGA DCLK 1 +VCC 1 16 DCLK X+ 2 15 CS Y+ 3 14 DIN X− 4 Y− 5 GND 13 TSC2046E A +VCC 12 DOUT 6 11 PENIRQ VBAT 7 10 IOVDD AUX 8 3 BUSY DOUT 4 5 6 7 NC NC B NC C NC D NC E NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC IOVDD X+ VREF Y+ AUX F 9 2 DIN PENIRQ +VCC BUSY CS NC NC VREF G NC NC GND GND VBAT 13 VREF 8 4 X− DCLK 7 3 Y+ CS TSC2046E 6 2 X+ DIN 5 1 Y− QFN +VCC BUSY 14 IOVDD 16 DOUT Top View 15 PENIRQ X− 12 AUX 11 VBAT 10 GND 9 Y− PIN DESCRIPTION TSSOP PIN # VFBGA PIN # QFN PIN # NAME DESCRIPTION 1 B1 and C1 5 Power Supply 2 D1 6 +VCC X+ 3 E1 7 Y+ Y+ Position Input 4 G2 8 X− X− Position Input 5 G3 9 Y− Y− Position Input 6 G4 and G5 10 GND Ground 7 G6 11 Battery Monitor Input 8 E7 12 VBAT AUX 9 D7 13 10 C7 14 VREF IOVDD 11 B7 15 PENIRQ 12 A6 16 DOUT Serial Data Output. Data are shifted on the falling edge of DCLK. This output is high impedance when CS is high. 13 A5 1 BUSY Busy Output. This output is high impedance when CS is high. 14 A4 2 DIN Serial Data Input. If CS is low, data sre latched on the rising edge of DCLK. 15 A3 3 CS Chip Select Input. Controls conversion timing and enables the serial input/output register. CS high = power-down mode (ADC only). 16 A2 4 DCLK X+ Position Input Auxiliary Input to ADC Voltage Reference Input/Output Digital I/O Power Supply Pen Interrupt External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. 5 "#$%&' www.ti.com SBAS417 − JUNE 2007 TYPICAL CHARACTERISTICS At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. +VCC SUPPLY CURRENT vs TEMPERATURE IOVDD SUPPLY CURRENT vs TEMPERATURE 30 350 IOVDD Supply Current (µA) +VCC Supply Current (µA) 400 300 250 200 150 100 −40 −20 0 20 40 60 80 25 20 15 10 5 −40 100 −20 Temperature (°C) 0 20 40 60 80 100 4.5 5.0 4.5 5.0 Temperature (°C) +VCC SUPPLY CURRENT vs +VCC POWER−DOWN SUPPLY CURRENT vs TEMPERATURE 450 140 400 +VCC Supply Current (µA) Supply Current (nA) 120 100 80 60 40 fSAMPLE = 125kHz 350 300 250 200 f SAMPLE = 12.5kHz 150 100 −40 −20 0 20 40 60 80 2.0 100 2.5 3.0 1M +VCC ≥ IOVDD 50 Sample Rate (Hz) IOVDD Supply Current (µA) 4.0 MAXIMUM SAMPLE RATE vs +VCC IOVDD SUPPLY CURRENT vs IOVDD 60 40 fSAMPLE = 125kHz 30 20 10 100k 10k fSAMPLE = 12.5kHz 0 1k 1.0 1.5 2.0 2.5 3.0 IOVDD (V) 6 3.5 +VCC (V) Temperature (°C) 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 +VCC (V) 4.0 "#$%&' www.ti.com SBAS417 − JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. CHANGE IN OFFSET vs TEMPERATURE 0.10 0.4 Delta from +25°C (LSB) 0.6 0.05 0 −0.05 −0.10 −0.15 −40 −20 0 20 40 60 80 0.2 0 −0.2 −0.4 −0.6 −40 100 −20 0 Temperature (°C) 40 60 80 100 REFERENCE CURRENT vs TEMPERATURE 14 18 12 16 Reference Current (µA) Reference Current (µA) 20 Temperature (°C) REFERENCE CURRENT vs SAMPLE RATE 10 8 6 4 14 12 10 8 2 0 0 25 50 75 100 6 −40 125 −20 0 20 40 60 80 100 Temperature (°C) Sample Rate (kHz) SWITCH ON− RESISTANCE vs +VCC (X+, Y+: +VCC to Pin; X−, Y−: Pin to GND) SWITCH ON−RESISTANCE vs TEMPERATURE (X+, Y+: +VCC to Pin; X−, Y−: Pin to GND) 8 8 Y− 7 7 Y− 6 6 5 RON (Ω) RON (Ω) Delta from +25°C (LSB) CHANGE IN GAIN vs TEMPERATURE 0.15 X− X+, Y+ 5 X− 4 3 X+, Y+ 4 2 1 3 2.0 2.5 3.0 3.5 +VCC (V) 4.0 4.5 5.0 −40 −20 0 20 40 60 80 100 Temperature (°C) 7 "#$%&' www.ti.com SBAS417 − JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. INTERNAL VREF vs TEMPERATURE MAXIMUM SAMPLING RATE vs RIN 2.5080 2.5075 INL: RIN = 500Ω INL: RIN = 2kΩ DNL: RIN = 500Ω DNL: RIN = 2kΩ 1.8 1.6 1.4 2.5070 Internal VREF (V) Max Absolute Delta Error from RIN = 0 (LSB) 2.0 1.2 1.0 0.8 0.6 2.5065 2.5060 3.5055 2.5050 2.5045 2.5040 0.4 2.5035 0.2 2.5030 20 40 60 80 100 120 140 Sampling Rate (kHz) 160 180 −40 −35 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 0 200 Temperature (°C) INTERNAL VREF vs +VCC INTERNAL VREF vs TURN− ON TIME 2.510 100 No Cap (42µs) 12-Bit Settling 80 2.500 Internal VREF (%) Internal VREF (V) 2.505 2.495 2.490 1µF Cap (124µs) 12-Bit Settling 60 40 20 2.485 2.480 0 2.5 3.0 3.5 4.0 4.5 5.0 0 +VCC (V) 200 400 600 800 1000 1200 1400 Turn-On Time (µs) TEMP DIODE VOLTAGE vs TEMPERATURE TEMP0 DIODE VOLTAGE vs +VCC 850 604 750 90.1mV TEMP1 700 650 600 550 TEMP0 135.1mV 500 450 602 600 598 596 −40 −35 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 594 Temperature (°C) 8 TEMP0 Diode Voltage (mV) TEMP Diode Voltage (mV) 800 2.7 3.0 +VCC (V) 3.3 "#$%&' www.ti.com SBAS417 − JUNE 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. TEMP1 DIODE VOLTAGE vs +VCC TEMP1 Diode Voltage (mV) 720 718 716 714 712 710 2.7 3.0 3.3 +VCC (V) THEORY OF OPERATION The TSC2046E is a classic successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on capacitive redistribution, which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µm CMOS process. The basic operation of the TSC2046E is shown in Figure 1. The device features an internal 2.5V reference and uses an external clock. Operation is maintained from a single supply of 2.7V to 5.25V. The internal reference can be overdriven with an external, low-impedance source between 1V and +VCC. The value of the reference voltage directly sets the input range of the converter. The analog input (X-, Y-, and Z-Position coordinates, auxiliary input, battery voltage, and chip temperature) to the converter is provided via a multiplexer. A unique configuration of low on-resistance touch panel driver switches allows an unselected ADC input channel to provide power and the accompanying pin to provide ground for an external device, such as a touch screen. By maintaining a differential input to the converter and a differential reference architecture, it is possible to negate the error from each touch panel driver switch’s on-resistance (if this is a source of error for the particular measurement). +2.7V to +5V 1µF + to 10µF (Optional) Touch Screen 0.1µF TSC2046E B1 +VCC DCLK A2 C1 +VCC CS A3 Serial/Conversion Clock Chip Select Serial Data In D1 X+ DIN A4 E1 Y+ BUSY A5 Converter Status G2 X− DOUT A6 Serial Data Out G3 Y− PENIRQ B7 Pen Interrupt To Battery Auxiliary Input Voltage Regulator G6 VBAT IOVDD C7 E7 AUX VREF D7 GND G4 G5 GND NOTE: VFBGA package and pin names shown. Figure 1. Basic Operation of the TSC2046E 9 "#$%&' www.ti.com SBAS417 − JUNE 2007 ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (shown in Figure 2) is captured on the internal capacitor array. The input current into the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor is fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. Figure 2 shows a block diagram of the input multiplexer on the TSC2046E, the differential input of the ADC, and the differential reference of the converter. Table 1 and Table 2 show the relationship between the A2, A1, A0, and SER/DFR control bits and the configuration of the TSC2046E. The control bits are provided serially via the DIN pin—see the Digital Interface section of this data sheet for more details. +VCC PENIRQ IOVDD Level Shifter TEMP1 50kΩ or 90kΩ VREF TEMP0 Logic SER/DFR (Shown Low) A2− A0 (Shown 001B) X+ X− Ref On/Off Y+ +IN Y− +REF ADC −IN 2.5V Reference −REF 7.5kΩ VBAT 2.5kΩ Battery On AUX GND Figure 2. Simplified Diagram of Analog Input A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 VBAT AUXIN TEMP Y− X+ Y+ +IN (TEMP0) Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS Off +IN Measure Off +IN +IN Measure +IN Measure +IN Measure +IN +IN (TEMP1) Y-DRIVERS Off On Off Off X−, On Y+, On X−, On Y+, On On Off Off Off Off Off Table 1. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high) A2 A1 A0 +REF −REF 0 0 1 Y+ Y− Y− +IN X+ 0 1 1 Y+ X− +IN 1 0 0 Y+ X− 1 0 1 X+ X− Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION Measure Y+, Y− Measure +IN Y+, X− Measure +IN Measure Table 2. Input Configuration (DIN), Differential Reference Mode (SER/DFR low) 10 DRIVERS Y+, X− X+, X− "#$%&' www.ti.com SBAS417 − JUNE 2007 INTERNAL REFERENCE The TSC2046E has an internal 2.5V voltage reference that can be turned on or off with the control bit, PD1 (see Table 5 and Figure 3). Typically, the internal reference voltage is only used in the single-ended mode for battery monitoring, temperature measurement, and for using the auxiliary input. Optimal touch screen performance is achieved when using the differential mode. The internal reference voltage of the TSC2046E must be commanded to be off to maintain compatibility with the ADS7843. Therefore, after power-up, a write of PD1 = 0 is required to ensure the reference is off (see the Typical Characteristics for power-up time of the reference from power-down). Reference Power−Down Band Gap There is also a critical item regarding the reference when making measurements while the switch drivers are ON. For this discussion, it is useful to consider the basic operation of the TSC2046E (see Figure 1). This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y-Position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and Y– drivers, and digitizing the voltage on X+ (Figure 4 shows a block diagram). For this measurement, the resistance in the X+ lead does not affect the conversion (it does affect the settling time, but the resistance is usually small enough that this is not a concern). However, because the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it is not possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. VREF Buffer +VCC To CDAC VREF Optional Y+ Figure 3. Simplified Diagram of the Internal Reference X+ REFERENCE INPUT The voltage difference between +REF and –REF (see Figure 2) sets the analog input range. The TSC2046E operates with a reference in the range of 1V to +VCC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code (referred to as LSB size) is also reduced. The LSB (least significant bit) size is equal to the reference voltage divided by 4096 in 12-bit mode. Any offset or gain error inherent in the ADC appears to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, it is typically 5LSBs with a 1V reference. In each case, the actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference (if an external reference is used), and a low-noise input signal. The voltage into the VREF input directly drives the capacitor digital-to-analog converter (CDAC) portion of the TSC2046E. Therefore, the input current is very low (typically < 13µA). +IN +REF Converter −IN −REF Y− GND Figure 4. Simplified Diagram of Single-Ended Reference (SER/DFR high, Y switches enabled, X+ is analog input) This situation can be remedied as shown in Figure 5. By setting the SER/DFR bit low, the +REF and –REF inputs are connected directly to Y+ and Y–, respectively, making the analog-to-digital conversion ratiometric. The result of the conversion is always a percentage of the external resistance, regardless of how it changes in relation to the on-resistance of the internal switches. Note that there is an important consideration regarding power dissipation when using the ratiometric mode of operation (see the Power Dissipation section for more details). 11 "#$%&' www.ti.com SBAS417 − JUNE 2007 +VCC Y+ X+ +IN +REF Converter −IN −REF Y− GND Figure 5. Simplified Diagram of Differential Reference (SER/DFR low, Y switches enabled, X+ is analog input) As a final note about the differential reference mode, it must be used with +VCC as the source of the +REF voltage and cannot be used with VREF. It is possible to use a high-precision reference on VREF and single-ended reference mode for measurements that do not need to be ratiometric. In some cases, it is possible to power the converter directly from a precision reference. Most references can provide enough power for the TSC2046E, but might not be able to supply enough current for the external load (such as a resistive touch screen). TOUCH SCREEN SETTLING In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (for example, noise generated by the LCD panel or backlight circuitry). These capacitors provide a low-pass filter to reduce the noise, but cause a settling time requirement when the panel is touched that typically shows up as a gain error. There are several methods for minimizing or eliminating this issue. The problem is that the input and/or reference has not settled to the final steady-state value prior to the ADC sampling the input(s) and providing the digital output. Additionally, the reference voltage may still be changing during the measurement cycle. Option 1 is to stop or slow down the TSC2046E DCLK for the required touch screen settling time. This option allows the input and reference to have stable values for the Acquire period (3 clock cycles of the TSC2046E; see Figure 9). This option works for both the single-ended and the differential modes. Option 2 is to operate the TSC2046E in the differential mode only for the touch screen measurements and command the TSC2046E to remain on (touch screen drivers ON) and not go into power-down (PD0 = 1). Several conversions are made, depending on the settling time required and the 12 TSC2046E data rate. Once the required number of conversions have been made, the processor commands the TSC2046E to go into its power-down state on the last measurement. This process is required for X-Position, Y-Position, and Z-Position measurements. Option 3 is to operate in the 15 Clock-per-Conversion mode, which overlaps the analog-to-digital conversions and maintains the touch screen drivers on until commanded to stop by the processor (see Figure 13). TEMPERATURE MEASUREMENT In some applications, such as battery recharging, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2046E relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the +25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The TSC2046E offers two modes of operation. The first mode requires calibration at a known temperature, but only requires a single reading to predict the ambient temperature. A diode is used (turned on) during this measurement cycle. The voltage across the diode is connected through the MUX for digitizing the forward bias voltage by the ADC with an address of A2 = 0, A1 = 0, and A0 = 0 (see Table 1 and Figure 6 for details). This voltage is typically 600mV at +25°C with a 20µA current through the diode. The absolute value of this diode voltage can vary by a few millivolts. However, the temperature coefficient (TC) of this voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage would be stored at a known room temperature, in memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3°C/LSB (in 12-bit mode). +VCC TE MP 0 TEM P1 MUX ADC Figure 6. Functional Block Diagram of Temperature Measurement "#$%&' www.ti.com SBAS417 − JUNE 2007 The second mode of operation does not require a test temperature calibration, but uses a two-measurement method to eliminate the need for absolute temperature calibration and for achieving 2°C accuracy. This mode requires a second conversion with an address of A2 = 1, A1 = 1, and A0 = 1, with a 91 times larger current. The voltage difference between the first and second conversion using 91 times the bias current is represented by Equation (1): kT @ In (N) q (1) where: N is the current ratio = 91. BATTERY MEASUREMENT An added feature of the TSC2046E is the ability to monitor the battery voltage on the other side of the voltage regulator (dc/dc converter), as shown in Figure 7. The battery voltage can vary from 0V to 6V, while maintaining the voltage to the TSC2046E at 2.7V, 3.3V, etc. The input voltage (VBAT) is divided down by four so that a 5.5V battery voltage is represented as 1.375V to the ADC. This design simplifies the multiplexer and control logic. In order to minimize the power consumption, the divider is only on during the sampling period when A2 = 0, A1 = 1, and A0 = 0 (see Table 1 for the relationship between the control bits and configuration of the TSC2046E). k = Boltzmann’s constant (1.38054 • 10−23 electron volts/ degrees Kelvin). q = the electron charge (1.602189 • 10–19 C). DC/DC Converter T = the temperature in degrees Kelvin. This method can provide improved absolute temperature measurement over the first mode at the cost of less resolution (1.6°C/LSB). The equation for solving for °K is: °K + q @ DV ǒk @ In (N)Ǔ Battery 0.5V + to 5.5V +VCC (2) 0.125V to 1.375V VBAT where: 2.7V ADC ∆V = V (I91) – V (I1) (in mV) 7.5kΩ ∴ °K = 2.573 °K/mV • ∆V 2.5kΩ °C = 2.573 • ∆V(mV) – 273°K NOTE: The bias current for each diode temperature measurement is only on for three clock cycles (during the acquisition mode) and, therefore, does not add any noticeable increase in power, especially if the temperature measurement only occurs occasionally. Figure 7. Battery Measurement Functional Block Diagram 13 "#$%&' www.ti.com SBAS417 − JUNE 2007 PRESSURE MEASUREMENT DIGITAL INTERFACE Measuring touch pressure can also be done with the TSC2046E. To determine pen or finger touch, the pressure of the touch needs to be determined. Generally, it is not necessary to have very high performance for this test; therefore, the 8-bit resolution mode is recommended (however, calculations shown here are in the 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2046E supports two methods. The first method requires knowing the X-plate resistance, measurement of the X-Position, and two additional cross panel measurements (Z1 and Z2) of the touch screen, as shown in Figure 8. Using Equation (3) calculates the touch resistance: See Figure 9 for the typical operation of the TSC2046E digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface. Each communication between the processor and the converter, such as SPI, SSI, or Microwiret synchronous serial interface, consists of eight clock cycles. One complete conversion can be accomplished with three serial communications for a total of 24 clock cycles on the DCLK input. ǒ Ǔ Z R TOUCH + RX−Plate @ X−Position 2 *1 4096 Z1 The first eight clock cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer and reference inputs appropriately, the converter enters the acquisition (sample) mode and, if needed, the touch panel drivers are turned on. After three more clock cycles, the control byte is complete and the converter enters the conversion mode. At this point, the input sample-and-hold goes into the hold mode and the touch panel drivers turn off (in single-ended mode). The next 12 clock cycles accomplish the actual analogto-digital conversion. If the conversion is ratiometric (SER/DFR = 0), the drivers are on during the conversion and a 13th clock cycle is needed for the last bit of the conversion result. Three more clock cycles are needed to complete the last byte (DOUT will be low), which are ignored by the converter. (3) The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position and Y-Position, and Z1. Using Equation (4) also calculates the touch resistance: R TOUCH + ǒ Ǔ RX−Plate @ X−Position 4096 *1 4096 Z1 ǒ Ǔ *R Y−Plate 1* Y−Position 4096 Measure X−Position (4) Measure Z1−Position Y+ X+ X+ Y+ Y+ X+ Touch Touch Touch X−Position Z1−Position X− Y− X− Z2−Position X− Y− Figure 8. Pressure Measurement Block Diagrams 14 Y− Measure Z2−Position "#$%&' www.ti.com SBAS417 − JUNE 2007 Control Byte mode, the converter reference voltage is always the difference between the VREF and GND pins (see Table 1 and Table 2, and Figure 2 through Figure 5, for further information). The control byte (on DIN), as shown in Table 3, provides the start conversion, addressing, ADC resolution, configuration, and power-down of the TSC2046E. Figure 9, Table 3 and Table 4 give detailed information regarding the order and description of these control bits within the control byte. Initiate START—The first bit, the S bit, must always be high and initiates the start of the control byte. The TSC2046E ignores inputs on the DIN pin until the start bit is detected. BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) S A2 A1 A0 MODE SER/DFR PD1 PD0 Table 3. Order of the Control Bits in the Control Byte Addressing—The next three bits (A2, A1, and A0) select the active input channel(s) of the input multiplexer (see Table 1, Table 2, and Figure 2), touch screen drivers, and the reference inputs. BIT NAME DESCRIPTION 7 S Start bit. Control byte starts with first high bit on DIN. A new control byte can start every 15th clock cycle in 12-bit conversion mode or every 11th clock cycle in 8-bit conversion mode (see Figure 13). MODE—The mode bit sets the resolution of the ADC. With this bit low, the next conversion has 12-bit resolution, whereas with this bit high, the next conversion has 8-bit resolution. 6-4 A2-A0 Channel Select bits. Along with the SER/DFR bit, these bits control the setting of the multiplexer input, touch driver switches, and reference inputs (see Table 1 and Figure 13). 3 MODE 12-Bit/8-Bit Conversion Select bit. This bit controls the number of bits for the next conversion: 12-bits (low) or 8-bits (high). 2 SER/DFR Single-Ended/Differential Reference Select bit. Along with bits A2-A0, this bit controls the setting of the multiplexer input, touch driver switches, and reference inputs (see Table 1 and Table 2). 1-0 PD1-PD0 Power-Down Mode Select bits. Refer to Table 5 for details. SER/DFR—The SER/DFR bit controls the reference mode, either single-ended (high) or differential (low). The differential mode is also referred to as the ratiometric conversion mode and is preferred for X-Position, Y-Position, and Pressure-Touch measurements for optimum performance. The reference is derived from the voltage at the switch drivers, which is almost the same as the voltage to the touch screen. In this case, a reference voltage is not needed as the reference voltage to the ADC is the voltage across the touch screen. In the single-ended Table 4. Descriptions of the Control Bits within the Control Byte CS t ACQ DCLK DIN 1 S 8 A2 A1 A0 MO D E SER/ DFR 1 8 1 8 PD1 PD0 (START) Idle Conversion Acquire Idle BUSY DOUT 11 10 9 8 7 6 5 4 3 (MSB) 2 1 0 Zero Filled... (LSB) (1) Drivers 1 and 2 (SER/DFR High) Off Drivers 1 and 2(1, 2) (SER/DFR Low) Off On Off On Off NOTES: (1) For Y−Position, Driver 1 is on X+ is selected, and Driver 2 is off. For X−Position, Driver 1 is off, Y+ is selected, and Driver 2 is on. Y− will turn on when power−down mode is entered and PD0 = 0. (2) Drivers will remain on if PD0 = 1 (no power down) until selected input channel, reference mode, or p ower−down mode is changed, or CS is high. Figure 9. Conversion Timing, 24 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port 15 "#$%&' www.ti.com SBAS417 − JUNE 2007 If X-Position, Y-Position, and Pressure-Touch are measured in the single-ended mode, an external reference voltage is needed. The TSC2046E must also be powered from the external reference. Caution should be observed when using the single-ended mode such that the input voltage to the ADC does not exceed the internal reference voltage, especially if the supply voltage is greater than 2.7V. NOTE: The differential mode can only be used for X-Position, Y-Position, and Pressure-Touch measurements. All other measurements require the single-ended mode. PD0 and PD1—Table 5 describes the power-down and the internal reference voltage configurations. The internal reference voltage can be turned on or off independently of the ADC. This feature can allow extra time for the internal reference voltage to settle to the final value prior to making a conversion. Make sure to also allow this extra wake-up time if the internal reference is powered down. The ADC requires no wake-up time and can be instantaneously used. Also note that the status of the internal reference power-down is latched into the part (internally) with BUSY going high. In order to turn the reference off, an additional write to the TSC2046E is required after the channel has been converted. PD1 PD0 PENIRQ DESCRIPTION 0 0 Enabled Power-Down Between Conversions. When each conversion is finished, the converter enters a low-power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to ensure full operation, and the very first conversion is valid. The Y− switch is on when in power-down. 0 1 Disabled Reference is off and ADC is on. 1 0 Enabled Reference is on and ADC is off. 1 1 Disabled Device is always powered. Reference is on and ADC is on. Table 5. Power-Down and Internal Reference Selection PENIRQ OUTPUT The pen-interrupt output function is shown in Figure 10. While in power-down mode with PD0 = 0, the Y-driver is on and connects the Y-plane of the touch screen to GND. The PENIRQ output is connected to the X+ input through two transmission gates. When the screen is touched, the X+ input is pulled to ground through the touch screen. In most of the TSC2046E models, the internal pullup resistor value is nominally 50kΩ, but this value may vary between 36kΩ and 67kΩ given process and temperature variations. In order to assure a logic low of 0.35 S (+VCC) is presented to the PENIRQ circuitry, the total resistance between the X+ and Y− terminals must be less than 21kΩ. 16 IOVDD +V CC Level Shifter 50kΩ or 90kΩ +VCC TEMP0 Y+ High except when TEMP0, TEMP1 activated. X+ PENIRQ TEMP1 TEMP DIODE Y− On Y+ or X+ drivers on, or TEMP0, TEMP1 measurements activated. Figure 10. PENIRQ Functional Block Diagram The −90 version of the TSC2046E uses a nominal 90kΩ pullup resistor that allows the total resistance between the X+ and Y− terminals to be as high as 30kΩ. Note that the higher pullup resistance causes a slower response time of the PENIRQ to a screen touch, so user software should take this into account. The PENIRQ output goes low due to the current path through the touch screen to ground, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-Position, the X+ input is disconnected from the PENIRQ internal pull-up resistor. This disconnection is done to eliminate any leakage current from the internal pull-up resistor through the touch screen, thus causing no errors. Furthermore, the PENIRQ output is disabled and low during the measurement cycle for X-, Y-, and Z-Position. The PENIRQ output is disabled and high during the measurement cycle for battery monitor, auxiliary input, and chip temperature. If the last control byte written to the TSC2046E contains PD0 = 1, the pen-interrupt output function is disabled and is not able to detect when the screen is touched. In order to re-enable the pen-interrupt output function under these circumstances, a control byte needs to be written to the TSC2046E with PD0 = 0. If the last control byte written to the TSC2046E contains PD0 = 0, the pen-interrupt output function is enabled at the end of the conversion. The end of the conversion occurs on the falling edge of DCLK after bit 1 of the converted data is clocked out of the TSC2046E. It is recommended that the processor mask the interrupt that PENIRQ is associated with whenever the processor sends a control byte to the TSC2046E. This masking prevents false triggering of interrupts when the PENIRQ output is disabled in the cases discussed in this section. "#$%&' www.ti.com SBAS417 − JUNE 2007 16 Clocks-per-Conversion Digital Timing The control bits for conversion n + 1 can be overlapped with conversion n to allow for a conversion every 16 clock cycles, as shown in Figure 11. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer from the processor to the converter. (16 clocks cycles are possible, provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that is captured on the input sample-and-hold may droop enough to affect the conversion result.) Note that the TSC2046E is fully powered while other serial communications are taking place during a conversion. Figure 9, Figure 12 and Table 6 provide detailed timing for the digital interface of the TSC2046E. 15 Clocks-per-Conversion Figure 13 provides the fastest way to clock the TSC2046E. This method does not work with the serial interface of most microcontrollers and digital signal processors, as they are generally not capable of providing 15 clock cycles per serial transfer. However, this method can be used with field-programmable gate arrays (FPGAs) or application- specific integrated circuits (ASICs). Note that this effectively increases the maximum conversion rate of the converter beyond the values given in the specification tables, which assume 16 clock cycles per conversion. CS DCLK 1 DIN 8 8 1 S 1 8 1 S Control Bits Control Bits BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 11 10 9 0 Figure 11. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port CS tCSS tCL t CH tBD tBD tDO tCSH DCLK t DS tDH PD0 DIN tBDV tBTR BUSY tDV DOUT tTR 11 10 Figure 12. Detailed Timing Diagram 17 "#$%&' www.ti.com SBAS417 − JUNE 2007 +VCC S 2.7V, +VCC S IOVDD S 1.5V, CLOAD = 50pF MIN TYP MAX SYMBOL DESCRIPTION tACQ tDS Acquisition Time 1.5 µs DIN Valid Prior to DCLK Rising 100 ns DIN Hold After DCLK High 50 tDH tDO tDV tTR UNITS ns DCLK Falling to DOUT Valid 200 ns CS Falling to DOUT Enabled 200 ns CS Rising to DOUT Disabled 200 ns tCSS tCSH CS Falling to First DCLK Rising 100 ns CS Rising to DCLK Ignored 10 ns tCH tCL DCLK High 200 ns DCLK Low 200 tBD DCLK Falling to BUSY Rising/Falling 200 ns tBDV tBTR CS Falling to BUSY Enabled 200 ns CS Rising to BUSY Disabled 200 ns ns Table 6. Timing Specifications, TA = −405C to +855C Power−Down CS DCLK 15 1 DIN S A2 A1 A0 MOD E SER/ DFR 1 15 S A2 A1 A0 PD1 PD0 M ODE SER/ DFR 1 0 1 S A2 A1 A0 PD1 PD0 BUSY DOUT 11 10 9 8 7 6 5 4 3 2 11 10 9 8 7 Figure 13. Maximum Conversion Rate, 15 Clocks-per-Conversion Data Format FS = Full− Scale Voltage = VREF(1) 1LSB = VREF(1)/4096 The TSC2046E output data is in Straight Binary format, as shown in Figure 14. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. The TSC2046E provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. This faster rate occurs because the internal settling time of the TSC2046E is not as critical—settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. 11...110 Output Code 8-Bit Conversion 1LSB 11...111 11...101 00...010 00...001 00...000 0V Input Voltage(2) (V) FS − 1LSB NOTES: (1) Reference voltage at converter: +REF − (−REF); see Figure 2. (2) Input voltage at converter, after multiplexer: +IN − (−IN); see Figure 2. Figure 14. Ideal Input Voltages and Output Codes 18 "#$%&' www.ti.com SBAS417 − JUNE 2007 POWER DISSIPATION There are two major power modes for the TSC2046E: full-power (PD0 = 1) and auto power-down (PD0 = 0). When operating at full speed and 16 clocks-per-conversion (see Figure 11), the TSC2046E spends most of the time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Therefore, the difference between full-power mode and auto power-down is negligible. If the conversion rate is decreased by slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion but conversions are done less often, the difference between the two modes is dramatic. Figure 15 shows the difference between reducing the DCLK frequency (scaling DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversions per second. In the latter case, the converter spends an increasing percentage of time in power-down mode (assuming the auto power-down mode is active). Another important consideration for power dissipation is the reference mode of the converter. In the single-ended reference mode, the touch panel drivers are ON only when the analog input voltage is being acquired (see Figure 9 and Table 1). The external device (for example, a resistive touch screen), therefore, is only powered during the acquisition period. In the differential reference mode, the external device must be powered throughout the acquisition and conversion periods (see Figure 9). If the conversion rate is high, it could substantially increase power dissipation. CS also puts the TSC2046E into power-down mode. When CS goes high, the TSC2046E immediately goes into power-down mode and does not complete the current conversion. The internal reference, however, does not turn off with CS going high. To turn the reference off, an additional write is required before CS goes high (PD1 = 0). When the TSC2046E first powers up, the device draws about 20µA of current until a control byte is written to it with PD0 = 0 to put it into power-down mode. This current draw can be avoided if the TSC2046E is powered up with CS = 0 and DCLK = IOVDD. 1000 Supply Current (µA) fCLK = 16 ⋅ fSAMPLE 100 f CLK = 2MHz Supply Current from +V C C and IO VDD 10 TA = 25¡C +VCC = 2.7V IOVDD = 1.8V 1 1k 10k 100k 1M fSAMPLE (Hz) Figure 15. Supply Current versus Directly Scaling the Frequency of DCLK with Sample Rate or Maintaining DCLK at the Maximum Possible Frequency 19 "#$%&' www.ti.com SBAS417 − JUNE 2007 LAYOUT The following layout suggestions provide the most optimum performance from the TSC2046E. Many portable applications, however, have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. This situation means less bypassing for the converter power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the TSC2046E circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches can originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. Because of the SAR architecture sensitvity, power to the TSC2046E should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1µF to 10µF capacitor may also be needed if the impedance of the connection between +VCC or IOVDD and the power supplies is high. Low-leakage capacitors should be used to minimize power dissipation through the bypass capacitors when the TSC2046E is in power-down mode. A bypass capacitor is generally not needed on the VREF pin because the internal reference is buffered by an internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. 20 The TSC2046E architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. Whereas high-frequency noise can be filtered out, voltage variation bacause of line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin must be connected to a clean ground point. In many cases, this is the analog ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Although resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections are a source of error, much like the on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations. As indicated previously, noise can be a major source of error in touch screen applications (such as in applications that require a backlit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and cause flickering of the converted data. Several things can be done to reduce this error; for instance, using a touch screen with a bottom-side metal layer connected to ground to shunt the majority of noise to ground. Additionally, filtering capacitors from Y+, Y–, X+, and X− pins to ground can also help. Caution should be observed under these circumstances for settling time of the touch screen, especially operating in the single-ended mode and at high data rates. PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TSC2046EIPW ACTIVE TSSOP PW 16 TSC2046EIPWR ACTIVE TSSOP PW TSC2046EIRGVR ACTIVE QFN TSC2046EIRGVRG4 ACTIVE TSC2046EIRGVT 90 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR QFN RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE QFN RGV 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TSC2046EIRGVTG4 ACTIVE QFN RGV 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TSC2046EIZQCR ACTIVE BGA MI CROSTA R JUNI OR ZQC 48 2500 TBD Call TI TSC2046EIZQCT ACTIVE BGA MI CROSTA R JUNI OR ZQC 48 250 Pb-Free (RoHS) SNAGCU Call TI Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 18-Jul-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSC2046EIPWR PW 16 TAI 330 12 6.67 5.4 1.6 8 12 Q1 TSC2046EIRGVR RGV 16 TAI 330 12 4.3 4.3 1.5 8 12 Q2 TSC2046EIRGVT RGV 16 TAI 330 12 4.3 4.3 1.5 8 12 Q2 TSC2046EIZQCT ZQC 48 TAI 330 12 4.3 4.3 1.5 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TSC2046EIPWR PW 16 TAI 535.4 346.0 48.3 TSC2046EIRGVR RGV 16 TAI 342.9 336.6 20.64 TSC2046EIRGVT RGV 16 TAI 342.9 336.6 20.64 TSC2046EIZQCT ZQC 48 TAI 342.9 336.6 20.64 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2007 Pack Materials-Page 3 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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