ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 TOUCH SCREEN CONTROLLER Check for Samples: ADS7843-Q1 FEATURES 1 • • • • • • • • Qualified for Automotive Applications Ratiometric Conversion Single Supply: 2.7V to 5V Up to 125kHz Conversion Rate Serial Interface Programmable 8- or 12-Bit Resolution 2 Auxiliary Analog Inputs Full Power-Down Control APPLICATIONS • • • • • DESCRIPTION The ADS7843-Q1 is a 12-bit sampling Analog-toDigital Converter (ADC) with a synchronous serial interface and low on-resistance switches for driving touch screens. Typical power dissipation is 750µW at a 125kHz throughput rate and a +2.7V supply. The reference voltage (VREF) can be varied between 1V and +VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode which reduces typical power dissipation to under 0.5µW. The ADS7843-Q1 is specified down to 2.7V operation. Low power, high speed, and onboard switches make the ADS7843-Q1 ideal for battery-operated systems such as personal digital assistants with resistive touch screens and other portable equipment. The ADS7843-Q1 is available in an SSOP-16 package and is specified over the –40°C to +85°C temperature range. Personal Digital Assistants Portable Instruments Point-of-Sales Terminals Pagers Touch Screen Monitors ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE (2) SSOP-16 – DBQ Tape and reel ORDERABLE PART NUMBER TOP-SIDE MARKING ADS7843IDBQRQ1 S7843Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated ADS7843-Q1 SBAS504A – MARCH 2011 – REVISED JULY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN DESCRIPTIONS (continued) PIN SSOP PACKAGE (TOP VIEW) NAME 5 Y– 6 GND 7 IN3 Auxiliary Input 1. ADC input Channel 3. 8 IN4 Auxiliary Input 2. ADC input Channel 4. 9 Y– Position Input NO. 1 NAME 10 +VCC Power Supply, 2.7V to 5V. 11 PENIR Pen Interrupt. Open anode output (requires Q 10kΩ to 100kΩ pull-up resistor externally). 12 1Serial Data Output. Data is shifted on the DOUT falling edge of DCLK. This output is high impedance when CS is HIGH. 13 BUSY 14 DIN Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK. 15 CS Chip Select Input. Controls conversion timing and enables the serial input/output register. DESCRIPTION +VCC Power Supply, 2.7V to 5V. 2 X+ X+ Position Input. ADC input Channel 1. 3 Y+ Y+ Position Input. ADC input Channel 2. 4 X– X– Position Input Ground VREF Voltage Reference Input PIN DESCRIPTIONS PIN DESCRIPTION NO. 16 Busy Output. This output is high impedance when CS is HIGH. External Clock Input. This clock runs the SAR DCLK conversion process and synchronizes serial data I/O. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER VALUE +VCC to GND UNIT –0.3 V to 6.5 V +VCC to GND –0.3 to +6 V Analog inputs to GND –0.3 to +VCC + 0.3 V Digital inputs to GND –0.3 to +VCC + 0.3 V Power dissipation 250 mW Maximum junction temperature +150 °C Operating temperature range –40°C to +85 °C Storage temperature range –65°C to +150 °C +300 °C Human-Body Model (HBM) 400 V Machine Model (MM) 100 V Charged-Device Model (CDM) 750 V Lead temperature (soldering, 10s) Electrostatic discharge (ESD) (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 ELECTRICAL CHARACTERISTICS at TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital inputs = GND or +VCC, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 0 VREF V –0.2 +VCC +0.2 V +0.2 V Analog Input Full-Scale Input Span Positive Input – Negative Input Absolute Input Range Positive Input Negative Input –0.2 Capacitance 25 pF Leakage Current 0.1 μA 12 Bits System Performance Resolution No Missing Codes 11 Bits Integral Linearity Error Offset Error Offset Error Match 0.1 Gain Error ±2 LSB (1) ±6 LSB 1 LSB ±4 LSB 1 LSB Gain Error Match 0.1 Noise 30 μVrms Power-Supply Rejection 70 dB Sampling Dynamics Conversion Time 12 Acquisition Time 3 Clk Cycles Clk Cycles Throughput Rate 125 Multiplexer Settling Time Aperture Delay Aperture Jitter kHz 500 ns 30 ns 100 ps 100 dB Y+, X+ 5 Ω Y–, X– 6 Ω Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz Switch Drivers On-Resistance Reference Input Range 1 Resistance CS = GND or +VCC +VCC 5 Input Current 13 fSAMPLE = 12.5kHz 2.5 CS = +VCC 0.001 V GΩ 40 μA μA 3 μA Digital Input/Output Logic Family Logic Levels, Except PENIRQ PENIRQ CMOS VIH | IIH | ≤ +5μA VIL | IIL | ≤ +5μA VOH IOH = –250μA VOL IOL = 250μA 0.4 V VOL TA = 0°C to +85°C, 100kΩ Pull-Up 0.8 V Data Format (1) +VCC • 0.7 +VCC +0.3 –0.3 +0.8 +VCC • 0.8 V V Straight Binary LSB means Least Significant Bit. With VREF equal to +2.5V, 1LSB is 610μV. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 3 ADS7843-Q1 SBAS504A – MARCH 2011 – REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) at TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital inputs = GND or +VCC, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 3.6 V Quiescent Current 280 650 μA fSAMPLE = 12.5kHz 220 Power-Supply Requirements +VCC Specified Performance 2.7 Shutdown Mode with DCLK = DIN = +VCC Power Dissipation +VCC = +2.7V μA 3 μA 1.8 mW +85 °C Temperature Range Specified Performance 4 –40 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 TYPICAL CHARACTERISTICS TA = 25°C, VDD = 5 V (unless otherwise noted) POWER-DOWN SUPPLY CURRENT vs TEMPERATURE Supply Current (mA) Supply Current (mA) SUPPLY CURRENT vs TEMPERATURE Figure 2. SUPPLY CURRENT vs +VCC MAXIMUM SAMPLE RATE vs +VCC Sample Rate (Hz) Supply Current (mA) Figure 1. Figure 4. CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE Delta from +25°C (LSB) Delta from +25°C (LSB) Figure 3. Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 5 ADS7843-Q1 SBAS504A – MARCH 2011 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 5 V (unless otherwise noted) REFERENCE CURRENT vs TEMPERATURE Reference Current (mA) Reference Current (mA) REFERENCE CURRENT vs SAMPLE RATE Figure 8. SWITCH-ON RESISTANCE vs +VCC (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) SWITCH-ON RESISTANCE vs TEMPERATURE (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) RON (W) RON (W) Figure 7. Figure 9. Figure 10. LSB Error MAXIMUM SAMPLING RATE vs RIN Figure 11. 6 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 THEORY OF OPERATION The ADS7843-Q1 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6μm CMOS process. The basic operation of the ADS7843-Q1 is shown in Figure 12. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 1V and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS7843-Q1. The analog input to the converter is provided via a four-channel multiplexer. A unique configuration of low onresistance switches allows an unselected ADC input channel to provide power and an accompanying pin to provide ground for an external device. By maintaining a differential input to the converter and a differential reference architecture, it is possible to negate the switch’s on-resistance error (should this be a source of error for the particular measurement). ANALOG INPUT See Figure 13 for a block diagram of the input multiplexer on the ADS7843-Q1, the differential input of the ADC, and the converter’s differential reference. Table 1 and Table 2 show the relationship between the A2, A1, A0, and SER/DFR control bits and the configuration of the ADS7843-Q1. The control bits are provided serially via the DIN pin—see the Digital Interface section of this data sheet for more details. When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (see Figure 13) is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. 1 mF to 10 mF 100 kW (optional) 1 mF Figure 12. Basic Operation of the ADS7843-Q1 Table 1. Input Configuration, Single-Ended Reference Mode (SER/DFR HIGH) (1) A2 A1 A0 X+ 0 0 1 +IN 1 0 1 0 1 0 1 1 0 Y+ IN3 IN4 +IN +IN +IN –IN(1) X SWITCH ES Y SWITCH ES +REF (1) –REF (1) GND OFF ON +VREF GND GND ON OFF +VREF GND GND OFF OFF +VREF GND GND OFF OFF +VREF GND Internal node, for clarification only—not directly accessible by the user. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 7 ADS7843-Q1 SBAS504A – MARCH 2011 – REVISED JULY 2012 www.ti.com Table 2. Input Configuration, Differential Reference Mode (SER/DFR LOW). (1) A2 A1 A0 X+ 0 0 1 +IN 1 0 1 0 1 0 1 1 0 Y+ IN3 IN4 +IN +IN +IN –IN(1) X SWITCH ES Y SWITCH ES +REF (1) –REF (1) –Y –X OFF ON +Y –Y ON OFF +X –X GND OFF OFF +VREF GND GND OFF OFF +VREF GND Internal node, for clarification only—not directly accessible by the user. Figure 13. Simplified Diagram of Analog Input REFERENCE INPUT The voltage difference between +REF and –REF (shown in Figure 13) sets the analog input range. The ADS7843-Q1 will operate with a reference in the range of 1V to +VCC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the ADC will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, it will typically be 5LSBs with a 1V reference. In each case, the actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a low-noise reference, and a low-noise input signal. The voltage into the VREF input is not buffered and directly drives the Capacitor Digital-to-Analog Converter (CDAC) portion of the ADS7843-Q1. Typically, the input current is 13μA with VREF = 2.7V and fSAMPLE = 125kHz. This value will vary by a few microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. 8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 There is also a critical item regarding the reference when making measurements where the switch drivers are on. For this discussion, it’s useful to consider the basic operation of the ADS7843-Q1 as shown in Figure 12. This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and Y– drivers, and digitizing the voltage on X+ (shown in Figure 14). For this measurement, the resistance in the X+ lead does not affect the conversion (it does affect the settling time, but the resistance is usually small enough that this is not a concern). Figure 14. Simplified Diagram of Single-Ended Reference (SER/DFR HIGH, Y Switches Enabled, X+ is Analog Input) However, since the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. This situation can be remedied as shown in Figure 15. By setting the SER/DFR bit LOW, the +REF and –REF inputs are connected directly to Y+ and Y–. This makes the A/D conversion ratiometric. The result of the conversion is always a percentage of the external resistance, regardless of how it changes in relation to the on-resistance of the internal switches. Note that there is an important consideration regarding power dissipation when using the ratiometric mode of operation, see the Power Dissipation section for more details. As a final note about the differential reference mode, it must be used with +VCC as the source of the +REF voltage and cannot be used with VREF. It is possible to use a high precision reference on VREF and single-ended reference mode for measurements which do not need to be ratiometric. Or, in some cases, it could be possible to power the converter directly from a precision reference. Most references can provide enough power for the ADS7843-Q1, but they might not be able to supply enough current for the external load (such as a resistive touch screen). Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 9 ADS7843-Q1 SBAS504A – MARCH 2011 – REVISED JULY 2012 www.ti.com Figure 15. Simplified Diagram of Differential Reference (SER/DFR LOW, Y Switches Enabled, X+ is Analog Input). DIGITAL INTERFACE Figure 16 shows the typical operation of the ADS7843-Q1’s digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface. Each communication between the processor and the converter consists of eight clock cycles. One complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the DCLK input. The first eight clock cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer, switches, and reference inputs appropriately, the converter enters the acquisition (sample) mode and, if needed, the internal switches are turned on. After three more clock cycles, the control byte is complete and the converter enters the conversion mode. At this point, the input sampleand-hold goes into the hold mode and the internal switches may turn off. The next 12th clock cycles accomplish the actual A/D conversion. If the conversion is ratiometric (SER/DFR LOW), the internal switches are on during the conversion. A 13th clock cycle is needed for the last bit of the conversion result. Three more clock cycles are needed to complete the last byte (DOUT will be LOW). These will be ignored by the converter. Figure 16. Conversion Timing, 24 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port. Control Byte See Figure 16 for the placement and order of the control bits within the control byte. Table 3 and Table 4 give detailed information about these bits. The first bit, the ‘S’ bit, must always be HIGH and indicates the start of the control byte. The ADS7843Q1 will ignore inputs on the DIN pin until the start bit is detected. The next three bits (A2-A0) select the active input channel or channels of the input multiplexer (see Table 1 and Table 2 and Figure 13). The MODE bit determines the number of bits for each conversion, either 12 bits (LOW) or 8 bits (HIGH). The SER/DFR bit controls the reference mode: either single-ended (HIGH) or differential (LOW). (The differential mode is also referred to as the ratiometric conversion mode.) In single-ended mode, the converter’s reference voltage is always the difference between the VREF and GND pins. In differential mode, the reference voltage is the difference between the currently enabled switches. See Table 1 and Table 2 and Figure 13 through Figure 15 for more information. The last two bits (PD1-PD0) select the power-down mode as shown in Table 5. If both inputs 10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid. There are two power-down modes: one where PENIRQ is disabled and one where it is enabled. Table 3. Order of the Control Bits in the Control Byte Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) S A2 A1 A0 MODE SER/D FR PD1 PD0 16-Clocks per Conversion The control bits for conversion n + 1 can be overlapped with conversion ‘n’ to allow for a conversion every 16 clock cycles, as shown in Figure 17. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter. Table 4. Descriptions of the Control Bits within the Control Byte BIT NAME DESCRIPTION 7 S Start Bit. Control byte starts with first HIGH bit on DIN. A new control byte can start every 16th clock cycle in 12-bit conversion mode or every 12th clock cycle in 8-bit conversion mode. 6-4 A2-A0 Channel Select Bits. Along with the SER/DFR bit, these bits control the setting of the multiplexer input, switches, and reference inputs, see Tables I and II. 3 MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls the number of bits for the following conversion: 12 bits (LOW) or 8 bits (HIGH). 2 SER/DFR Single-Ended/Differential Reference Select Bit. Along with bits A2A0, this bit controls the setting of the multiplexer input, switches, and reference inputs, see Tables I and II. 1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for details. Table 5. Power-Down Selection PD1 PD0 PENIRQ DESCRIPTION 0 0 Enabled Power-down between conversions. When each conversion is finished, the converter enters a low power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid. The Y– switch is on while in power-down. 0 1 Disabled Same as mode 00, except PENIRQ is disabled. The Y– switch is off while in power-down mode. 1 0 Disabled Reserved for future use. 1 1 Disabled No power-down between conversions, device is always powered. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 11 ADS7843-Q1 SBAS504A – MARCH 2011 – REVISED JULY 2012 www.ti.com Figure 17. Conversion Timing, 16 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port. This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the input sample-and-hold may droop enough to affect the conversion result. Note that the ADS7843-Q1 is fully powered while other serial communications are taking place during a conversion. Digital Timing Figure 19 and Table 6 provide detailed timing for the digital interface of the ADS7843-Q1. Table 6. Timing Specifications (+VCC = +2.7V and Above, TA = –40°C to +85°C, CLOAD = 50pF). 12 SYMBOL DESCRIPTION MIN tACQ Acquisition Time 1.5 MAX UNITS μs ns tDS DIN Valid Prior to DCLK Rising 100 tDH DIN Hold After DCLK HIGH 10 tDO DCLK Falling to DOUT Valid 200 ns tDV CS Falling to DOUT Enabled 200 ns tTR CS Rising to DOUT Disabled 200 ns tCSS CS Falling to First DCLK Rising tCSH tCH ns 100 ns CS Rising to DCLK Ignored 0 ns DCLK HIGH 200 ns tCL DCLK LOW 200 tBD DCLK Falling to BUSY Rising 200 ns tBDV CS Falling to BUSY Enabled 200 ns tBTR CS Rising to BUSY Disabled 200 200 200 ns ns ns 200 ns Submit Documentation Feedback ns Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 Data Format The ADS7843-Q1 output data is in Straight Binary format, as shown in Figure 18. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. Figure 18. Ideal Input Voltages and Output Codes 8-Bit Conversion The ADS7843-Q1 provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. This could be used in conjunction with serial interfaces that provide 12-bit transfers or two conversions could be accomplished with three 8-bit transfers. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. This is because the internal settling time of the ADS7843-Q1 is not as critical—settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. Figure 19. Detailed Timing Diagram POWER DISSIPATION There are two major power modes for the ADS7843Q1: full power (PD1-PD0 = 11B) and auto powerdown (PD1-PD0 = 00B). When operating at full speed and 16 clocks per conversion ( see Figure 17), the ADS7843-Q1 spends most of its time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Therefore, the difference between full power mode and auto power- down is negligible. If the conversion rate is decreased by simply slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion but conversions are simply done less often, the difference between the two modes is dramatic. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 13 ADS7843-Q1 SBAS504A – MARCH 2011 – REVISED JULY 2012 www.ti.com Figure 20 shows the difference between reducing the DCLK frequency (“scaling” DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversions per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active). Supply Current (mA) Another important consideration for power dissipation is the reference mode of the converter. In the singleended reference mode, the converter’s internal switches are on only when the analog input voltage is being acquired (see Figure 16). Thus, the external device, such as a resistive touch screen, is only powered during the acquisition period. In the differential reference mode, the external device must be powered throughout the acquisition and conversion periods (see Figure 16). If the conversion rate is high, this could substantially increase power dissipation. Figure 20. Supply Current versus Directly Scaling the Frequency of DCLK with Sample Rate or Keeping DCLK at the Maximum Possible Frequency LAYOUT The following layout suggestions should provide the most optimum performance from the ADS7843-Q1. However, many portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly “clean” power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter’s power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the ADS7843-Q1 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just 14 prior to latching the output of the analog comparator. Thus, during any single conversion for an ‘n-bit’ SAR converter, there are n ‘windows’ in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. With this in mind, power to the ADS7843-Q1 should be clean and well bypassed. A 0.1μF ceramic bypass capacitor should be placed as close to the device as possible. A 1μF to 10μF capacitor may also be needed if the impedance of the connection between +VCC and the power supply is high. The reference should be similarly bypassed with a 0.1μF capacitor. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation. The ADS7843-Q1 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion). The ADS7843-Q1 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections will be a source of error, much like the on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 ADS7843-Q1 www.ti.com SBAS504A – MARCH 2011 – REVISED JULY 2012 REVISION HISTORY Changes from Original (March, 2011) to Revision A • Page Changed top-side marking from ADS7843Q to S7843Q. ..................................................................................................... 1 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): ADS7843-Q1 15 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device ADS7843IDBQRQ1 Status (1) Package Type Package Drawing ACTIVE SSOP DBQ Pins Package Qty 16 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF ADS7843-Q1 : • Catalog: ADS7843 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7843IDBQRQ1 Package Package Pins Type Drawing SSOP DBQ 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7843IDBQRQ1 SSOP DBQ 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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