BOURNS TISPPBL2SDR

TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
OVERVOLTAGE PROTECTION FOR ERICSSON COMPONENTS LINE INTERFACE CIRCUITS
●
Overvoltage Protector‡ for:-
D PACKAGE
(TOP VIEW)
PBL 3762A
PBL 3764A/4, PBL 3764A/6
PBL 3766, PBL 3766/6
PBL 3767, PBL 3767/6
PBL 3796, PBL 3796/2
PBL 3798, PBL 3798/2
PBL 3798/5
PBL 3798/6
PBL 3799
PBL 3860A/1, PBL 3860A/6
PBL 386 10/2
PBL 386 11/2
PBL 386 20/1
PBL 386 21/1
PBL 386 30/1
PBL 386 40/1
PBL 386 50/1
PBL 3898/M
●
NC
1
8
2
7
A
(Ground)
NC
3
6
A
(Ground)
(Ring) K2
4
5
NC
(Gate) G
MD6XBA
NC - No internal connection
Terminal typical application names shown in
parenthesis
device symbol
K1
A
G1,G2
A
Rated for International Surge Wave Shapes
WAVE SHAPE
2/10 µs
●
K1
(Tip)
STANDARD
ITSP
K2
Terminals K1, K2 and A correspond to the alternative
line designators of T, R and G or A, B and C. The
negative protection voltage is controlled by the
voltage, VGG, applied to the G terminal.
SD6XAP
A
GR-1089-CORE
100
1.2/50 µs
ITU-T K22
100
0.5/700 µs
I3124
40
10/700 µs
ITU-T K20, K21
40
10/1000 µs
GR-1089-CORE
30
Single-Lead Line Connection Version of
Feed-Through TISPPBL2D
- Ground Lead Creepage Distance . . > 3 mm
●
Small Outline Surface Mount Package
- Available Ordering Options
CARRIER
ORDER #
Tube
TISPPBL2SD
Taped and reeled
TISPPBL2SDR
description
The TISPPBL2S is a dual forward-conducting buffered p-gate overvoltage protector. It is designed to protect
the Ericsson Components PBL 3xxx family of SLICs (Subscriber Line Interface Circuits) against overvoltages
on the telephone line caused by lightning, a.c. power contact and induction. The TISPPBL2S limits voltages
that exceed the SLIC supply rail levels.
The SLIC line driver section is typically powered from 0 V (ground) and a negative voltage in the region of
-10 V to -85 V. The protector gate is connected to this negative supply. This references the protection
(clipping) voltage to the negative supply voltage. As the protection voltage will track the negative supply
voltage the overvoltage stress on the SLIC is minimised.
Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially
clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then
the protector will crowbar into a low voltage ground referenced on-state condition. As the overvoltage
‡ Customers are advised to obtain the latest version of the relevant Ericsson Components SLIC information to verify, before placing orders, that
the information being relied on is current.
PRODUCT
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
1
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
subsides the high holding current of the crowbar prevents d.c. latchup. The TISPPBL2S buffered gate design
reduces the loading on the SLIC supply during overvoltages caused by power cross and induction.
These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high
reliability and in normal system operation they are virtually transparent. The TISPPBL2S is the TISPPBL2D
with a different pinout. The feed-through Ring (leads 4 — 5) and Tip (leads 1 — 8) connections have been
replaced by single Ring (lead 4) and Tip (lead 1) connections. This increases package creepage distance of
the biased to ground connections from about 0.7 mm to over 3 mm.
absolute maximum ratings
RATING
SYMBOL
VALUE
UNIT
Repetitive peak off-state voltage, IG = 0, -40°C ≤ TJ ≤ 85°C
VDRM
-100
V
Repetitive peak gate-cathode voltage, VKA = 0, -40°C ≤ TJ ≤ 85°C
VGKRM
-90
V
Non-repetitive peak on-state pulse current (see Notes 1 and 2)
10/1000 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)
30
0.2/310 µs (I3124, open-circuit voltage wave shape 0.5/700 µs)
40
ITSP
5/310 µs (ITU-T K20 & K21, open-circuit voltage wave shape 10/700 µs)
A
40
1/20 µs (ITU-T K22, open-circuit voltage wave shape 1.2/50 µs)
100
2/10 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)
100
Non-repetitive peak on-state current, 50/60 Hz (see Notes 1 and 2)
100 ms
11
1s
4.5
ITSM
5s
300 s
0.95
900 s
0.93
Non-repetitive peak gate current, 1/2 µs pulse, cathodes commoned (see Note 1)
Operating free-air temperature range
Junction temperature
Storage temperature range
A
2.4
IGSM
40
A
TA
-40 to +85
°C
TJ
-40 to +150
°C
Tstg
-40 to +150
°C
NOTES: 1. Initially the protector must be in thermal equilibrium with -40 °C ≤ TJ ≤ 85 °C. The surge may be repeated after the device returns to
its initial conditions.
2. These non-repetitive rated currents are peak values for either polarirty. The rated current values may be applied either to the Ring
to Ground or to the Tip to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied
simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Above
85 °C, derate linearly to zero at 150 °C lead temperature.
recommended operating conditions
CG
R1
Gate decoupling capacitor
MIN
TYP
100
220
TISPPBL2S series resistor for GR-1089-CORE first-level and second-level surge survival
40
TISPPBL2S series resistor for GR-1089-CORE first-level surge survival
25
TISPPBL2S series resistor for ITU-T recommendation K20/21
10
MAX
UNIT
nF
Ω
electrical characteristics, Tamb = 25 °C (unless otherwise noted)
PARAMETER
ID
Off-state current
TEST CONDITIONS
VD = VDRM, VGK = 0
MIN
MAX
UNIT
TJ = -40 °C
-5
µA
TJ = 85 °C
-50
µA
PRODUCT
2
TYP
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
electrical characteristics, Tamb = 25 °C (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
V(BO)
Breakover voltage
t(BR)
Breakdown time
VF
Forward voltage
VFRM
IT = -20 A, 0.5/700 generator, Figure 3 test circuit (See Note 3 and
IT = -20 A, 0.5/700 generator, Figure 3 test cir-
V(BR) < -50 V
IF = 5 A, tw = 500 µs
Peak forward recovery
IF = 20 A, 0.5/700 generator, Figure 3 test circuit (See Note 4 and Fig-
voltage
ure 2)
Forward recovery time
IH
Holding current
IGAT
TYP
Figure 2)
cuit (See Note 3 and Figure 2)
tFR
IGAS
MIN
Gate reverse current,
on state
V
1
µs
3
V
8
V
IF = 20 A, 0.5/700 generator, Figure 3 test cir-
VF > 5 V
1
VF > 1 V
10000
VGG = VGKRM, VAK = 0
UNIT
-70
cuit (See Note 4 and Figure 2)
IT = -1 A, di/dt = 1A/ms, VGG = -50 V, -40 °C ≤ TJ ≤ 85 °C
Gate reverse current
MAX
-150
µs
mA
TJ = -40 °C
-5
µA
TJ = 85 °C
-50
µA
-1
mA
IT = -0.5 A, tw = 500 µs, VGG = -50 V
Gate reverse current,
IGAF
forward conducting
IF = 1 A, tw = 500 µs, VGG = -50 V
-10
mA
state
IGT
Gate trigger current
IT = -5 A, tp(g) ≥ 20 µs, VGG = -50 V
VGT
Gate trigger voltage
IT = -5 A, tp(g) ≥ 20 µs, VGG = -50 V
CAK
Anode-cathode offstate capacitance
5
f = 1 MHz, Vd = 1 V, IG = 0, (see Note 5)
mA
2.5
V
VD = -3 V
110
pF
VD = -50 V
60
pF
NOTES: 3. For the required TIPX and RINGX terminal negative pulse performance refer to the respective Ericsson Components SLIC data
sheet. The PBL 379x family of SLICs has ratings of -120 V for 0.25 µs, -90 V for 1 µs, -70 V for 10 ms and -70 V for d.c. The PBL
376x family together with the PBL 3860A SLIC have the same maximum ratings when the applied battery voltage is -50 V. As the
FLEXI-SLIC™ PBL 386 xx family is specified in terms of current pulses, a minimum value of 2 Ω for RP should be used.
Compliance to these conditions is guaranteed by the maximum breakover voltage and the breakdown times of the TISPPBL2S.
4. For the required TIPX and RINGX terminal positive pulse performance refer to the respective Ericsson Components SLIC data
sheet. The PBL 379x family of SLICs has ratings of 15 V for 0.25 µs, 10 V for 1 µs, 5 V for 10 ms and 1 V for d.c. The PBL 376x
family together with the PBL 3860A SLIC have similar ratings. As the FLEXI-SLIC™ PBL 386 xx family is specified in terms of
current pulses, a minimum value of 2 Ω for RP should be used. Compliance to these conditions is guaranteed by the peak forward
recovery voltage and the forward recovery times of the TISPPBL2S
5. These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured
device terminals are a.c. connected to the guard terminal of the bridge.
thermal characteristics
PARAMETER
RθJA
Junction to free air thermal resistance
PRODUCT
TEST CONDITIONS
Ptot = 0.8 W, TA = 25 °C
5 cm2, FR4 PCB
D Package
MIN
TYP
MAX
UNIT
160
°C/W
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
3
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
PARAMETER MEASUREMENT INFORMATION
GATE TRANSFER
CHARACTERISTIC
PRINCIPAL TERMINAL V-I CHARACTERISTIC
+i K
Quadrant I
+i
I FSP (= |I TSP|)
Forward
Conduction
Characteristic
I F S M (= |I T S M |)
IF
IF
VF
V GK(BO)
V GG
-v
I GT
VD
ID
I (BO)
-i G
+i G
IG A F
IH
IS
VT
VS
V (BO)
+v
IG A T
IT
IT
IT S M
IG
Quadrant III
S w itching
Characteristic
IK
I TSP
-i
-i K
PM6XAIA
Figure 1. PRINCIPAL TERMINAL AND GATE TRANSFER CHARACTERISTICS
PROTECTOR MAXIMUM LIMITING VOLTAGE
vs
TIME
10
5
MAX VFRM = 8 V
1 µs
10 ms
VOLTAGE - V
0
-50
Time
VBAT = -50 V
1 µs
-60
-70
MAX V(BO) = -70 V
PM6XAL
-80
Figure 2. TRANSIENT LIMITS FOR TISPPBL2S LIMITING VOLTAGE
PRODUCT
4
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
IMPULSE
R1 CURRENT
50 Ω
IT, IF
Hi
S1
±1960 V
15 Ω
20 µF
25 Ω
20 nF
Lo
LIMITING
VOLTAGE
VK, VF
Th4
DUT
(TISPPBL2S)
ECAT WITH E502 0.5/700 SURGE NETWORK
Th5
R1 = ONE SECTION OF A PBR 530 01/1 LPC LINE
RESISTOR NETWORK
IG
220 nF
VGG
-50 V
(VBAT)
AI6XBAS
Figure 3. TEST CIRCUIT FOR MEASUREMENT OF LIMITING VOLTAGE
80
di/dt - Rate of Rise of Wavefront Current - A/µs
i - Wavefront Current - A
20
E502 0.5/700 WAVEFRONT CURRENT
vs
TIME
AI6XAY
15
10
5
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time - µs
Figure 4. CURRENT WAVEFRONT
PRODUCT
E502 0.5/700 WAVEFRONT di/dt
vs
TIME
AI6XAZ
70
60
50
40
30
20
10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Time - µs
Figure 5. CURRENT WAVEFRONT di/dt
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
5
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
THERMAL INFORMATION
ITSM - Peak Non-Recurrent 50 Hz Current - A
PEAK NON-RECURRING A.C.
vs
CURRENT DURATION
10
TI6LACA
RING AND TIP CONNECTIONS Equal ITSM values were applied to both
GROUND CONNECTION Current is twice ITSM value
VGEN = 600 Vrms
RGEN = 70 to 950 Ω
VG = -48 V, TAMB = 85°C
1
0·1
1
10
100
1000
t - Current Duration - s
Figure 6.
PRODUCT
6
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
TYPICAL CHARACTERISTICS
VK - Cathode Voltage - V
-10
-20
50 devices tested from 10 wafer lots
0.5/700 Waveform
IT = -20 A
TA = 25°C
VGG = -50 V
DISTRIBUTION LIMITS OF
DIODE FORWARD VOLTAGE
vs
TIME
6
-30
-40
-50
4
3
2
50 devices tested from 10 wafer lots
0.5/700 Waveform
IF = 20 A
TA = 25°C
VGG = -50 V
1
-60
0
0.0 0.1 0.2 0.3
-70
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Time - µs
Figure 7.
99·9
0.9 1.0
DIODE FORWARD CURRENT
vs
FORWARD VOLTAGE
TC61AD
0.7
0.4
99
IF - Forward Current - A
Cumulative Population - %
1
50 devices tested from 10 wafer lots
IF = 20 A, IT = -20 A, 0.5/700 Waveform
TA = 25°C, VGG = -50 V
99·99
0.4 0.5 0.6 0.7 0.8
Time - µs
Figure 8.
CUMULATIVE POPULATION %
vs
PEAK LIMITING VOLTAGE TC6XAB
99·999
AI6XAX
5
VF - Forward Voltage - V
0
DISTRIBUTION LIMITS OF
THYRISTOR LIMITING VOLTAGE
vs
TIME
AI6XAW
90
70
50
30
10
85°C
0.2
25°C
-40°C
0.1
0.07
0.04
1
DIODE
VFRM
0·1
THYRISTOR
VGG - V(BO)
0.02
0·01
0·001
4
5
6
7
8
9 10
Peak Limiting Voltage - V
15
Figure 9.
PRODUCT
0.01
0.5
0.6
0.7
0.8
0.9
1.0
VF - Forward Voltage - V
1.1
1.2
Figure 10.
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
7
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
99·99
Cumulative Population - %
99·9
50 devices tested from 10 wafer lots
IF = 20 A, IT = -20 A, 0.5/700 Waveform
TA = 25°C, VGG = -50 V
99
90
70
50
30
10
1
0·1
0·01
DIODE tFR
for VF > 5 V
Outliers
(2) @ 0 µs
THYRISTOR t(BR)
for V(BR) < VGG
0·001
0.001
1
0.004 0.01
0.04 0.1
0.4
t(BR), tFR - Breakdown and Forward Recovery Times - µs
1.10
Normalised Peak Limiting Voltages
99·999
NORMALISED PEAK LIMITING VOLTAGES
vs
JUNCTION TEMPERATURE TC6XAA
CUMULATIVE POPULATION %
vs
LIMITING TIME
TC6XAC
1.05
1.00
0.95
Normalised to 25°C values
of V(BO) and VFRM
IF = 20 A, IT = -20 A
0.5/700 Waveform
VGG = -50 V
THYRISTOR
V(BO)
DIODE
VFRM
0.90
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80
TJ - Junction Temperature - °C
Figure 11.
Figure 12.
APPLICATIONS INFORMATION
operation of gated protectors
Figure 13 and Figure 14 show how the TISPPBL2S limits overvoltages. The TISPPBL2S thyristor sections
limit negative overvoltages and the diode sections limit positive overvoltages.
SLIC
PROTECTOR
SLIC
PROTECTOR
SLIC
SLIC
IK
IF
Th5
TISP
PBL2S
VGG
AI6XANS
C1
Th5
TISP
PBL2S
IG
D1
VBat
C2
Figure 13. NEGATIVE OVERVOLTAGE CONDITION
VGG
AI6XAOS
C1
D1
VBat
C2
Figure 14. POSITIVE OVERVOLTAGE CONDITION
Negative overvoltages (Figure 13) are initially clipped close to the SLIC negative supply rail value (VBAT) by
the conduction of the transistor base-emitter and the thyristor gate-cathode junctions. If sufficient current is
available from the overvoltage, then the thyristor will crowbar into a low voltage ground referenced on-state
condition. As the overvoltage subsides the high holding current of the crowbar thyristor prevents d.c. latchup.
PRODUCT
8
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
The negative protection voltage will be the sum of the gate supply (VBAT) and the peak gate(terminal)-cathode
voltage (VGK(BO)). Under a.c. overvoltage conditions VGK(BO) will be less than 3 V. The integrated transistor
buffer in the TISPPBL2S greatly reduces protectors source and sink current loading on the VBAT supply.
Without the transistor, the thyristor gate current would charge the VBAT supply. An electronic power supply is
not usually designed to be charged like a battery. As a result, the electronic supply would switch off and the
thyristor gate current would provide the SLIC supply current. Normally the SLIC current would be less than
the gate current, which would cause the supply voltage to increase and destroy the SLIC by a supply
overvoltage. The integrated transistor buffer removes this problem.
Fast rising impulses will cause short term overshoots in gate-cathode voltage. The negative protection
voltage under impulse conditions will also be increased if there is a long connection between the gate
decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast impulse, the gate current (IG) is
the same as the cathode current (IK). Rates of 60 A/µs can cause inductive voltages of 0.6 V in 2.5 cm of
printed wiring track. To minimise this inductive voltage increase of protection voltage, the length of the
capacitor to gate terminal tracking should be minimised. Inductive voltages in the protector cathode wiring
can increase the protection voltage. These voltages can be minimised by routing the SLIC connection via the
protector as shown in Figure 13 and Figure 14.
Positive overvoltages (Figure 14) are clipped to ground by forward conduction of the diode section in the
TISPPBL2S. Fast rising impulses will cause short term overshoots in forward voltage (VFRM).
TISPPBL2S limiting voltages
This clause details the TISPPBL2S voltage limiting levels under impulse conditions.
test circuit
Figure 3 shows the basic test circuit used for the measurement of impulse limiting voltage. During the
impulse, the high levels of electrical energy and rapid rates of change cause electrical noise to be induced or
conducted into the measurement system. It is possible for the electrical noise voltage to be many times the
wanted signal voltage. Elaborate wiring and measurement techniques where used to reduce the noise
voltage to less than 2 V peak to peak.
impulse generator
A Keytek ECAT E-Class series 100 with an E502 surge network was used for testing. The E502 produces a
0.5/700 voltage impulse. This particular waveform was used as it has the fastest rate of current rise (di/dt) of
the commonly used lightning surge waveforms. This maximises the measured limiting voltage. Figure 4
shows the current wavefront through the DUT. To produce a peak test current level of ±20 A, the E502
charging voltage was set to ±1960 V. Figure 5 shows the DUT current di/dt. Initially the wavefront current rises
at 60 A/µs, this rate then reduces as the peak current is approached. At the TISPPBL2S V(BO) condition the
di/dt is about 50 A/µs.
limiting voltage levels
Fifty devices were measured in the test circuit of Figure 3. The 50 devices were made up from groups of 5
devices taken from 10 separately processed device lots. Figure 7 shows the total waveform variation of the
thyristor limiting voltage across the 50 devices. This shows that the largest peak limiting voltage (Breakover
voltage, V(BO)) is -62 V, a 12 V overshoot beyond the -50 V gate reference supply, VGG. The limiting voltage
exceeds the gate reference supply voltage level for a period (t(BR)) of about 0.4 µs.
Figure 9 and Figure 11 show these two waveform parameters in terms of device population. In Figure 9, the
limiting voltage is shown in terms of the overshoot beyond the gate reference supply (VGG - V(BO)). Removing
the gate reference voltage level magnifies the thyristor limiting voltage variation and shows the data
stratification caused by the oscilloscope digitisation. Extrapolating the data trend indicates that the overshoot
is less than 14 V at the 99.997% level (equal to 30 ppm of the population exceeding 14 V, equivalent to +4
sigma point of a normal distribution). In Figure 11, extrapolating the thyristor data trend to the 99.997% level
PRODUCT
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
9
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
indicates a maximum breakdown time, t(BR), of 0.5 µs. Figure 12 shows that increasing the temperature up to
85°C increases the thyristor peak limiting voltage by 2.4%, giving a maximum 85°C peak limiting voltage of
1.024x(-50-14) = -65.5. Over the -40°C to 85°C temperature range the TISPPBL2S is specified to have a
maximum V(BO) value of -70 V and a breakdown time, t(BR), of 1 µs.
Figure 8 shows the total waveform variation of the diode limiting voltage across the 50 devices. The peak
limiting voltage (Peak Forward Recovery Voltage VFRM) is less than 6 V, and this value includes the 2 V of
magnetically induced noise in the probe. Figure 9 shows that extrapolated 99.997% level is about 5.5 V. In
Figure 11, extrapolating the diode data trend to the 99.997% level indicates a maximum forward recovery
time, tFR, of 0.1 µs. Figure 12 indicates that there is about a 10% uplift by increasing the temperature to 85°C.
This gives a maximum 85°C peak limiting voltage of 1.1x(5.5) = 6.1 V. Over the -40°C to 85°C temperature
range, the TISPPBL2S is specified to have a maximum VFRM value of 8 V and a maximum forward recovery
time of 1 µs.
Diodes do not switch to a much lower voltage like thyristors, so the diode limiting voltage applies for the whole
impulse duration. Forward voltages of 1 V or less are normally considered safe. Figure 10 shows that the
lowest current 1 V condition occurs at -40°C with a current of 0.3 A. When the TISPPBL2S is tested with the
rated 10/1000 impulse it would take about 8 ms for the current to decay from 30 A to 0.3 A. Over the -40°C to
85°C temperature range, the TISPPBL2S is specified to have a VF below 1 V within 10 ms.
SLIC protection requirements
This clause discusses the various requirements of the Ericsson Components SLICs detailed on the first page
of this data sheet and compares these to the TISPPBL2S protector parameters. Some SLICs are rated for
0°C to 70°C operation, others for -40°C to 85°C operation. The TISPPBL2S protector is specified for -40°C to
85°C operation and so covers both temperature ranges.
normal operation
Depending on the SLIC type, the maximum SLIC supply voltage rating (VBat) will be -70 V, -80 V or -85 V. The
-85V rating of the TISPPBL2S gate-cathode (VGKRM) matches the highest SLIC voltage rating.
To restore normal operation after the TISPPBL2S has switched on, the minimum switch-off current (holding
current IH) needed is equal to the maximum SLIC short circuit current to ground (d.c. line current together
with the maximum longitudinal current). For the SLICs listed on the first page of this data sheet, the
TISPPBL2S minimum holding current of 140 mA will ensure switch-off after an overvoltage.
overvoltage protection
Ericsson Components specify SLIC withstand capability as a series of stress-time values. Figure 15 shows
the voltage withstand limits of the PBL 3762A SLIC.
In the positive polarity, the PBL 3762A RING or TIP voltage must not exceed +15 V. For 250 ns, the PBL
3762A will be able to withstand a voltage between +10 V and +15 V. For 1 µs, the PBL 3796 will be able to
withstand a voltage between +5 V and +10 V. For 10 ms, the PBL 3796 will be able to withstand a voltage
between +2 V and +5 V. To protect against positive overvoltage, the TISPPBL2S positive limiting voltage must
be equal to or less than these voltage values during the specified time periods.
In the negative polarity, the PBL 3762A RING or TIP voltage must not exceed VBAT - 70. Continuously the
PBL 3762A can withstand a VBAT of -70 V and this implies a maximum peak voltage of -140 V. Figure 15 is
drawn for a VBAT of -50 V and so that the peak voltage becomes -120 V.
For 250 ns, the PBL 3762A will be able to withstand a voltage between VBAT -40V and VBAT -70 V or -90 V
and -120 V in this case. For 1 µs, the PBL 3796 will be able to withstand a voltage between VBAT -20V and
VBAT -40 V or -70 V and -90 V in this case. For 10 ms, the PBL 3796 will be able to withstand a voltage
between VBAT and VBAT -20 V or -50 V and -70 V in this case. By adding a series feed diode in the battery
PRODUCT
10
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
PBL 3762A SLIC RING AND TIP VOLTAGE WITHSTAND
vs
TIME
Voltages (with VBAT set to -50 V) - V
15
0.25 µs
10
1 µs
5
10 ms
0
Time
VBAT
-50
-60
VBAT - 20 V
10 ms
-70
1 µs
-80
D.C. and 10 ms pulse rating increased
to -70 V (independent of VBAT value)
by use of series battery feed diode
VBAT - 40 V
-90
-100
0.25 µs
-110
VBAT - 70 V
-120
AI6XBC
Figure 15. TRANSIENT LIMITS FOR PBL 3762A WITHSTAND VOLTAGE
feed the d.c. and 10 ms voltage withstands increase to -70 V, independent of the actual VBAT value.To protect
against negative overvoltage, the TISPPBL2S negative limiting voltage must be equal to or less than these
voltage values during the specified time periods.
The following table lists the protection requirements of three selections from different SLIC families. Two, the
PBL 3796 and the PBL 3762A, specify voltage withstand. The PBL 3796 specifies the negative voltages in
absolute terms and the PBL 3762A specifies the negative voltages in terms of voltage relative to the battery
supply voltage, VBAT.
Tertiary protection is incorporated in the PBL 386 20/1 SLIC and the withstand is specified in terms of current
into this protection. This type of SLIC also has more time periods specified for the current withstand values.
To co-ordinate the SLIC external secondary protection (TISPPBL2S) and the internal tertiary protection, a
series resistor, RP, is required between the two. The tertiary protection will develop about 1 V and the
withstand current through resistor RP will also develop a voltage. The sum of these voltages will determine
the required limiting voltage level of the TISPPBL2S. A suitable value for RP is 2 Ω.
SLIC withstand comparison
SLIC
PBL 3796
CONDITION
continuous
pulse < 10 ms
PRODUCT
V
PBL 3762A
V
V
-70
+1
VBat (-70 V)
Note 1
Note 1
Note 3
-70
+5
VBat - 20
Note 1
Note 1
Note 3
PBL 386 20/1
V
+2
+5
A
-0.1
Note 6
A
+0.1
-2
+2
Note 5
Note 5
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
11
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
SLIC withstand comparison
SLIC
PBL 3796
CONDITION
V
PBL 3762A
V
V
PBL 386 20/1
V
pulse < 1 ms
pulse < 10 µs
pulse < 1 µs
pulse < 250 ns
Notes:
-90
+10
VBat - 40
Note 1
Note 1
Note 3
-120
+15
VBat - 70
Note 1, 2
Note 1, 2
Note 4
+10
+15
A
A
-5
+5
Note 5
Note 5
-15
+15
Note 5
Note 5
-20
+20
Note 5
Note 5
-20
+20
Note 5
Note 5
1. These voltage rating require a diode to be installed in series with the VBat pin.
2. RF1, RF2 ≥ 20 Ω is also required. Pulse supplied to TIP and RING outside RF1, RF2
3. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -70 V.
A pulse ≤ 1 µs is increased to the greater of |-70 V| or |VBat - 40 V|
4. RF1, RF2 ≥ 20 Ω is also required. Pulse supplied to TIP and RING outside RF1, RF2
5. Pulse is applied to TIP and RING outside RP1 and RP2
6. Permitted continuous voltage for VBat is -75 V
The negative limiting voltage of the TISPPBL2S is defined as a 1 µs, -20 V pulse below the battery voltage
(Figure 2). This value does not exceed any of the voltage withstand levels listed in the SLIC withstand table.
In the positive polarity the TISPBL2S limits the maximum voltage to 8 V in a 1 µs period and between 1 V and
5 V for a 10 ms period. These values do not exceed the values listed in the SLIC withstand table.
A graphical representation is shown in Figure 16. In the positive polarity, the three line types correspond to
the three SLIC types discussed (RP is 2 Ω for the PBL 386 20/1). The two shaded areas represent the
positive and negative maximum limiting voltage levels of the TISPPBL2S as per Figure 2. The negative
voltage withstand capability of the three SLICs is shown relative to their maximum rated battery supply
voltage, VBATM. Figure 16 shows that the TISPPBL2S maximum limiting voltage levels do not exceed the
SLIC voltage withstand ratings.
application circuit
Figure 17 shows a typical TISPPBL2S SLIC card protection circuit. The incoming line conductors, R and T,
connect to the relay matrix via the series over-current protection. Fusible resistors, fuses and positive
temperature coefficient (PTC) resistors can be used for over-current protection. Resistors will reduce the
prospective current from the surge generator for both the TISPPBL2S and the ring/test protector. The
TISP7xxxF3 protector has the same protection voltage for any terminal pair. This protector is used when the
ring generator configuration may be ground or battery-backed. For dedicated ground-backed ringing
generators, the TISP3xxxF3 gives better protection as its inter-conductor protection voltage is twice the
conductor to ground value.
Relay contacts 3a and 3b connect the line conductors to the SLIC via the TISPPBL2S protector. Closing
contacts 3a and 3b connects the TISPPBL2S protector in parallel with the ring/test protector. As the ring/test
protector requires much higher voltages than the TISPPBL2S to operate, it will only operate when the
contacts 3a and 3b are open. Both protectors will divert the same levels of peak surge current and their
required current ratings should be similar. The TISPPBL2S protector gate reference voltage comes from the
SLIC negative supply (VBAT). A 220 nF gate capacitor sources the high gate current pulses caused by fast
PRODUCT
12
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
PBL 3xxx SLIC VOLTAGE WITHSTAND
AND TISPPBL2S VOLTAGE LIMITING
vs
TIME
40
30
PBL 386 20/1
PBL 3762A
PBL 3796
20
10
TISPPBL2S
Voltage - V
0
10 µs
1 µs
0.25 µs
VBATM
1 ms
10 ms
Time
TISPPBL2S
VBATM - 10
VBATM - 20
PBL 386 20/1
VBATM - 30
VBATM - 40
VBATM - 50
PBL 3796
VBATM - 60
PBL 3762A
AI6XBDS
VBATM - 70
Figure 16. SLIC VOLTAGE WITHSTAND AND TISPPBL2S PROTECTION LEVELS
TIP
WIRE
OVERCURRENT
PROTECTION
RING/TEST
PROTECTION
TEST
RELAY
RING
RELAY
SLIC
PROTECTION
RP
Th1
R1a
SLIC
RELAY
S3a
Th4
S2a
S1a
PBL
3xxx
SLIC
Th3
RING
WIRE
R1b
Th2
TISP
3xxxF3
OR
7xxxF3
S3b
S1b
TEST
EQUIPMENT
S2b
TISP
PBL2S
Th5
RP
C1
220 nF
VBAT
RP IS USED WHEN THE SLIC
HAS TERTIARY PROTECTION
RING
GENERATOR
AI6XAPS
Figure 17. TYPICAL APPLICATION CIRCUIT
rising impulses. When the SLIC has internal tertiary protection (e.g. PBL 386 21/1), then the two RP resistors
need to be added for protection co-ordination.
PRODUCT
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.
13
TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
MECHANICAL DATA
D008
plastic small-outline package
This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
D008
8-pin Small Outline Microelectronic Standard
Package MS-012, JEDEC Publication 95
5,00 (0.197)
4,80 (0.189)
6,20 (0.244)
5,80 (0.228)
8
7
6
5
1
2
3
4
INDEX
4,00 (0.157)
3,81 (0.150)
7° NOM
3 Places
1,75 (0.069)
1,35 (0.053)
0,203 (0.008)
0,102 (0.004)
0,79 (0.031)
0,28 (0.011)
5,21 (0.205)
4,60 (0.181)
0,50 (0.020)
x 45°NOM
0,25 (0.010)
7° NOM
4 Places
0,51 (0.020)
0,36 (0.014)
8 Places
Pin Spacing
1,27 (0.050)
(see Note A)
6 Places
0,229 (0.0090)
0,190 (0.0075)
4° ± 4°
1,12 (0.044)
0,51 (0.020)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
Leads are within 0,25 (0.010) radius of true position at maximum material condition.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006).
Lead tips to be planar within ±0,051 (0.002).
PRODUCT
14
MDXXAAC
INFORMATION
AUGUST 1999 - REVISED AUGUST 2002
Specifications are subject to change without notice.