DFPMU-DP Floating Point Coprocessor Double Precision ver 3.03 OVERVIEW DFPMU-DP is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. DFPMU-DP directly replaces C software functions, by equivalent, very fast hardware operations, which significantly accelerate system performance. It doesn’t require any programming, so it also doesn’t require any modifications made in the main software. Everything is done automatically during software compilation by the DFPMU-DP C driver. allows save silicon space and provides exact configuration required by certain application. DFPMU-DP is a technology independent design that can be implemented in a variety of process technologies. APPLICATIONS ● Math coprocessors ● DSP algorithms ● Embedded arithmetic coprocessor ● Fast data processing & control DFPMU-DP was designed to operate with DCD’s DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered together with the DFPMU-DP package. DFPMU-DP uses the specialized CORDIC and standard algorithms to compute math functions. It supports addition, subtraction, multiplication, division, square root, comparison, and trigonometric functions: sine, cosine, tangent and arctangent. It has builtin conversion instructions from integer type to floating point type and vice versa. The input numbers format is according to IEEE-754 standard. DFPMU-DP supports double and single precision real numbers, 8-bit, 16-bit and 32-bit integers. DFPMU-DP is prepared to use with 8-, 16- and 32-bit processors. Each floating point function can be turned on/off at configuration level providing the flexible scalability of DFPMU-DP module. It All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. KEY FEATURES ● Direct replacement for C double, float software functions such as: +, -, *, /,==, !=,>=, <=, <, > ● Fully configurable ● Fully synthesizable, static synchronous design with no internal tri-states ● Configurability of all available functions ● C interface supplied for all popular compilers: GNU C/C++, 8051 compilers DELIVERABLES ♦ ● No programming required ● IEEE-754 Double precision real format support – double type ● IEEE-754 Single precision real format support – float type ♦ ● 8-bit, 16-bit 32-bit and 52-bit integers format supported – integer types ● Flexible arguments and result registers location ♦ ● Performs the following functions: ○ FADD, FSUB – addition, subtraction ○ FMUL, FDIV – multiplication, division ○ FSQRT – square root ○ FXAM – examine input data ○ FUCOM – comparison ○ FSIN, FCOS – sine, cosine ○ FTAN – tangent ○ FATAN – arctangent ○ FCLD, FILD – 8-bit, 16-bit integer to dou- ♦ ♦ ♦ Source code: ◊ VHDL Source Code or/and ◊ VERILOG Source Code or/and ◊ Encrypted Netlist or/and ◊ plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance ● ● ● Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support ble ○ FLLD, FELD – 32-bit, 52-bit integer to double ○ FCST, FIST – double to 8-bit, 16-bi inte- ger ○ FLST, FEST – double to 32-bit, 52-bit in- teger ○ FFLD – float to double ○ FFST – double to float ● Exceptions built-in routines ● Masks each exception indicator: ○ Precision lack PE ○ Underflow result UE ○ Overflow result OE ○ Invalid operand IE ○ Division by zero ZE ○ Denormal operand DE All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. LICENSING PINS DESCRIPTION Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time of use limitations. ● Single Design license for ○ VHDL, Verilog source code called HDL Source ○ Encrypted, or plain text EDIF called Netlist ● Unlimited Designs license for ○ HDL Source ○ Netlist ● Upgrade from ○ Netlist to HDL Source ○ Single Design to Unlimited Designs SYMBOL datai(31:0)1 datao(31:0)1 addr(4:2)2 we irq PIN TYPE DESCRIPTION clk Input rst Input Global system reset cs Input Chip select for read/write Input Data bus input Input Register address to read/write Input Data write enable datai[31:0]1 2 addr[4:2] we Global system clock datao[31:0]1 Output Data bus output irq Output Interrupt request indicator 1 – data bus can be configured as 8-, 16- or 32- bit depends on processor’s bus size 2 – address bus is aligned to work with 8- (3:0), 16(3:1) or 32- (4:2) bit processors BLOCK DIAGRAM Mantissa – performs operations on mantissa part of number. The addition, subtraction, multiplication, division, square root, comparison and conversion operations are executed in this module. It contains mantissas and work registers. CORDIC – performs trigonometric operations on input data. The sine, cosine, tangent and arctangent operations are executed in this module. It contains three work registers. datai(31:0)1 datao(31:0)1 irq Mantissa Interface addr(4:2)2 we cs cs rst clk Align Exponent Shifter CORDIC clk rst Control Unit Exponent – performs operations on exponent part of number. The addition, subtraction, shifting, comparison and conversion operations are executed in this module. It contains exponents and work registers. Align – performs the numbers analyze against IEEE-754 standard compliance. InAll trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. formation about the data classes are passed as result to appropriate internal module. Shifter – performs mantissa shifting during normalization, denormalization operations. Information about shifted-out bits are stored for rounding process. Control Unit – manages execution of all instructions and internal operation required to execute particular function. Interface – makes interface between external device and DFPMU-DP internal 32-bit modules. It contains data, control and status registers. It can be configured to work with 8-, 16- and 32-bit processors. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route (all key features have been included): Speed Logic Cells Fmax grade CYCLONE -6 7070 77 MHz CYCLONE-II -6 7080 68 MHz STRATIX -5 7070 82 MHz STRATIX-II -3 5290 109 MHz Core performance in ALTERA® devices Device DFPMU-DP floating point instructions performance has been compared to standard C library functions delivered with every commercial C compiler. Each program was executed in the same system environments. Number of clock periods were measured between input data loading into work registers and output result storing after operation. The results are placed in table below. Improvement has been computed as number of: (NIOS-II CLK) divided by (NIOS-II+DFPMUDP CLK), required to execute particular instruction. IEEE-754 FP Instruction Addition Subtraction Multiplication Division Square Root Sine Cosine Tangent Arcs Tangent Average speed improvement: Improvement 12.0 11.7 10.6 15.0 21.5 52.0 60.8 97.9 78.7 38.3 More details are available in core documentation. The following table gives a survey about the 32-bit NIOS-II+DFPMU-DP performance compared to 32-bit NIOS-II. Device NIOS-II NIOS-II+DFPMU (arithmetic) NIOS-II+DFPMU (trigonometric) NIOS-II+DFPMU (overall) All trademarks mentioned in this document are trademarks of their respective owners. Improvement 1.0 14.1 72.4 38.8 http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. 72,4 50 38,8 40 30 20 10,2 10 1 0 32-bit NIOS-II NIOS-II+DFPMU-DP (arithmetic) NIOS-II+DFPMU-DP (trigonometric) NIOS-II+DFPMU-DP (overall) All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND n fo @ d c d .p l e-mail: [email protected] tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: ttp://www.dcd.pl/apartn.php Please check hhttp://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.