TI MSP430F22X2

MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
•
•
•
•
•
•
•
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 270 µA at 1 MHz, 2.2 V
– Standby Mode: 0.7 µA
– Off Mode (RAM Retention): 0.1 µA
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
– Internal Very-Low-Power Low-Frequency
Oscillator
– 32-kHz Crystal
– High-Frequency (HF) Crystal up to 16 MHz
– Resonator
– External Digital Clock Source
– External Resistor
16-Bit Timer_A With Three Capture/Compare
Registers
16-Bit Timer_B With Three Capture/Compare
Registers
Universal Serial Communication Interface
– Enhanced UART Supporting Auto-Baudrate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C™
10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference,
Sample-and-Hold, Autoscan, and Data Transfer
Controller
•
•
•
•
•
•
•
•
Two Configurable Operational Amplifiers
(MSP430F22x4 Only)
Brownout Detector
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Bootstrap Loader
On-Chip Emulation Module
Family Members Include:
– MSP430F2232
– 8KB + 256B Flash Memory
– 512B RAM
– MSP430F2252
– 16KB + 256B Flash Memory
– 512B RAM
– MSP430F2272
– 32KB + 256B Flash Memory
– 1KB RAM
– MSP430F2234
– 8KB + 256B Flash Memory
– 512B RAM
– MSP430F2254
– 16KB + 256B Flash Memory
– 512B RAM
– MSP430F2274
– 32KB + 256B Flash Memory
– 1KB RAM
Available in a 38-Pin Thin Shrink Small-Outline
Package (TSSOP) (DA), 40-Pin QFN Package
(RHA), and 49-Pin Ball Grid Array (YFF) (See
Table 1)
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide, Literature
Number SLAU144
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2011, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430F22xx series is an ultra-low-power mixed signal microcontroller with two built-in 16-bit timers, a
universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer
controller (DTC), two general-purpose operational amplifiers in the MSP430F22x4 devices, and 32 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front
ends are another area of application.
Table 1. Available Options
PACKAGED DEVICES (1) (2)
TA
PLASTIC 49-PIN BGA
(YFF)
PLASTIC 38-PIN TSSOP
(DA)
PLASTIC 40-PIN QFN
(RHA)
MSP430F2232IYFF
MSP430F2232IDA
MSP430F2232IRHA
MSP430F2252IYFF
MSP430F2252IDA
MSP430F2252IRHA
MSP430F2272IYFF
MSP430F2272IDA
MSP430F2272IRHA
MSP430F2234IYFF
MSP430F2234IDA
MSP430F2234IRHA
MSP430F2254IYFF
MSP430F2254IDA
MSP430F2254IRHA
-40°C to 85°C
MSP430F2274IYFF
-40°C to 105°C
(1)
(2)
MSP430F2274IDA
MSP430F2274IRHA
MSP430F2232TDA
MSP430F2232TRHA
MSP430F2252TDA
MSP430F2252TRHA
MSP430F2272TDA
MSP430F2272TRHA
MSP430F2234TDA
MSP430F2234TRHA
MSP430F2254TDA
MSP430F2254TRHA
MSP430F2274TDA
MSP430F2274TRHA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
• Debugging and Programming Interface
– MSP-FET430UIF (USB)
– MSP-FET430PIF (Parallel Port)
• Debugging and Programming Interface with Target Board
– MSP-FET430U38 (DA package)
• Production Programmer
– MSP-GANG430
2
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
MSP430F22x2 Device Pinout, DA Package
TEST/SBWTCK
1
38
P1.7/TA2/TDO/TDI
DVCC
2
37
P1.6/TA1/TDI
P2.5/ROSC
3
36
P1.5/TA0/TMS
DVSS
4
35
P1.4/SMCLK/TCK
XOUT/P2.7
5
34
P1.3/TA2
XIN/P2.6
6
33
P1.2/TA1
RST/NMI/SBWTDIO
7
32
P1.1/TA0
P2.0/ACLK/A0
8
31
P1.0/TACLK/ADC10CLK
P2.1/TAINCLK/SMCLK/A1
9
30
P2.4/TA2/A4/VREF+/VeREF+
P2.2/TA0/A2
10
29
P2.3/TA1/A3/VREF−/VeREF−
P3.0/UCB0STE/UCA0CLK/A5
11
28
P3.7/A7/OA1I2
P3.1/UCB0SIMO/UCB0SDA
12
27
P3.6/A6/OA0I2
P3.2/UCB0SOMI/UCB0SCL
13
26
P3.5/UCA0RXD/UCA0SOMI
P3.3/UCB0CLK/UCA0STE
14
25
P3.4/UCA0TXD/UCA0SIMO
AVSS
15
24
P4.7/TBCLK
AVCC
16
23
P4.6/TBOUTH/A15
P4.0/TB0
17
22
P4.5/TB2/A14
P4.1/TB1
18
21
P4.4/TB1/A13
P4.2/TB2
19
20
P4.3/TB0/A12
MSP430F22x4 Device Pinout, DA Package
TEST/SBWTCK
1
38
P1.7/TA2/TDO/TDI
DVCC
2
37
P1.6/TA1/TDI
P2.5/ROSC
3
36
P1.5/TA0/TMS
DVSS
4
35
P1.4/SMCLK/TCK
XOUT/P2.7
5
34
P1.3/TA2
XIN/P2.6
6
33
P1.2/TA1
RST/NMI/SBWTDIO
7
32
P1.1/TA0
P2.0/ACLK/A0/OA0I0
8
31
P1.0/TACLK/ADC10CLK
P2.1/TAINCLK/SMCLK/A1/OA0O
9
30
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
P2.2/TA0/A2/OA0I1
10
29
P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
P3.0/UCB0STE/UCA0CLK/A5
11
28
P3.7/A7/OA1I2
P3.1/UCB0SIMO/UCB0SDA
12
27
P3.6/A6/OA0I2
P3.2/UCB0SOMI/UCB0SCL
13
26
P3.5/UCA0RXD/UCA0SOMI
P3.3/UCB0CLK/UCA0STE
14
25
P3.4/UCA0TXD/UCA0SIMO
AVSS
15
24
P4.7/TBCLK
AVCC
16
23
P4.6/TBOUTH/A15/OA1I3
P4.0/TB0
17
22
P4.5/TB2/A14/OA0I3
P4.1/TB1
18
21
P4.4/TB1/A13/OA1O
P4.2/TB2
19
20
P4.3/TB0/A12/OA0O
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
TEST/SBWTCK
DVCC
DVCC
P2.5/ROSC
MSP430F22x2 Device Pinout, RHA Package
39 38 37 36 35 34 33 32
DVSS
1
30
P1.1/TA0
XOUT/P2.7
2
29
P1.0/TACLK/ADC10CLK
XIN/P2.6
3
28
P2.4/TA2/A4/VREF+/VeREF+
DVSS
4
27
P2.3/TA1/A3/VREF−/VeREF−
RST/NMI/SBWTDIO
5
26
P3.7/A7
P2.0/ACLK/A0
6
25
P3.6/A
P2.1/TAINCLK/SMCLK/A1
7
24
P3.5/UCA0RXD/UCA0SOMI
P2.2/TA0/A2
8
23
P3.4/UCA0TXD/UCA0SIMO
P3.0/UCB0STE/UCA0CLK/A5
9
22
P4.7/TBCLK
10
21
P4.6/TBOUTH/A15
P3.1/UCB0SIMO/UCB0SDA
4
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P4.5/TB2/A14
P4.4/TB1/A13
P4.3/TB0/A12
P4.2/TB2
P4.1/TB1
P4.0/TB0
AVCC
AVSS
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
12 13 14 15 16 17 18 19
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
TEST/SBWTCK
DVCC
DVCC
P2.5/ROSC
MSP430F22x4 Device Pinout, RHA Package
39 38 37 36 35 34 33 32
P1.1/TA0
DVSS
1
30
XOUT/P2.7
2
29
P1.0/TACLK/ADC10CLK
XIN/P2.6
3
28
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
DVSS
4
27
P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
RST/NMI/SBWTDIO
5
26
P3.7/A7/OA1I2
P2.0/ACLK/A0/OA0I0
6
25
P3.6/A6/OA0I2
P2.1/TAINCLK/SMCLK/A1/OA0O
7
24
P3.5/UCA0RXD/UCA0SOMI
P2.2/TA0/A2/OA0I1
8
23
P3.4/UCA0TXD/UCA0SIMO
P3.0/UCB0STE/UCA0CLK/A5
9
22
P4.7/TBCLK
10
21
P4.6/TBOUTH/A15/OA1I3
P3.1/UCB0SIMO/UCB0SDA
Copyright © 2006–2011, Texas Instruments Incorporated
P4.5/TB2/A14/OA0I3
P4.4/TB1/A13/OA1O
P4.3/TB0/A12/OA0O
P4.2/TB2
P4.1/TB1
P4.0/TB0
AVCC
AVSS
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
12 13 14 15 16 17 18 19
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
TOP VIEW
D1
D2
D3
D4
D5
D6
D7
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
G1
G2
G3
G4
G5
G6
G7
Package Dimensions
The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this
data sheet for more details.
Table 2. YFF Package Dimensions
6
PACKAGED DEVICES
D
E
MSP430F22x2
MSP430F22x4
3.33 ± 0.03 mm
3.49 ± 0.03 mm
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
MSP430F22x2 Functional Block Diagram
VCC
P1.x/P2.x
VSS
2x8
XIN
P3.x/P4.x
2x8
XOUT
Basic Clock
System+
ACLK
SMCLK
MCLK
Flash
RAM
32kB
16kB
8kB
1kB
512B
512B
ADC10
10−Bit
Ports P1/P2
Ports P3/P4
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
12
Channels,
Autoscan,
DTC
2x8 I/O
pull−up/down
resistors
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
Timer_B3
JTAG
Interface
Watchdog
WDT+
Brownout
Protection
15/16−Bit
Timer_A3
3 CC
Registers
Spy−Bi Wire
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
RST/NMI
MSP430F22x4 Functional Block Diagram
VCC
P1.x/P2.x
VSS
2x8
XIN
P3.x/P4.x
2x8
XOUT
Basic Clock
System+
ACLK
Flash
ADC10
10−Bit
Ports P1/P2
Ports P3/P4
OA0, OA1
SMCLK
32kB
16kB
8kB
MCLK
16MHz
CPU
incl. 16
Registers
RAM
1kB
512B
512B
12
Channels,
Autoscan,
DTC
2 Op Amps
2x8 I/O
pull−up/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
Timer_B3
Brownout
Protection
Watchdog
WDT+
15/16−Bit
Spy−Bi Wire
Timer_A3
3 CC
Registers
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
RST/NMI
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Table 3. Terminal Functions, MSP430F22x2
TERMINAL
NAME
NO.
I/O
YFF
DA
RHA
F2
31
29
DESCRIPTION
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK
I/O
Timer_A, clock signal TACLK input
ADC10, conversion clock
P1.1/TA0
G2
32
30
I/O
P1.2/TA1
E2
33
31
I/O
P1.3/TA2
G1
34
32
I/O
P1.4/SMCLK/TCK
F1
35
33
I/O
P1.5/TA0/TMS
E1
36
34
I/O
P1.6/TA1/TDI/TCLK
E3
37
35
I/O
P1.7/TA2/TDO/TDI (1)
D2
38
36
I/O
P2.0/ACLK/A0
A4
8
6
I/O
P2.1/TAINCLK/SMCLK/A1
B4
9
7
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin / SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin / Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin / Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin / Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin / ACLK output
ADC10, analog input A0
General-purpose digital I/O pin
Timer_A, clock signal at INCLK, SMCLK signal output
ADC10, analog input A1
General-purpose digital I/O pin
P2.2/TA0/A2
A5
10
8
I/O
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2
General-purpose digital I/O pin
P2.3/TA1/A3/VREF-/ VeREF-
F3
29
27
I/O
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3 / negative reference voltage output/input
P2.4/TA2/A4/VREF+/ VeREF+
G3
30
28
I/O
P2.5/ROSC
C2
3
40
I/O
XIN/P2.6
A2
6
3
I/O
XOUT/P2.7
A1
5
2
I/O
P3.0/UCB0STE/UCA0CLK/
A5
B5
11
9
I/O
General-purpose digital I/O pin / Timer_A, compare: OUT2 output
ADC10, analog input A4 / positive reference voltage output/input
General-purpose digital I/O pin
Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
General-purpose digital I/O pin
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
General-purpose digital I/O pin
USCI_B0 slave transmit enable / USCI_A0 clock input/output
ADC10, analog input A5
P3.1/UCB0SIMO/
UCB0SDA
A6
12
10
I/O
P3.2/UCB0SOMI/UCB0SCL
A7
13
11
I/O
(1)
(2)
8
General-purpose digital I/O pin
USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
General-purpose digital I/O pin
USCI_B0 slave out/master in SPI mode, SCL I2C clock in I2C mode
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NAME
NO.
I/O
YFF
DA
RHA
P3.3/UCB0CLK/UCA0STE
B6
14
12
I/O
P3.4/UCA0TXD/
UCA0SIMO
G6
25
23
I/O
P3.5/UCA0RXD/
UCA0SOMI
G5
26
24
I/O
P3.6/A6
F4
27
25
I/O
P3.7/A7
G4
28
26
I/O
P4.0/TB0
D6
17
15
I/O
P4.1/TB1
D7
18
16
I/O
P4.2/TB2
E6
19
17
I/O
P4.3/TB0/A12
E7
20
18
I/O
DESCRIPTION
General-purpose digital I/O pin
USCI_B0 clock input/output / USCI_A0 slave transmit enable
General-purpose digital I/O pin
USCI_A0 transmit data output in UART mode, slave in/master out in SPI
mode
General-purpose digital I/O pin
USCI_A0 receive data input in UART mode, slave out/master in SPI mode
General-purpose digital I/O pin
ADC10 analog input A6
General-purpose digital I/O pin
ADC10 analog input A7
General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
General-purpose digital I/O pin
P4.4/TB1/A13
F7
21
19
I/O
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
General-purpose digital I/O pin
P4.5/TB2/A14
F6
22
20
I/O
Timer_B, compare: OUT2 output
ADC10 analog input A14
General-purpose digital I/O pin
P4.6/TBOUTH/A15
G7
23
21
I/O
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
P4.7/TBCLK
F5
24
22
I/O
RST/NMI/SBWTDIO
B3
7
5
I
TEST/SBWTCK
D1
1
37
I
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
C1,
D3,
D4,
E4, E5
2
38, 39
Digital supply voltage
AVCC
C6,
C7,
D5
16
14
Analog supply voltage
DVSS
A3,
B1,
B2,
C3,
C4
4
1, 4
Digital ground reference
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MSP430F22x2
MSP430F22x4
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Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NAME
NO.
I/O
YFF
DA
RHA
AVSS
B7,
C5
15
13
QFN Pad
NA
NA
Pad
10
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DESCRIPTION
Analog ground reference
NA
QFN package pad; connection to DVSS recommended.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Table 4. Terminal Functions, MSP430F22x4
TERMINAL
NAME
NO.
I/O
YFF
DA
RHA
F2
31
29
DESCRIPTION
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK
I/O
Timer_A, clock signal TACLK input
ADC10, conversion clock
P1.1/TA0
G2
32
30
I/O
P1.2/TA1
E2
33
31
I/O
P1.3/TA2
G1
34
32
I/O
P1.4/SMCLK/TCK
F1
35
33
I/O
P1.5/TA0/TMS
E1
36
34
I/O
P1.6/TA1/TDI/TCLK
E3
37
35
I/O
P1.7/TA2/TDO/TDI (1)
D2
38
36
I/O
P2.0/ACLK/A0/OA0I0
A4
8
6
I/O
P2.1/TAINCLK/SMCLK/
A1/OA0O
B4
9
7
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin / SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin / Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin / Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin / Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin / ACLK output
ADC10, analog input A0 / OA0, analog input IO
General-purpose digital I/O pin / Timer_A, clock signal at INCLK
SMCLK signal output
ADC10, analog input A1 / OA0, analog output
General-purpose digital I/O pin
P2.2/TA0/A2/OA0I1
A5
10
8
I/O
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2 / OA0, analog input I1
General-purpose digital I/O pin
P2.3/TA1/A3/
VREF-/VeREF-/
OA1I1/OA1O
F3
29
27
I/O
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3 / negative reference voltage output/input
OA1, analog input I1 / OA1, analog output
General-purpose digital I/O pin / Timer_A, compare: OUT2 output
P2.4/TA2/A4/
VREF+/VeREF+/OA1I0
G3
30
28
I/O
ADC10, analog input A4 / positive reference voltage output/input
OA1, analog input I/O
P2.5/ROSC
C2
3
40
I/O
XIN/P2.6
A2
6
3
I/O
XOUT/P2.7
A1
5
2
I/O
General-purpose digital I/O pin
Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
General-purpose digital I/O pin
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
General-purpose digital I/O pin
P3.0/UCB0STE/UCA0CLK/
A5
B5
11
9
I/O
USCI_B0 slave transmit enable / USCI_A0 clock input/output
ADC10, analog input A5
P3.1/UCB0SIMO/
UCB0SDA
(1)
(2)
A6
12
10
I/O
General-purpose digital I/O pin
USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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MSP430F22x4
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Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NAME
NO.
I/O
YFF
DA
RHA
P3.2/UCB0SOMI/UCB0SCL
A7
13
11
I/O
P3.3/UCB0CLK/UCA0STE
B6
14
12
I/O
P3.4/UCA0TXD/
UCA0SIMO
G6
25
23
I/O
P3.5/UCA0RXD/
UCA0SOMI
G5
26
24
I/O
P3.6/A6/OA0I2
F4
27
25
I/O
P3.7/A7/OA1I2
G4
28
26
I/O
P4.0/TB0
D6
17
15
I/O
P4.1/TB1
D7
18
16
I/O
P4.2/TB2
E6
19
17
I/O
P4.3/TB0/A12/OA0O
E7
20
18
I/O
DESCRIPTION
General-purpose digital I/O pin
USCI_B0 slave out/master in SPI mode, SCL I2C clock in I2C mode
General-purpose digital I/O pin
USCI_B0 clock input/output / USCI_A0 slave transmit enable
General-purpose digital I/O pin
USCI_A0 transmit data output in UART mode, slave in/master out in SPI
mode
General-purpose digital I/O pin
USCI_A0 receive data input in UART mode, slave out/master in SPI mode
General-purpose digital I/O pin
ADC10 analog input A6 / OA0 analog input I2
General-purpose digital I/O pin
ADC10 analog input A7 / OA1 analog input I2
General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12 / OA0 analog output
General-purpose digital I/O pin
P4.4/TB1/A13/OA1O
F7
21
19
I/O
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13 / OA1 analog output
General-purpose digital I/O pin
P4.5/TB2/A14/OA0I3
F6
22
20
I/O
Timer_B, compare: OUT2 output
ADC10 analog input A14 / OA0 analog input I3
General-purpose digital I/O pin
P4.6/TBOUTH/A15/OA1I3
G7
23
21
I/O
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15 / OA1 analog input I3
P4.7/TBCLK
F5
24
22
I/O
RST/NMI/SBWTDIO
B3
7
5
I
TEST/SBWTCK
D1
1
37
I
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
C1,
D3,
D4,
E4, E5
2
38, 39
Digital supply voltage
AVCC
C6,
C7,
D5
16
14
Analog supply voltage
12
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MSP430F22x4
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Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
YFF
DA
RHA
DVSS
A3,
B1,
B2,
C3,
C4
4
1, 4
Digital ground reference
AVSS
B7,
C5
15
13
Analog ground reference
QFN Pad
NA
NA
Pad
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NA
QFN package pad; connection to DVSS recommended.
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SHORT-FORM DESCRIPTION
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 5 shows examples of the three types of
instruction formats; Table 6 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
Table 5. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
INSTRUCTION FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional/conditional
Table 6. Address Mode Descriptions
ADDRESS MODE
SYNTAX
EXAMPLE
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
14
D
(2)
Register
(1)
(2)
S
(1)
OPERATION
S = source
D = destination
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Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
– ACLK remains active.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– ACLK remains active.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 7. Interrupt Vector Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
Timer_B3
TBCCR0 CCIFG (4)
maskable
0FFFAh
29
Timer_B3
TBCCR1 and TBCCR2 CCIFGs,
TBIFG (2) (4)
maskable
0FFF8h
28
0FFF6h
27
Watchdog Timer
WDTIFG
maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (2) (4)
maskable
0FFF0h
24
USCI_A0/USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG (2)
maskable
0FFEEh
23
USCI_A0/USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG (2)
maskable
0FFECh
22
ADC10
ADC10IFG (4)
maskable
0FFEAh
21
0FFE8h
20
(1)
(2)
(3)
(4)
(5)
(6)
16
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(2) (4)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7 (2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(5)
0FFDEh
15
(6)
0FFDCh to 0FFC0h
14 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
Interrupt flags are located in the module.
This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
rw-0, 1
rw-(0), (1)
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 8. Interrupt Enable 1
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
Table 9. Interrupt Enable 2
Address
7
6
5
4
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
Table 10. Interrupt Flag Register 1
Address
7
6
4
3
2
1
0
02h
UTXIFG0
URXIFG0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-1
rw-0
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
WDTIFG
OFIFG
RSTIFG
PORIFG
NMIIFG
5
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Power-on reset interrupt flag. Set on VCC power up.
Set via RST/NMI pin
Table 11. Interrupt Flag Register 2
Address
7
6
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
5
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
USCI_A0 receive-interrupt flag
USCI_A0 transmit-interrupt flag
USCI_B0 receive-interrupt flag
USCI_B0 transmit-interrupt flag
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Memory Organization
Table 12. Memory Organization
MSP430F223x
MSP430F225x
MSP430F227x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB Flash
0FFFFh-0FFC0h
0FFFFh-0E000h
16KB Flash
0FFFFh-0FFC0h
0FFFFh-0C000h
32KB Flash
0FFFFh-0FFC0h
0FFFFh-08000h
Information memory
Size
Flash
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
Boot memory
Size
ROM
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
Size
512 Byte
03FFh-0200h
512 Byte
03FFh-0200h
1KB
05FFh-0200h
16-bit
8-bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
RAM
Peripherals
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide, literature number SLAU319.
Table 13. BSL Function Pins
BSL FUNCTION
DA PACKAGE PINS
RHA PACKAGE PINS
YFF PACKAGE PINS
Data transmit
32 - P1.1
30 - P1.1
G3 - P1.1
Data receive
10 - P2.2
8 - P2.2
A5 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal
very-low-power LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 14. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY
CALIBRATION REGISTER
SIZE
ADDRESS
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
CALBC1_8MHZ
byte
010FDh
1 MHz
8 MHz
12 MHz
16 MHz
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
CALBC1_16MHZ
byte
010F9h
CALDCO_16MHZ
byte
010F8h
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 15. Timer_A3 Signal Connections
INPUT PIN NUMBER
DA
RHA
YFF
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
31 - P1.0
29 - P1.0
F2 - P1.0
TACLK
TACLK
ACLK
ACLK
Timer
NA
CCR0
TA0
OUTPUT PIN NUMBER
DA
RHA
YFF
SMCLK
SMCLK
9 - P2.1
7 - P2.1
B4 - P2.1
TAINCLK
INCLK
32 - P1.1
30 - P1.1
G2 - P1.1
TA0
CCI0A
32 - P1.1
30 - P1.1
G2 - P1.1
10 - P2.2
8 - P2.2
A5 - P2.2
TA0
CCI0B
10 - P2.2
8 - P2.2
A5 - P2.2
36 - P1.5
34 - P1.5
E1 - P1.5
33 - P1.2
31 - P1.2
E2 - P1.2
VSS
GND
VCC
VCC
33 - P1.2
31 - P1.2
E2 - P1.2
TA1
CCI1A
29 - P2.3
27 - P2.3
F3 - P2.3
TA1
CCI1B
29 - P2.3
27 - P2.3
F3 - P2.3
VSS
GND
37 - P1.6
35 - P1.6
E3 - P1.6
VCC
VCC
34 - P1.3
32 - P1.3
G1 - P1.3
34 - P1.3
20
32 - P1.3
G1 - P1.3
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CCR1
CCR2
TA1
TA2
CCI2A
ACLK
(internal)
TA2
CCI2B
30 - P2.4
28 - P2.4
G3 - P2.4
VSS
GND
38 - P1.7
36 - P1.7
D2 - P1.7
VCC
VCC
Copyright © 2006–2011, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 16. Timer_B3 Signal Connections
INPUT PIN NUMBER
DA
RHA
YFF
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
24 - P4.7
22 - P4.7
F5 - P4.7
TBCLK
TBCLK
ACLK
ACLK
Timer
NA
CCR0
TB0
SMCLK
SMCLK
24 - P4.7
22 - P4.7
F5 - P4.7
TBCLK
INCLK
17 - P4.0
15 - P4.0
D6 - P4.0
TB0
CCI0A
20 - P4.3
18 - P4.3
E7 - P4.3
TB0
CCI0B
VSS
GND
VCC
VCC
18 - P4.1
16 - P4.1
D7 - P4.1
TB1
CCI1A
21 - P4.4
19 - P4.4
F7 - P4.4
TB1
CCI1B
VSS
GND
VCC
VCC
19 - P4.2
17 - P4.2
E6 - P4.2
TB2
CCI2A
ACLK
(internal)
CCI2B
VSS
GND
VCC
VCC
CCR1
CCR2
TB1
TB2
OUTPUT PIN NUMBER
DA
RHA
YFF
17 - P4.0
15 - P4.0
D6 - P4.0
20 - P4.3
18 - P4.3
E7 - P4.3
18 - P4.1
16 - P4.1
D7 - P4.1
21 - P4.4
19 - P4.4
F7 - P4.4
19 - P4.2
17 - P4.2
E6 - P4.2
22 - P4.5
20 - P4.5
F6 - P4.5
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Operational Amplifier (OA) (MSP430F22x4 only)
The MSP430F22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and
output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA
op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
Table 17. OA0 Signal Connections
ANALOG INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE INPUT NAME
DA
RHA
YFF
8 - A0
6 - A0
B4 - A0
OA0I0
OAxI0
10 - A2
8 - A2
B5 - A2
OA0I1
OA0I1
10 - A2
8 - A2
B5 - A2
OA0I1
OAxI1
27 - A6
25 - A6
F4 - A6
OA0I2
OAxIA
22 - A14
20 - A14
F6 - A14
OA0I3
OAxIB
DEVICE INPUT SIGNAL
MODULE INPUT NAME
Table 18. OA1 Signal Connections
ANALOG INPUT PIN NUMBER
22
DA
RHA
YFF
30 - A4
28 - A4
G3 - A4
OA1I0
OAxI0
10 - A2
8 - A2
B5 - A2
OA0I1
OA0I1
29 - A3
27 - A3
F3 - A3
OA1I1
OAxI1
28 - A7
26 - A7
G4 - A7
OA1I2
OAxIA
23 - A15
21 - A15
G7 - A15
OA1I3
OAxIB
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Peripheral File Map
Table 19. Peripherals With Word Access
MODULE
ADC10
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
ADC10SA
1BCh
ADC memory
ADC10MEM
1B4h
ADC control register 1
ADC10CTL1
1B2h
ADC control register 0
ADC10CTL0
1B0h
ADC analog enable 0
ADC10AE0
04Ah
ADC data transfer start address
ADC analog enable 1
Timer_B
ADC10AE1
04Bh
ADC data transfer control register 1
ADC10DTC1
049h
ADC data transfer control register 0
ADC10DTC0
048h
Capture/compare register
TBCCR2
0196h
Capture/compare register
TBCCR1
0194h
Capture/compare register
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control
TBCCTL2
0186h
Capture/compare control
TBCCTL1
0184h
Capture/compare control
TBCCTL0
0182h
Timer_B control
Timer_A
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register
TACCR2
0176h
Capture/compare register
TACCR1
0174h
Capture/compare register
TACCR0
0172h
TAR
0170h
Capture/compare control
TACCTL2
0166h
Capture/compare control
TACCTL1
0164h
Capture/compare control
TACCTL0
0162h
TACTL
0160h
Timer_A register
Timer_A control
Timer_A interrupt vector
Flash Memory
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
FCTL1
0128h
WDTCTL
0120h
Flash control 1
Watchdog Timer+
Watchdog/timer control
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Table 20. Peripherals With Byte Access
MODULE
OA1 (MSP430F22x4 only)
OA0 (MSP430F22x4 only)
USCI_B0
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
Operational Amplifier 1 control register 1
OA1CTL1
0C3h
Operational Amplifier 1 control register 1
OA1CTL0
0C2h
Operational Amplifier 0 control register 1
OA0CTL1
0C1h
Operational Amplifier 0 control register 1
OA0CTL0
0C0h
USCI_B0 transmit buffer
UCB0TXBUF
06Fh
USCI_B0 receive buffer
UCB0RXBUF
06Eh
UCB0STAT
06Dh
USCI_B0 bit rate control 1
UCB0BR1
06Bh
USCI_B0 bit rate control 0
UCB0BR0
06Ah
USCI_B0 control 1
UCB0CTL1
069h
USCI_B0 control 0
UCB0CTL0
068h
USCI_B0 I2C slave address
UCB0SA
011Ah
USCI_B0 I2C own address
UCB0OA
0118h
USCI_A0 transmit buffer
UCA0TXBUF
067h
USCI_A0 receive buffer
USCI_B0 status
USCI_A0
Basic Clock System+
Port P4
UCA0RXBUF
066h
USCI_A0 status
UCA0STAT
065h
USCI_A0 modulation control
UCA0MCTL
064h
USCI_A0 baud rate control 1
UCA0BR1
063h
USCI_A0 baud rate control 0
UCA0BR0
062h
USCI_A0 control 1
UCA0CTL1
061h
USCI_A0 control 0
UCA0CTL0
060h
USCI_A0 IrDA receive control
UCA0IRRCTL
05Fh
USCI_A0 IrDA transmit control
UCA0IRTCTL
05Eh
USCI_A0 auto baud rate control
UCA0ABCTL
05Dh
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P4 resistor enable
P4REN
011h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
P4IN
01Ch
Port P3 resistor enable
P3REN
010h
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P4 input
Port P3
Port P3 input
Port P2
P3IN
018h
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
P2IN
028h
Port P2 interrupt enable
Port P2 input
24
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MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Table 20. Peripherals With Byte Access (continued)
MODULE
Port P1
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
Port P1 interrupt enable
Special Function
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
Absolute Maximum Ratings
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(1)
Voltage applied at VCC to VSS
Voltage applied to any pin
-0.3 V to 4.1 V
(2)
-0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device terminal
Storage temperature, Tstg
(1)
(3)
Unprogrammed device
-55°C to 150°C
Programmed device
-55°C to 105°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions (1) (2)
MIN
VCC
Supply voltage
VSS
Operating free-air temperature
fSYSTEM
Processor frequency
(maximum MCLK frequency) (1) (2)
(see Figure 1)
(1)
(2)
UNIT
1.8
3.6
V
During program/erase
flash memory
2.2
3.6
V
I version
-40
85
T version
-40
105
VCC = 1.8 V, Duty cycle = 50% ±10%
dc
4.15
VCC = 2.7 V, Duty cycle = 50% ±10%
dc
12
VCC ≥ 3.3 V, Duty cycle = 50% ±10%
dc
16
AVSS = DVSS = VSS
TA
MAX
During program
execution
AVCC = DVCC = VCC
Supply voltage
NOM
0
V
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency −MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Operating Area
26
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MSP430F22x4
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Active Mode Supply Current (into DVCC + AVCC ) Excluding External Current
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IAM,1MHz
IAM,1MHz
IAM,4kHz
IAM,100kHz
TEST CONDITIONS
TA
MIN
TYP
MAX
2.2 V
270
390
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3V
390
550
2.2 V
240
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3.3 V
340
Active mode (AM)
current (4 kHz)
fMCLK = fSMCLK = fACLK = 32768 Hz/8 =
4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (100 kHz)
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0, CPUOFF = 0,
SCG0 = 0, SCG1 = 0, OSCOFF = 1
-40°C to
85°C
2.2 V
5
105°C
-40°C to
85°C
-40°C to
85°C
µA
µA
9
µA
6
10
3V
20
2.2 V
60
105°C
-40°C to
85°C
UNIT
18
105°C
105°C
(1)
(2)
VCC
85
95
3V
72
µA
95
105
All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
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Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC )
ACTIVE-MODE CURRENT
vs
SUPPLY VOLTAGE
TA = 25°C
ACTIVE-MODE CURRENT
vs
DCO FREQUENCY
5.0
8.0
f DCO = 16 MHz
7.0
TA = 85 °C
Active Mode Current − mA
Active Mode Current − mA
4.0
6.0
f DCO = 12 MHz
5.0
4.0
f DCO = 8 MHz
3.0
2.0
TA = 25 °C
3.0
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
1.0
0.0
1.5
2.0
2.5
3.0
3.5
VCC − Supply Voltage − V
Figure 2.
28
VCC = 2.2 V
f DCO = 1 MHz
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4.0
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 3.
Copyright © 2006–2011, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM0,1MHz
ILPM0,100kHz
ILPM2
ILPM3,LFXT1
TEST CONDITIONS
TA
(1)
(2)
(3)
(4)
(5)
TYP
MAX
2.2 V
75
90
Low-power mode 0
(LPM0) current (3)
3V
90
120
2.2 V
37
48
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
3V
41
65
22
29
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
-40°C to
85°C
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
Low-power mode 4
(LPM4) current (5)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
2.2 V
105°C
-40°C to
85°C
31
3V
25
105°C
0.7
1.4
0.7
1.4
2.4
3.3
105°C
5
10
-40°C
0.9
1.5
0.9
1.5
2.6
3.8
105°C
6
12
-40°C
0.4
1
25°C
0.5
1
1.8
2.9
25°C
85°C
2.2 V
3V
2.2 V
105°C
4.5
9
-40°C
0.5
1.2
0.6
1.2
2.1
3.3
25°C
3V
105°C
5.5
11
-40°C
0.1
0.5
0.1
0.5
1.5
3
4.5
9
25°C
85°C
105°C
µA
µA
µA
34
25°C
85°C
UNIT
32
-40°C
85°C
ILPM4
MIN
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
85°C
ILPM3,VLO
VCC
2.2 V/
3V
µA
µA
µA
All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VCC
MIN
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT- )
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1
1.65
1.35
2.25
0.25 VCC
0.55 VCC
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.1
1
3V
0.3
1
3V
20
2.2 V
3V
VIT-
TYP
35
50
5
UNIT
V
V
V
kΩ
pF
Inputs (Ports P1, P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External trigger
pulse width to set interrupt flag (1)
VCC
2.2 V/3 V
MIN
TYP
MAX
20
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int) .
Leakage Current (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
30
High-impedance leakage current
TEST CONDITIONS
(1) (2)
VCC
2.2 V/3 V
MIN
TYP
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
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MSP430F22x4
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Outputs (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH(max) = -1.5 mA
VOH
High-level output voltage
IOH(max) = -6 mA
(2)
IOH(max) = -1.5 mA (1)
IOH(max) = -6 mA (2)
IOL(max) = 1.5 mA
VOL
Low-level output voltage
(2)
2.2 V
3V
(1)
2.2 V
IOL(max) = 6 mA (2)
IOL(max) = 1.5 mA (1)
IOL(max) = 6 mA (2)
(1)
VCC
(1)
3V
MIN
MAX
VCC - 0.25
VCC
VCC - 0.6
VCC
VCC - 0.25
VCC
VCC - 0.6
VCC
VSS
VSS + 0.25
VSS
VSS + 0.6
VSS
VSS + 0.25
VSS
VSS + 0.6
UNIT
V
V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency (with load)
P1.4/SMCLK, CL = 20 pF,
RL = 1 kΩ against VCC/2 (1) (2)
fPort_CLK
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2)
(1)
(2)
VCC
MIN
TYP
MAX
2.2 V
10
3V
12
2.2 V
12
3V
16
UNIT
MHz
MHz
Alternatively, a resistive divider with two 2-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap
of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics - Outputs
One output loaded at a time.
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P4.5
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P4.5
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
VOL − Low-Level Output V oltage − V
1.0
1.5
2.0
2.5
3.0
Figure 4.
Figure 5.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−5.0
−10.0
−15.0
−20.0
−25.0
0.0
3.5
0.0
VCC = 2.2 V
P4.5
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
0.5
VOL − Low-Level Output V oltage − V
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output V oltage − V
Figure 6.
32
TA = 25°C
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2.5
VCC = 3 V
P4.5
−10.0
−20.0
−30.0
−40.0
−50.0
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output V oltage − V
Figure 7.
Copyright © 2006–2011, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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POR/Brownout Reset (BOR)
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 8
dVCC /dt ≤ 3 V/s
V(B_IT-)
See Figure 8 through Figure 10
dVCC /dt ≤ 3 V/s
Vhys(B_IT-)
See Figure 8
dVCC /dt ≤ 3 V/s
td(BOR)
See Figure 8
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally
(1)
(2)
VCC
MIN
TYP
MAX
0.7 ×
V(B_IT-)
70
3V
130
UNIT
V
1.71
V
210
mV
2000
µs
2
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-) . The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics - POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO .
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
UNIT
VCC
Supply voltage range
3.0
3.6
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO)
2.2 V/3 V
1.55
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
ratio
Duty cycle
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
RSELx = 15
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%
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Calibrated DCO Frequencies - Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
-1
±0.2
+1
25°C
3V
0.990
1
1.010
MHz
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3V
15.84
16
16.16
MHz
MAX
UNIT
Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
36
TA
VCC
1-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±0.5
2.5
%
8-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
2.5
%
12-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
2.5
%
16-MHz tolerance over
temperature
0°C to 85°C
3V
-3
±2.0
3
%
2.2 V
0.97
1
1.03
3V
0.975
1
1.025
3.6 V
0.97
1
1.03
2.2 V
7.76
8
8.4
3V
7.8
8
8.2
3.6 V
7.6
8
8.24
2.2 V
11.7
12
12.3
3V
11.7
12
12.3
3.6 V
11.7
12
12.3
3V
15.52
16
16.48
15
16
16.48
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
0°C to 85°C
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3.6 V
MIN
TYP
MHz
MHz
MHz
MHz
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Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over VCC
25°C
8-MHz tolerance over VCC
25°C
12-MHz tolerance over VCC
16-MHz tolerance over VCC
UNIT
1.8 V to 3.6 V
-3
±2
+3
%
1.8 V to 3.6 V
-3
±2
+3
%
25°C
2.2 V to 3.6 V
-3
±2
+3
%
25°C
3 V to 3.6 V
-6
±2
+3
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
0.97
1
1.03
MHz
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
7.76
8
8.24
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3 V to 3.6 V
15
16
16.48
MHz
MIN
TYP
MAX
UNIT
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
1-MHz tolerance
overall
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
8-MHz tolerance
overall
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
12-MHz
tolerance overall
I: -40°C to 85°C
T: -40°C to 105°C
2.2 V to 3.6 V
-5
±2
+5
%
16-MHz
tolerance overall
I: -40°C to 85°C
T: -40°C to 105°C
3 V to 3.6 V
-6
±3
+6
%
fCAL(1MHz)
BCSCTL1 = CALBC1_1MHZ,
1-MHz
DCOCTL = CALDCO_1MHZ,
calibration value
Gating time: 5 ms
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
0.95
1
1.05
MHz
fCAL(8MHz)
BCSCTL1 = CALBC1_8MHZ,
8-MHz
DCOCTL = CALDCO_8MHZ,
calibration value
Gating time: 5 ms
I: -40°C to 85°C
T: -40°C to 105°C
1.8 V to 3.6 V
7.6
8
8.4
MHz
fCAL(12MHz)
BCSCTL1 = CALBC1_12MHZ,
12-MHz
DCOCTL = CALDCO_12MHZ,
calibration value
Gating time: 5 ms
I: -40°C to 85°C
T: -40°C to 105°C
2.2 V to 3.6 V
11.4
12
12.6
MHz
fCAL(16MHz)
BCSCTL1 = CALBC1_16MHZ,
16-MHz
DCOCTL = CALDCO_16MHZ,
calibration value
Gating time: 2 ms
I: -40°C to 85°C
T: -40°C to 105°C
3 V to 3.6 V
15
16
17
MHz
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Typical Characteristics - Calibrated 1-MHz DCO Frequency
CALIBRATED 1-MHz FREQUENCY
vs
TEMPERATURE
CALIBRATED 1-MHz FREQUENCY
vs
SUPPLY VOLTAGE
1.03
1.03
1.02
1.02
Frequency − MHz
1.00
VCC = 2.2 V
VCC = 3.0 V
0.99
Frequency − MHz
VCC = 1.8 V
1.01
TA = 105 °C
1.01
TA = 85 °C
1.00
TA = 25 °C
0.99
TA = −40 °C
VCC = 3.6 V
0.98
0.98
0.97
−50.0
−25.0
0.0
25.0
50.0
TA − Temperature − °C
Figure 11.
38
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75.0
100.0
0.97
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 12.
Copyright © 2006–2011, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
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Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
(1)
(2)
UNIT
2
BCSCTL1 = CALBC1_8MHZ,
DCO clock wake-up time DCOCTL = CALDCO_8MHZ
from LPM3/4 (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
2.2 V/3 V
1.5
µs
1
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
tCPU,LPM3/4
MAX
3V
1
CPU wake-up time from
LPM3/4 (2)
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
CLOCK WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
DCO Wake-Up Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 13.
DCO With External Resistor ROSC (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
1.8
3V
1.95
UNIT
fDCO,ROSC
DCO output frequency with ROSC
DT
Temperature drift
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
±0.1
%/°C
DV
Drift with VCC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
10
%/V
(1)
2.2 V
MAX
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
MHz
ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
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Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY
vs
ROSC
VCC = 2.2 V, TA = 25°C
DCO FREQUENCY
vs
ROSC
VCC = 3 V, TA = 25°C
10.00
DCO Frequency − MHz
DCO Frequency − MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
1.00
0.10
RSELx = 4
0.01
10.00
10000.00
ROSC − External Resistor − kW
Figure 15.
DCO FREQUENCY
vs
TEMPERATURE
VCC = 3 V
DCO FREQUENCY
vs
SUPPLY VOLTAGE
TA = 25°C
2.25
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
DCO Frequency − MHz
ROSC = 100k
2.00
DCO Frequency − MHz
10000.00
2.50
2.25
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
0.50
ROSC = 1M
0.25
−25.0
0.0
25.0
50.0
TA − Temperature − C
Figure 16.
40
1000.00
Figure 14.
2.50
0.00
−50.0
100.00
ROSC − External Resistor − kW
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75.0
ROSC = 1M
0.25
100.0
0.00
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 17.
Copyright © 2006–2011, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Crystal Oscillator LFXT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P1.4/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V/3 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, LFXT1Sx = 3 (4)
2.2 V/3 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
dfVLO/dVCC
(1)
(2)
TA
-40°C to 85°C
105°C
(1)
VLO frequency supply voltage drift
(2)
VCC
2.2 V/3 V
I: -40°C to 85°C
T: -40°C to 105°C
2.2 V/3 V
25°C
1.8 V to 3.6 V
MIN
TYP
MAX
4
12
20
22
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method:
I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]
Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Crystal Oscillator LFXT1, High-Frequency Mode (1)
PARAMETER
VCC
MIN
XTS = 1, LFXT1Sx = 0
1.8 V to 3.6 V
LFXT1 oscillator crystal
frequency, HF mode 1
XTS = 1, LFXT1Sx = 1
LFXT1 oscillator crystal
frequency, HF mode 2
XTS = 1, LFXT1Sx = 2
fLFXT1,HF0
LFXT1 oscillator crystal
frequency, HF mode 0
fLFXT1,HF1
fLFXT1,HF2
TEST CONDITIONS
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 3.6 V
2
10
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fLFXT1,HF,logic
OAHF
CL,eff
LFXT1 oscillator logic-level
square-wave input frequency, HF XTS = 1, LFXT1Sx = 3
mode
Oscillation allowance for HF
crystals (see Figure 18 and
Figure 19)
Integrated effective load
capacitance, HF mode (2)
fFault,HF
(1)
(2)
(3)
(4)
(5)
42
Oscillator fault frequency
16
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
2700
XTS = 0, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz,
CL,eff = 15 pF
800
XTS = 0, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz,
CL,eff = 15 pF
300
(3)
XTS = 1,
Measured at P1.4/ACLK,
fLFXT1,HF = 10 MHz
XTS = 1,
Measured at P1.4/ACLK,
fLFXT1,HF = 16 MHz
(4)
2
1.8 V to 3.6 V
XTS = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz,
CL,eff = 15 pF
XTS = 1
Duty cycle, HF mode
TYP
XTS = 1, LFXT1Sx = 3 (5)
50
pF
60
2.2 V/3 V
%
40
2.2 V/3 V
MHz
Ω
1
40
MHz
30
50
60
300
kHz
To improve EMI on the XT2 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
800.0
100000.00
LFXT1Sx = 3
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 1
LFXT1Sx = 2
XT Oscillator Supply Current − uA
Oscillation Allowance − Ohms
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
0.0
0.0
Crystal Frequency − MHz
4.0
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 18.
Figure 19.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1, TA2
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
UNIT
MHz
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTB,cap
Timer_B capture timing
TB0, TB1, TB2
Copyright © 2006–2011, Texas Instruments Incorporated
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
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UNIT
MHz
ns
43
MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
tτ
UART receive deglitch time (1)
(1)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V/3 V
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
150
600
3V
50
100
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 20 and Figure 21)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(1)
TEST CONDITIONS
VCC
MIN
SMCLK, ACLK
Duty cycle = 50% ± 10%
UCLK edge to SIMO valid,
CL = 20 pF
2.2 V
110
3V
75
2.2 V
0
3V
0
TYP
MAX
UNIT
fSYSTEM
MHz
ns
ns
2.2 V
30
3V
20
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 20. SPI Master Mode, CKPH = 0
44
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MSP430F22x2
MSP430F22x4
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1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 21. SPI Master Mode, CKPH = 1
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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USCI (SPI Slave Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 22 and Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time, Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
2.2 V/3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(1)
UCLK edge to SOMI valid,
CL = 20 pF
50
UNIT
tSTE,LEAD
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 22. SPI Slave Mode, CKPH = 0
46
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MSP430F22x4
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 23. SPI Slave Mode, CKPH = 1
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V/3 V
0
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V/3 V
4
µs
tSP
Pulse width of spikes suppressed by input filter
2.2 V
50
150
600
3V
50
100
600
2.2 V/3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
2.2 V/3 V
2.2 V/3 V
0
4
µs
0.6
4.7
µs
0.6
ns
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 24. I2C Mode Timing
48
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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10-Bit ADC, Power Supply and Input Range Conditions (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
Analog supply voltage
range
VSS = 0 V
VAx
Analog input voltage
range (2)
All Ax terminals,
Analog inputs selected in
ADC10AE register
ADC10 supply current (3)
fADC10CLK = 5 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1,
ADC10SHT1 = 0,
ADC10DIV = 0
IADC10
IREF+
Reference supply
current, reference buffer
disabled (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
TA
I: -40°C to 85°C
T: -40°C to 105°C
VCC
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
2.2 V
0.52
1.05
3V
0.6
1.2
2.2 V/3 V
0.25
0.4
I: -40°C to 85°C
T: -40°C to 105°C
mA
mA
3V
0.25
0.4
1.1
1.4
Reference buffer supply
IREFB,0 current with
ADC10SR = 0 (4)
fADC10CLK = 5 MHz
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
-40°C to 85°C
2.2 V/3 V
105°C
2.2 V/3 V
Reference buffer supply
IREFB,1 current with
ADC10SR = 1 (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
-40°C to 85°C
2.2 V/3 V
105°C
2.2 V/3 V
CI
Input capacitance
Only one terminal Ax selected at
a time
I: -40°C to 85°C
T: -40°C to 105°C
RI
Input MUX ON
resistance
0 V ≤ VAx ≤ VCC
I: -40°C to 85°C
T: -40°C to 105°C
(1)
(2)
(3)
(4)
MIN
2.2 V/3 V
1.8
0.5
mA
0.7
0.8
mA
27
pF
2000
Ω
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC,REF+
TEST CONDITIONS
VCC
IVREF+ ≤ 1 mA, REF2_5V = 0
Positive built-in
reference analog
IVREF+ ≤ 0.5 mA, REF2_5V = 1
supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 1
VREF+
Positive built-in
reference voltage
ILD,VREF+
Maximum VREF+
load current
VREF+ load
regulation
MIN
TYP
MAX
UNIT
2.2
2.8
V
2.9
IVREF+ ≤ IVREF+max, REF2_5V = 0
2.2 V/3 V
1.41
1.5
1.59
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
2.35
2.5
2.65
2.2 V
±0.5
3V
±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
2.2 V/3 V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
3V
V
mA
LSB
±2
VREF+ load
regulation response
time
IVREF+ = 100 µA to 900 µA,
VAx ≈ 0.5 x VREF+,
Error of conversion result
≤1 LSB
CVREF+
Maximum
capacitance at pin
VREF+ (1)
IVREF+ ≤ ±1 mA,
REFON = 1, REFOUT = 1
2.2 V/3 V
100
pF
TCREF+
Temperature
coefficient
IVREF+ = constant with
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V/3 V
±100
ppm/°C
tREFON
Settling time of
internal reference
voltage (2)
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 to 1
tREFBURST
(1)
(2)
50
Settling time of
reference buffer (2)
ADC10SR = 0
ADC10SR = 1
IVREF+ = 0.5 mA,
REF2_5V = 0,
REFON = 1,
REFBURST = 1
ADC10SR = 0
IVREF+ = 0.5 mA,
REF2_5V = 1,
REFON = 1,
REFBURST = 1
ADC10SR = 0
ADC10SR = 1
ADC10SR = 1
400
3V
3.6 V
2000
30
ns
µs
1
2.2 V
2.5
2
3V
µs
4.5
The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT = 1),
must be limited; the reference buffer may become unstable otherwise.
The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
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MSP430F22x4
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10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
MIN
MAX
VeREF+ > VeREF-,
SREF1 = 1, SREF0 = 0
1.4
VCC
VeREF- ≤ VeREF+ ≤ VCC - 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
1.4
3
0
1.2
V
1.4
VCC
V
VeREF-
Negative external reference input
voltage range (4)
VeREF+ > VeREF-
ΔVeREF
Differential external reference
input voltage range
ΔVeREF = VeREF+ - VeREF-
VeREF+ > VeREF- (5)
IVeREF+
IVeREF(1)
(2)
(3)
(4)
(5)
Static input current into VeREF+
Static input current into VeREF-
0 V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
VCC
UNIT
V
±1
0 V ≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
0 V ≤ VeREF- ≤ VCC
µA
2.2 V/3 V
0
±1
2.2 V/3 V
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn on settling time of
the ADC (1)
(1)
ADC10SR = 1
fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSELx ≠ 0
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
2.2 V/3 V
3.7
6.3
2.2 V/3 V
2.06
3.51
2.2 V/3 V
13 × ADC10DIVx ×
1 / fADC10CLK
100
UNIT
MHz
MHz
µs
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
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10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
2.2 V/3 V
±1
LSB
ED
Differential linearity error
2.2 V/3 V
±1
LSB
EO
Offset error
2.2 V/3 V
±1
LSB
EG
Gain error
ET
(1)
Total unadjusted error
Source impedance RS < 100 Ω
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
±1.1
±2
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
3V
±1.1
±2
SREFx = 011, buffered external reference (1),
VeREF+ = 1.5 V
2.2 V
±1.1
±4
SREFx = 011, buffered external reference (1),
VeREF+ = 2.5 V
3V
±1.1
±3
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
±2
±5
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
3V
±2
±5
SREFx = 011, buffered external reference (1),
VeREF+ = 1.5 V
2.2 V
±2
±7
SREFx = 011, buffered external reference (1),
VeREF+ = 2.5 V
3V
±2
±6
TYP
MAX
2.2 V
40
120
3V
60
160
LSB
LSB
The reference buffer offset adds to the gain and total unadjusted error.
10-Bit ADC, Temperature Sensor and Built-In VMID
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
Temperature sensor supply
current (1)
VCC
REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1, INCHx = 0Ah (2)
TCSENSOR
VOffset,Sensor
TEST CONDITIONS
Sensor offset voltage
ADC10ON = 1, INCHx = 0Ah
2.2 V/3 V
(2)
Sensor output voltage (3)
3.44
3.55
-100
Temperature sensor voltage at
TA = 105°C (T version only)
VSENSOR
MIN
100
1365
1465
1195
1295
1395
Temperature sensor voltage at TA = 25°C
985
1085
1185
Temperature sensor voltage at TA = 0°C
895
995
1095
2.2 V/3 V
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (4)
ADC10ON = 1, INCHx = 0Bh
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(1)
(2)
(3)
(4)
(5)
52
2.2 V/3 V
µA
3.66 mV/°C
1265
Temperature sensor voltage at TA = 85°C
UNIT
mV
mV
µs
30
2.2 V
N/A
3V
N/A
µA
V
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high).When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
No additional current is needed. The VMID is used during sampling.
The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Operational Amplifier (OA) Supply Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
MIN
Supply voltage range
Supply current (1)
Medium Mode
2.2 V/3 V
Slow Mode
PSRR
(1)
MAX
180
290
110
190
50
80
2.2
Fast Mode
ICC
TYP
Power-supply rejection ratio
Noninverting
2.2 V/3 V
UNIT
3.6
V
µA
70
dB
Corresponding pins configured as OA inputs and outputs, respectively.
Operational Amplifier (OA) Input/Output Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VI/P
TEST CONDITIONS
VCC
Input voltage range
Input leakage
current (1) (2)
TA = +55 to +85°C
2.2 V/3 V
TA = +85 to +105°C
Medium Mode
Voltage noise
density, I/P
±0.5
5
-20
±5
20
-50
fV(I/P) = 1 kHz
140
30
fV(I/P) = 10 kHz
65
Offset temperature
drift, I/P (3)
2.2 V/3 V
0.3 V ≤ VIN ≤ VCC - 1.0 V
ΔVCC ≤ ±10%, TA = 25°C
VOH
High-level output
voltage, O/P
Fast Mode, ISOURCE ≤ -500 µA
VOL
Low-level output
voltage, O/P
Fast Mode, ISOURCE ≤ 500 µA
Slow Mode, ISOURCE ≤ -150 µA
Slow Mode, ISOURCE ≤ 150 µA
RLoad = 3 kΩ, CLoad = 50 pF,
VO/P(OAx) > VCC - 1.2 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
RLoad = 3 kΩ, CLoad = 50 pF,
0.2 V ≤ VO/P(OAx) ≤ VCC - 0.2 V
CMRR
(1)
(2)
(3)
(4)
Common-mode
rejection ratio
Noninverting
±10
±10
2.2 V/3 V
mV
µV/°C
±1.5
2.2 V/3 V
RLoad = 3 kΩ, CLoad = 50 pF,
VO/P(OAx) < 0.2 V
Output resistance
(see Figure 25)
nV/√Hz
50
2.2 V/3 V
Offset voltage drift
with supply, I/P
RO/P(OAx)
nA
50
Fast Mode
Offset voltage, I/P
(4)
V
80
Slow Mode
VIO
UNIT
50
Slow Mode
Medium Mode
MAX
VCC - 1.2
-5
Fast Mode
Vn
TYP
-0.1
TA = -40 to +55°C
Ilkg
MIN
VCC - 0.2
VCC
VCC - 0.1
VCC
VSS
0.2
VSS
0.1
150
250
150
250
0.1
4
mV/V
70
V
V
Ω
dB
ESD damage can degrade input current leakage.
The input bias current is overridden by the input leakage current.
Calculated using the box method
Specification valid for voltage-follower OAx configuration
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RO/P(OAx)
Max
R Load
ILoad
AV CC
OAx
2
CLoad
O/P(OAx)
Min
AV CC −0.2VAV
0.2V
V
CC OUT
Figure 25. OAx Output Resistance Tests
Operational Amplifier (OA) Dynamic Specifications (MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SR
TEST CONDITIONS
Slew rate
VCC
MIN
Fast Mode
1.2
Medium Mode
0.8
Slow Mode
0.3
Open-loop voltage gain
φm
GBW
TYP
MAX
UNIT
V/µs
100
dB
Phase margin
CL = 50 pF
60
deg
Gain margin
CL = 50 pF
20
dB
Noninverting, Fast Mode,
RL = 47 kΩ, CL = 50 pF
2.2
Gain-bandwidth product
(see Figure 26 and Figure 27)
Noninverting, Medium Mode,
RL = 300 kΩ, CL = 50 pF
2.2 V/3 V
1.4
Noninverting, Slow Mode,
RL = 300 kΩ, CL = 50 pF
ten(on)
Enable time on
ten(off)
Enable time off
MHz
0.5
ton, noninverting, Gain = 1
2.2 V/3 V
10
2.2 V/3 V
TYPICAL OPEN-LOOP GAIN
vs
FREQUENCY
20
µs
1
µs
TYPICAL PHASE
vs
FREQUENCY
140
0
120
100
−50
Fast Mode
80
Fast Mode
Phase − degrees
Gain − dB
60
40
Medium Mode
20
0
Slow Mode
−100
Medium Mode
−150
−20
Slow Mode
−40
−200
−60
−80
1
10
100
1000
Input Frequency − kHz
Figure 26.
54
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10000
100000
−250
1
10
100
1000
10000
100000
Input Frequency − kHz
Figure 27.
Copyright © 2006–2011, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Operational Amplifier OA Feedback Network, Resistor Network (MSP430F22x4 Only) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Rtotal
Total resistance of resistor string
76
96
128
kΩ
Runit
Unit resistor of resistor string (2)
4.8
6
8
kΩ
(1)
(2)
A single resistor string is composed of 4 Runit + 4 Runit + 2 Runit + 2 Runit + 1 Runit + 1 Runit + 1 Runit + 1 Runit = 16 Runit = Rtotal.
For the matching (that is, the relative accuracy) of the unit resistors on a device, see the gain and level specifications of the respective
configurations.
Operational Amplifier (OA) Feedback Network, Comparator Mode (OAFCx = 3) (MSP430F22x4
Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLevel
Comparator level
MIN
TYP
MAX
OAFBRx = 1, OARRIP = 0
TEST CONDITIONS
VCC
0.245
0.25
0.255
OAFBRx = 2, OARRIP = 0
0.495
0.5
0.505
OAFBRx = 3, OARRIP = 0
0.619
0.625
0.631
OAFBRx = 4, OARRIP = 0
N/A (1)
OAFBRx = 5, OARRIP = 0
N/A (1)
OAFBRx = 6, OARRIP = 0
N/A (1)
OAFBRx = 7, OARRIP = 0
OAFBRx = 1, OARRIP = 1
2.2 V/3 V
0.065
0.122
0.125
0.128
0.184
0.1875
0.192
OAFBRx = 4, OARRIP = 1
0.245
0.25
0.255
OAFBRx = 5, OARRIP = 1
0.367
0.375
0.383
OAFBRx = 6, OARRIP = 1
0.495
0.5
0.505
Fast Mode, Overdrive 10 mV
40
Fast Mode, Overdrive 100 mV
4
Medium Mode, Overdrive 100 mV
VCC
N/A (1)
3
Medium Mode, Overdrive 10 mV
60
2.2 V/3 V
Medium Mode, Overdrive 500 mV
(1)
0.0625
OAFBRx = 3, OARRIP = 1
Fast Mode, Overdrive 500 mV
Propagation delay
(low-high and high-low)
0.061
OAFBRx = 2, OARRIP = 1
OAFBRx = 7, OARRIP = 1
tPLH,
tPHL
N/A (1)
UNIT
6
µs
5
Slow Mode, Overdrive 10 mV
160
Slow Mode, Overdrive 100 mV
20
Slow Mode, Overdrive 500 mV
15
The level is not available due to the analog input voltage range of the operational amplifier.
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Operational Amplifier (OA) Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
(MSP430F22x4 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
G
Gain
MIN
TYP
MAX
OAFBRx = 0
TEST CONDITIONS
0.998
1
1.002
OAFBRx = 1
1.328
1.334
1.340
OAFBRx = 2
1.985
2.001
2.017
OAFBRx = 3
2.638
2.667
2.696
3.94
4
4.06
OAFBRx = 5
5.22
5.33
5.44
OAFBRx = 6
7.76
7.97
8.18
OAFBRx = 7
15
15.8
16.6
OAFBRx = 4
THD
Total harmonic distortion/nonlinearity
All gains
tSettle
Settling time (1)
All power modes
(1)
VCC
2.2 V/3 V
2.2 V
-60
3V
-70
2.2 V/3 V
7
UNIT
dB
12
µs
The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
Operational Amplifier (OA) Feedback Network, Inverting Amplifier Mode (OAFCx = 6)
(MSP430F22x4 Only) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
G
Gain
MIN
TYP
MAX
OAFBRx = 1
TEST CONDITIONS
-0.345
-0.335
-0.325
OAFBRx = 2
-1.023
-1.002
-0.979
OAFBRx = 3
-1.712
-1.668
-1.624
-3.1
-3
-2.9
OAFBRx = 5
-4.51
-4.33
-4.15
OAFBRx = 6
-7.37
-6.97
-6.57
OAFBRx = 7
-16.3
-14.8
-13.1
OAFBRx = 4
THD
Total harmonic distortion/nonlinearity
All gains
tSettle
Settling time (2)
All power modes
(1)
(2)
56
VCC
2.2 V/3 V
2.2 V
-60
3V
-70
2.2 V/3 V
7
UNIT
dB
12
µs
This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx.
The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC (PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
7
mA
10
ms
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
2.2 V/3.6 V
20
104
Program/Erase endurance
ms
105
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
0
Block program time for 1st byte or word
(2)
25
tFTG
tBlock,
1-63
Block program time for each additional
byte or word
(2)
18
tFTG
Block program end-sequence wait time
(2)
6
tFTG
Mass erase time
(2)
10593
tFTG
Segment erase time
(2)
4819
tFTG
tBlock,
End
tMass Erase
tSeg Erase
(1)
(2)
100
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
(1)
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
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MSP430F22x2
MSP430F22x4
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JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V/3 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V/3 V
15
100
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V/3 V
25
90
kΩ
fTCK
TCK input frequency (2)
RInternal
Internal pulldown resistance on TEST
(1)
(2)
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
58
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
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APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
DVCC
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
Set
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Table 21. Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
Timer_A3.TACLK
0
1
ADC10CLK
1
1
P1.1 (1) (I/O)
I: 0; O: 1
0
0
1
P1.0 (1)
P1.0/TACLK/ADC10CLK
P1.1/TA0
0
1
Timer_A3.CCI0A
Timer_A3.TA0
P1.2 (1) (I/O)
P1.2/TA1
2
Timer_A3.CCI0A
Timer_A3.TA0
(1)
3
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
P1.3 (1) (I/O)
P1.3/TA2
CONTROL BITS/SIGNALS
Default after reset (PUC/POR)
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Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access
Features
Pad Logic
P1REN.x
P1DIR.x
0
P1OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
Set
Interrupt
Edge
Select
P1SEL.x
P1IES.x
To JTAG
From JTAG
Table 22. Port P1 (P1.4 to P1.6) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.4
P1.4/SMCLK/TCK
4
(2)
(I/O)
5
(1)
(2)
(3)
60
6
P1SEL.x
4-Wire JTAG
I: 0; O: 1
0
0
1
1
0
TCK
X
X
1
I: 0; O: 1
0
0
Timer_A3.TA0
1
1
0
TMS
X
X
1
I: 0; O: 1
0
0
P1.6 (2) (I/O)
P1.6/TA1/TDI/TCLK
P1DIR.x
SMCLK
P1.5 (2) (I/O)
P1.5/TA0/TMS
CONTROL BITS/SIGNALS (1)
Timer_A3.TA1
1
1
0
TDI/TCLK (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Function controlled by JTAG
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features
Pad Logic
P1REN.7
P1DIR.7
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.7
DVSS
DVCC
P1.7/TA2/TDO/TDI
Bus
Keeper
P1SEL.7
EN
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
Set
Interrupt
Edge
Select
P1SEL.7
P1IES.7
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 23. Port P1 (P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.7 (2) (I/O)
P1.7/TA2/TDO/TDI
7
Timer_A3.TA2
TDO/TDI
(1)
(2)
(3)
(3)
CONTROL BITS/SIGNALS (1)
P1DIR.x
P1SEL.x
4-Wire JTAG
I: 0; O: 1
0
0
1
1
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
Function controlled by JTAG
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Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P2REN.x
P2DIR.x
0
P2OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P2.0/ACLK/A0/OA0I0
P2.2/TA0/A2/OA0I1
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
Set
Interrupt
Edge
Select
P2SEL.x
P2IES.x
+
OA0
−
Table 24. Port P2 (P2.0, P2.2) Pin Functions
Pin Name (P2.x)
x
y
FUNCTION
P2.0 (2) (I/O)
P2.0/ACLK/A0/OA0I0
0
0
ACLK
A0/OA0I0
(3)
P2.2 (2) (I/O)
P2.2/TA0/A2/OA0I1
(1)
(2)
(3)
62
2
2
Timer_A3.CCI0B
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
Timer_A3.TA0
1
1
0
A2/OA0I1 (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 1
ADC10AE0.1
P2REN.1
P2DIR.1
0
P2OUT.1
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P2.1/TAINCLK/SMCLK/
A1/OA0O
Bus
Keeper
P2SEL.1
EN
P2IN.1
EN
Module X IN
D
P2IE.1
P2IRQ.1
EN
Q
P2IFG.1
Set
+
OA0
P2SEL.1
P2IES.1
OAADCx
OAFCx
OAPMx
Interrupt
Edge
Select
1
−
(OAADCx = 10 or OAFCx = 000) and OAPMx > 00
To OA0 Feedback Network
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger
SREF2
Pad Logic
VSS
0
To ADC 10 VR−
1
To ADC 10
INCHx = 3
ADC10AE0.3
P2REN.3
P2DIR.3
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.3
DVSS
DVCC
P2.3/TA1/
A3/VREF−/VeREF−/
OA1I1/OA1O
Bus
Keeper
P2SEL.3
EN
P2IN.3
EN
Module X IN
D
P2IE.3
P2IRQ.3
P2IFG.3
P2SEL.3
P2IES.3
OAADCx
OAFCx
OAPMx
EN
Q
Set
Interrupt
Edge
Select
OA1
1
−
(OAADCx = 10 or OAFCx = 000) and OAPMx > 00
To OA1 Feedback Network
64
+
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Table 25. Port P2 (P2.1) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2.1
P2.1/TAINCLK/SMCLK/A1/OA0O
(1)
(2)
(3)
1
1
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
Timer_A3.INCLK
0
1
0
SMCLK
1
1
0
A1/OA0O (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Table 26. Port P2 (P2.3) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
Timer_A3.CCI1B
0
1
0
Timer_A3.TA1
1
1
0
A3/VREF-/VeREF-/OA1I1/OA1O (3)
X
X
1
P2.3 (2) (I/O)
P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA1O
(1)
(2)
(3)
3
3
CONTROL BITS/SIGNALS (1)
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger
Pad Logic
To /from ADC10
positive reference
To ADC 10
INCHx = 4
ADC10AE0.4
P2REN.4
P2DIR.4
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.4
DVSS
P2.4/TA2/
A4/VREF+/VeREF+/
OA1I0
Bus
Keeper
P2SEL.4
EN
P2IN.4
EN
Module X IN
D
P2IE.4
P2IRQ.4
EN
Q
P2IFG.4
Set
Interrupt
Edge
Select
P2SEL.4
P2IES.4
+
OA1
−
Table 27. Port P2 (P2.4) Pin Functions
PIN NAME (P2.x)
x
y
CONTROL BITS/SIGNALS (1)
FUNCTION
P2.4 (2) (I/O)
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
4
4
Timer_A3.TA2
A4/VREF+/VeREF+/OA1I0
(1)
(2)
(3)
66
(3)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
1
1
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
Pad Logic
To DCO
DCOR
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
DVCC
P2.5/ROSC
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
Set
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Table 28. Port P2 (P2.5) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.5
P2.5/ROSC
(1)
(2)
(3)
5
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
DCOR
I: 0; O: 1
0
0
N/A (3)
0
1
0
DVSS
1
1
0
ROSC
X
X
1
X = Don't care
Default after reset (PUC/POR)
N/A = Not available or not applicable
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
Pad Logic
P2SEL.7
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
DVCC
P2.6/XIN
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Table 29. Port P2 (P2.6) Pin Functions
PIN NAME (P2.x)
P2.6/XIN
(1)
(2)
68
x
6
FUNCTION
P2.6 (I/O)
XIN (2)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
I: 0; O: 1
0
X
1
X = Don't care
Default after reset (PUC/POR)
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
DVCC
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Table 30. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
XOUT/P2.7
(1)
(2)
(3)
x
6
FUNCTION
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
P2.7 (I/O)
I: 0; O: 1
0
XOUT (2)
X
1
(3)
X = Don't care
Default after reset (PUC/POR)
If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 5
ADC10AE0.5
P3REN.0
P3DIR.0
USCI Direction
Control
0
P3OUT.0
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.0/UCB0STE/UCA0CLK/A5
Bus
Keeper
P3SEL.0
EN
P3IN.0
EN
Module X IN
D
Table 31. Port P3 (P3.0) Pin Functions
PIN NAME (P1.x)
x
y
FUNCTION
P3.0 (2) (I/O)
P3.0/UCB0STE/UCA0CLK/
A5
0
5
UCB0STE/UCA0CLK (3)
A5
(1)
(2)
(3)
(4)
(5)
70
(5)
(4)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
X
1
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P3REN.x
P3DIR.x
USCI Direction
Control
0
P3OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
Bus
Keeper
P3SEL.x
EN
P3IN.x
EN
Module X IN
D
Table 32. Port P3 (P3.1 to P3.5) Pin Functions
PIN NAME (P3.x)
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
(1)
(2)
(3)
(4)
(5)
(6)
x
1
2
3
4
5
FUNCTION
P3.1
(2)
(I/O)
UCB0SIMO/UCB0SDA (3)
P3.2 (4) (I/O)
UCB0SOMI/UCB0SCL
(5)
P3.3 (4) (I/O)
UCB0CLK/UCA0STE (5)
P3.4
(4)
(6)
(I/O)
UCA0TXD/UCA0SIMO (5)
P3.5 (4) (I/O)
UCA0RXD/UCA0SOMI (5)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
Default after reset (PUC/POR)
The pin direction is controlled by the USCI module.
Default after reset (PUC/POR)
The pin direction is controlled by the USCI module.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode even if 4-wire SPI mode is selected.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P3REN.x
P3DIR.x
DVSS
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3OUT.x
DVSS
P3.6/A6/OA0I2
P3.7/A7/OA1I2
Bus
Keeper
P3SEL.x
EN
P3IN.x
EN
Module X IN
D
+
OA0/1
−
Table 33. Port P3 (P3.6, P3.7) Pin Functions
PIN NAME (P3.x)
P3.6/A6/OA0I2
P3.7/A7/OA1I2
(1)
(2)
(3)
72
x
6
7
y
6
7
FUNCTION
P3.6
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
A6/OA0I2 (3)
X
X
1
P3.7 (2) (I/O)
I: 0; O: 1
0
0
X
X
1
A7/OA1I2
(3)
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Table 34. Port P4 (P4.0 to P4.2) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (1) (I/O)
P4.0/TB0
0
Timer_B3.CCI0A
Timer_B3.TB0
P4.1 (1) (I/O)
P4.1/TB1
1
Timer_B3.CCI1A
Timer_B3.TB1
(1)
2
P4DIR.x
P4SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_B3.CCI2A
0
1
Timer_B3.TB2
1
1
P4.2 (1) (I/O)
P4.2/TB2
CONTROL BITS/SIGNALS
Default after reset (PUC/POR)
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
†
INCHx = 8+y
ADC10AE1.y
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
DVCC
P4.3/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
+
OA0/1
−
OAADCx
OAPMx
1
OAADCx = 01 and OAPMx > 00
To OA0/1 Feedback Network
1
†
If OAADCx = 11 and not OAFCx = 000, the ADC input A12 or A13 is internally connected to the OA0 or OA1 output,
respectively, and the connections from the ADC and the operational amplifiers to the pad are disabled.
74
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Table 35. Port P4 (P4.3 to P4.4) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.3
P4.3/TB0/A12/OA0O
3
4
4
5
ADC10AE1.y
0
0
0
1
0
Timer_B3.TB0
1
1
0
A12/OA0O (3)
X
X
1
I: 0; O: 1
0
0
Timer_B3.CCI1B
(I/O)
0
1
0
Timer_B3.TB1
1
1
0
X
X
1
A13/OA1O
(1)
(2)
(3)
P4SEL.x
I: 0; O: 1
(2)
(I/O)
P4DIR.x
Timer_B3.CCI0B
P4.4
P4.4/TB1/A13/OA1O
(2)
CONTROL BITS/SIGNALS (1)
(3)
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
INCHx = 14
ADC10AE1.6
P4REN.5
P4DIR.5
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P4OUT.5
DVSS
DVCC
P4.5/TB3/A14/OA0I3
Bus
Keeper
P4SEL.5
EN
P4IN.5
EN
Module X IN
D
+
OA0
−
Table 36. Port P4 (P4.5) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.5
P4.5/TB3/A14/OA0I3
(1)
(2)
(3)
76
5
6
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P4DIR.x
P4SEL.x
ADC10AE1.y
I: 0; O: 1
0
0
Timer_B3.TB2
1
1
0
A14/OA0I3 (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 15
ADC10AE1.7
P4REN.6
P4DIR.6
0
P4OUT.6
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P4.6/TBOUTH/
A15/OA1I3
Bus
Keeper
P4SEL.6
EN
P4IN.6
EN
Module X IN
D
+
OA1
−
Table 37. Port P4 (P4.6) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.6
P4.6/TBOUTH/A15/OA1I3
(1)
(2)
(3)
6
7
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P4DIR.x
P4SEL.x
ADC10AE1.y
I: 0; O: 1
0
0
TBOUTH
0
1
0
DVSS
1
1
0
A15/OA1I3 (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P4REN.x
P4DIR.x
0
P4OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P4.7/TBCLK
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Table 38. Port P4 (Pr.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.7
P4.7/TBCLK
(1)
78
7
(1)
(I/O)
CONTROL BITS/SIGNALS
P4DIR.x
P4SEL.x
I: 0; O: 1
0
Timer_B3.TBCLK
0
1
DVSS
1
1
Default after reset (PUC/POR)
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITEST
Figure 28. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit
bootloader access key is used. Also, see the Bootstrap Loader section for more
information.
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MSP430F22x2
MSP430F22x4
SLAS504E – JULY 2006 – REVISED MARCH 2011
www.ti.com
REVISION HISTORY
Literature
Number
Summary
SLAS504
Preliminary data sheet release
SLAS504A
Production data sheet release
Updated specification and added characterization graphs
Updated/corrected port pin schematics
SLAS504B
Maximum low-power mode supply current limits decreased
Added note concerning fUCxCLK to USCI SPI parameters
SLAS504C
Changed Tstg for programmed devices from "-40°C to 105°C" to "-55°C to 105°C" (page 23)
Added Development Tool Support section (page 2)
SLAS504D
Corrected pin names in "Port P3 pin schematic: P3.0" and "Port P3 (P3.0) pin functions" (page 68)
Corrected pin names in "Port P3 pin schematic: P3.1 to P3.5" and "Port P3 (P3.1 to P3.5) pin functions" (page 69)
Corrected signal names in "Port P2 pin schematic: P2.5, input/output" (page 65) (D1)
Corrected values in "x" column in "Port P3 (P3.1 to P3.5) pin functions" (page 69) (D2)
SLAS504E
80
Added information for YFF package
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