Features • • • • • • • • • • • Fully Integrated Low IF Receiver Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 kBit/s High Sensitivity of Typically -93 dBm Due to Integrated LNA High Output Power of Typically +4 dBm Multi-channel Operation – 95 Channels – Support Frequency Hopping (ETSI) and Digital Modulation (FCC) Supply-voltage Range 2.9 V to 3.6 V (Unregulated) Auxiliary-voltage Regulator on Chip (3.2 V to 4.6 V) Low Current Consumption Few Low Cost External Components Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier Low Profile Lead-free Plastic Package QFN32 (5 × 5 × 0.9 mm) Low IF 2.4 GHz ISM Transceiver ATR2406 Applications • • • • • • • Hightech Multi-user Toys Wireless Game Controllers Telemetry Wireless Audio/Video Electronic Point of Sales Wireless Head Set FCC CFR47, Part 15, ETSI EN 300 328 and ARIB STD-T-66 Compliant Radio Links Preliminary Electrostatic sensitive device. Observe precautions for handling. Description The ATR2406 is a single chip RF-transceiver intended for applications in the 2.4 GHz ISM band. The QFN32 packaged IC is a complete transceiver including image rejection mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF-transceiver offers a clock recovery function on-chip. Rev. 4779F–ISM–09/04 Figure 1. Block Diagram REG_DEC VREG REG_CTRL VS_REG IREF VREG_VCO VCO REG LNA AUX REG VREF IR-MIXER BP RX_IN VS_SYN VS_IFD VS_IFA VS_RX/TX LIMITER RSSI DEMOD RX_DATA RSSI PA VCO TX_OUT RAMP_OUT BUS RAMP GEN GAUSSIAN FILTER CTRL LOGIC PLL CLOCK DATA ENABLE RX-CLOCK PU_REG PU_TRX RX_ON TX_ON nOLE REF_CLK TX_DATA VTUNE CP Pin Configuration ENABLE DATA CLOCK TX_DATA RX_DATA PU_TRX nOLE TX_ON Figure 2. Pinning QFN32 - 5 × 5 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 ATR2406 RX_ON IC IC RAMP_OUT TX_OUT RX_IN1 RX_IN2 VS_TRX REG_CTRL VREG VS_REG REG_DEC VREG_VCO VTUNE CP VS_SYN PU_REG REF_CLK RSSI VS_IFD VS_IFA RX-CLOCK IC IREF 2 ATR2406 [Preliminary] 4779F–ISM–09/04 ATR2406 [Preliminary] Pin Description Pin Symbol Function 1 PU_REG Power-up input for auxiliary regulator 2 REF_CLK Reference frequency input 3 RSSI 4 VS_IFD Received signal strength indicator output Digital supply voltage 5 VS_IFA Analog supply voltage for IF circuits 6 RX-CLOCK RX-CLOCK, if RX mode with clock recovery is active 7 IC 8 IREF External resistor for band-gap reference 9 REG_CTRL Auxiliary voltage regulator control output 10 VREG 11 VS_REG 12 REG_DEC 13 VREG_VCO 14 VTUNE Internal connected, do not connect on PCB Auxiliary voltage regulator output Auxiliary voltage regulator supply voltage Decoupling pin for VCO_REG VCO voltage regulator VCO tuning voltage input 15 CP 16 VS_SYN Charge-pump output Synchronous supply voltage 17 VS_TRX Transmitter receiver supply voltage 18 RX_IN2 Differential receiver input 2 19 RX_IN1 Differential receiver input 1 20 TX_OUT TX driver amplifier output 21 RAMP_OUT 22 IC Ramp generator output for PA power ramping Internal connected, do not connect on PCB 23 IC 24 RX_ON RX control input Internal connected, do not connect on PCB 25 TX_ON TX control input 26 nOLE Open loop enable input 27 PU_TRX RX/TX/PLL/VCO power-up input 28 RX_DATA RX data output 29 TX_DATA TX data input 30 CLOCK 3-wire-bus: Clock input 31 DATA 3-wire-bus: Data input 32 ENABLE Paddle GND 3-wire-bus: Enable input Ground 3 4779F–ISM–09/04 Functional Description Receiver The RF signal at RF_IN is differently fed through the LNA to the image rejection mixer IR_MIXER driving the integrated LowIF bandpass filter. The IF frequency is 864 kHz.The limiting IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator DEMOD. No tuning is required. Datasling is handled internally. Clock Recovery For 1152 kBit/s data rate the receiver has a clock recovery function on-chip. The receiver includes a clock recovery circuit which regenerates the clock out of the received data. The advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data) which allows to reduce the load of the processing microcontroller significantly. The falling edge of the clock gives the optimal sampling position for the RX_Data signal so at this event the data must be sampled by the microcontroller. The recovered clock is available at pin 6. Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typically +4 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled internally so that spurious requirements are fulfilled. Synthesizer The IR_MIXER, the PA and the programmable counter PC are driven by the fully integrated VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 1.728 MHz). Open loop modulation is supported. Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. 4 ATR2406 [Preliminary] 4779F–ISM–09/04 ATR2406 [Preliminary] Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage auxiliary regulator VS -0.3 +4.7 V Supply voltage VS -0.3 +3.6 V Vcontr -0.3 VS V Storage temperature Tstg -40 +125 °C Input RF level PRF +10 dBm VESD_anal TBD V VESD_dig TBD V Control voltages ESD protection Operating Range Parameters Symbol Min. Max. Unit VS 2.9 3.6 V VS_BATT 3.2 4.6 V Temperature ambient Tamb -10 +60 °C Input frequency range fRX 2400 2483 MHz Supply voltage Auxiliary regulator supply voltage Electrical Characteristics VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified No. 1 Parameters Test Conditions Symbol Min. Typ. Max. Unit V Supply 1.1 Supply voltage With AUX regulator VS 3.2 3.6 4.6 1.2 Supply voltage w/o AUX regulator VS 2.9 3.0 3.6 1.3 RX supply current CW-mode IS 31 mA 1.4 TX supply current CW-mode IS 16 mA 1.5 Synthesizer supply current IS 26 mA 1.6 Supply current in power-down mode With AUX regulator PU_TRX = 0; PU_REG = 0 IS <1 µA 1.7 Supply current in power-down mode w/o AUX regulator PU_TRX = 0; PU_REG = 0 IS <1 µA 2 V Voltage Regulator 2.1 AUX regulator VREG 3.0 V 2.2 VCO regulator VREG_VCO 2.7 V 72/144/288/576/1152 kBit/s 0 dBm 3 3.1 3.2 Notes: Transmitter Part TX data rate Output power Over full temperature range, from 2400 MHz to 2483 MHz(1) PTX 4 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For further information refer to Application Note. 5 4779F–ISM–09/04 Electrical Characteristics (Continued) VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions 6 taps in filter 3.3 TX data filter clock 3.4 Frequency deviation 3.5 Frequency deviation scaling 3.6 Frequency drift during a slot 3.7 Harmonics 2nd Harmonic 3rd Harmonic BW = 100 kHz(1) 3.8 Spurious Emission 30 - 1000 MHz 1 - 12.75 GHz 1.8 - 1.9 GHz 5.15 - 5.3 GHz BW = 100 kHz(1) 4 GFFM = GFFM_nom × GFCS (see bus protocol D9 to D11) Symbol Min. Typ. Max. Unit fTXFCLK 6.912 MHz GFFM_nom ±400 kHz GFCS 60 ∆fo (drift) 130 % ±10 kHz -40.5 -46 dBc dBc -40.5 -48 -70 -70 dBm dBm dBm dBm Receiver Part 4.1 Sensitivity 4.2 Third order input intercept point At input for BER ≤10-3 at 1152 kBit/s(1) IIP3 -93 dBm -15 dBm -3 4.3 Intermodulation rejection BER < 10 , wanted at -83 dBm, level of interferers in channels N + 2 and N + 4(1) IM3 32 dBc 4.4 Co-channel rejection BER < 10-3, wanted at -76 dBm(1) RCO -11 dBc Adjacent channel rejection BER < 10 , wanted at -76 dBm, adjacent level referred to wanted channel level(1) ±1.728 MHz Ri (N-1) 4 dBc Bi-adjacent channel rejection BER < 10-3, wanted at -76 dBm, biadjacent level referred to wanted channel level(1) ±3.456 MHz Ri (N - 2) 30 dBc 4.7 Rejection with ≥ 3 channels separation BER < 10-3, wanted at -76 dBm, n ≥ 3 adjacent level referred to wanted channel level(1) ≥ ±5.128 MHz Ri (n ≥ 3) 40 dBc 4.8 Out of band rejection > 6 MHz BER < 10-3, wanted at -83 dBm at 2.45 GHz(1) Bldf>6MHz 38 dBc 4.9 Out of band rejection 2300 MHz to 2394 MHz 2506 MHz to 2600 GHz BER < 10-3, wanted at -83 dBm at 2.45 GHz(1) Blnear 47 dBc BER < 10-3, wanted at -83 dBm at 2.45 GHz(1) Blfar 57 dBc -3 4.5 4.6 Out of band rejection 4.10 30 MHz to 2300 MHz 2600 MHz to 6 GHz 5 5.1 Notes: 6 RSSI Part Maximum RSSI output voltage Under high RX input signal level VRSSImax 2.1 V 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For further information refer to Application Note. ATR2406 [Preliminary] 4779F–ISM–09/04 ATR2406 [Preliminary] Electrical Characteristics (Continued) VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters 5.2 RSSI output voltage, monotonic with -33 dBm at RF input over range -96 dBm to -36 dBm with -96 dBm at RF input 5.3 Wake-up time from power-up signal to correct RSSI output 6 Symbol Min. Typ. Oscillator frequency 6.2 Frequency control voltage range 6.3 VCO tuning input gain 1.9 0.3 VRSSI Over full temperature range(1) VVTUNE 2400 2483 MHz 0.5 VCC - 0.5 V GVCO 150 MHz/V 10.368 13.824 MHz MHz Synthesizer D7 = 0 D7 = 1 REF_CLK 7.2 Sinusoidal input signal level (RMS value) AC coupled sinewave REF_CLK 7.3 Scaling factor prescaler SPSC 32/33 7.4 Scaling factor main counter SMC 86/87/88/89 7.5 Scaling factor swallow counter SSC 9 V V µs External reference input frequency 8.1 Unit 40 Ton 7.1 8 Max. VCO 6.1 7 Test Conditions 250 500 0 mVRMS 31 Phase Detector Phase detector comparison frequency fPD 1728 kHz Charge-pump Output Charge-pump output current VCP = 1/2 VCC ICP ±2 mA 9.2 Leakage current VCP = 1/2 VCC IL ±100 pA 10 Timing Conditions(1)(2) 10.1 Transmit to Receive time TX →RX-time 100 µs 10.2 Receive to Transmit time RX →TX-time 100 µs 9.1 10.3 Channel switch time CS-time 350 µs 10.4 Power down to Transmit PD →TR-time 450 µs 10.5 Power down to Receive PD →RX-time 400 µs PRR-time 3 µs PLL set-time 350 µs 10.6 Programming register 10.7 PLL settling time 11 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE 11.1 HIGH-level input voltage Logic 1 VIH 1.4 3.4 V 11.2 LOW-level input voltage Logic 0 VIL -0.3 +0.4 V 11.3 HIGH-level output voltage Logic 1 VOH 3.4 V 11.4 LOW-level output voltage Logic 0 VOL 0 11.5 Input bias current Logic 1 or logic 0 Ibias -5 11.6 3-wire bus clock frequency Notes: fCLKmax V +5 µA 10 MHz 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For further information refer to Application Note. 7 4779F–ISM–09/04 PLL Principle Figure 3. PLL Principle Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = 1728 kHz × (SMC × 32 + SSC) External loop filter PA driver Phase frequency detector PD fPD = 1728 kHz Charge pump VCO Divider by 2 Mixer Gaussian filter GF Reference counter RC REF_CLK D7 10.368 MHz 0 13.824 MHz 1 PLL reference Frequency REF_CLK TXDAT Baseband controller 8 ATR2406 [Preliminary] 4779F–ISM–09/04 ATR2406 [Preliminary] The following table shows the LO frequencies for RX and TX in the 2.4 GHz ISM band. There are 95 channels available. Since the ATR2406 supports wideband modulation with 400 kHz deviation, every second channel can be used without overlap in the spectrum. Table 1. LO Frequencies Mode fIF/kHz Channel fANT/MHz fVCO/MHz SMC SSC N C0 2401.056 2401.056 86 27 2779 C1 2401.920 2401.920 86 28 2780 ... ... ... ... ... ... C93 2481.408 2481.408 89 24 2872 C94 2482.272 2482.272 89 25 2873 C0 2401.056 2401.920 86 28 2780 C1 2401.920 2402.784 86 29 2781 ... ... ... ... ... ... C93 2481.408 2482.272 89 25 2873 C94 2482.272 2483.136 89 26 2874 TX RX 864 TX Register Setting The following 16-bit word has to be programmed for TX. MSB LSB Data bits D15 D14 0 1 Note: D13 D12 PA D11 D10 D9 GFCS D8 D7 1 RC D6 D5 D4 MC D3 D2 D1 D0 SC D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0 or 1. Table 2. Output Power Settings with Bits D12 - D13 PA (Output Power Settings) D13 D12 RAMP_OUT (Pin 21) 0 0 1.3 V 0 1 1.35 V 1 0 1.4 V 1 1 1.75 V 9 4779F–ISM–09/04 RX Register Setting The are two RX settings possible. For a data rate of 1152 kBit/s an internal clock recovery function is implemented. Register Setting without Clock Recovery Must be used for data rates below 1.152 Mbit. MSB LSB Data bits D15 D14 D13 D12 D11 D10 D9 D8 D7 0 1 X X X X X 0 RC Note: D6 D5 D4 D3 MC D2 D1 D0 SC X values are not relevant and can be set to 0 or 1. RX Register Setting with Internal Clock Recovery Recommended for 1.152 Mbit data rate. The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal samples the data signal. MSB Data bits D24 D23 D22 D21 D20 D19 D18 D17 D16 1 0 1 0 0 0 0 0 0 LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 X X X X X 0 RC Note: D6 D5 D4 MC D3 D2 D1 D0 SC X values are not relevant and can be set to 0 or 1. PLL Settings RC, MC and SC bits are controlling the synthesizer frequency according to Table 3, Table 4 and Table 5. Formula for calculating the frequency: TX frequency: fANT = 864 kHz × (32 × SMC + SSC) RX frequency: fANT = 864 kHz × (32 × SMC + SSC + 1) Table 3. PLL Settings with the Reference Counter Bit D7 RC (Reference Counter) 10 D7 CLK Reference 0 10.368 MHz 1 13.824 MHz ATR2406 [Preliminary] 4779F–ISM–09/04 ATR2406 [Preliminary] Table 4. PLL Settings with the Main Counter Bits D5 - D6 MC (Main Counter) D6 D5 SMC 0 0 86 0 1 87 1 0 88 1 1 89 Table 5. PLL Settings with the Swallow Counter Bits D0 - D4 SC (Swallow Counter) GFCS Adjustment D4 D3 D2 D1 D0 SSC 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 ... ... ... ... ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 The Gaussian Filter Control Setting is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. These bits are only relevant in TX mode. Table 6. GFCS Adjustment with Bits D9 - D11 GFCS (Gaussian Filter Control Settings) D11 D10 D9 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% The VRAMP voltage is used to control the output power of an external power amplifier. The voltage ramp is started with the TX_ON signal. These bits are only relevant in TX mode. 11 4779F–ISM–09/04 Control Signals The various transceiver functions are activated by the following control signals. A timing proposal is given in Figure 5 on page 13 Table 7. Control Signals – Functions Serial Programming Bus Signal Functions PU_REG Activates AUX voltage regulator and the VCO voltage regulator supplying the complete transceiver PU_TRX Activates RX/TX blocks RX_ON Activates RX circuits: DEMOD, IF AMP, IR MIXER TX_ON Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT nOLE Disables open loop mode of the PLL The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed information is active. Additional leading bits are ignored and there is no check made how many clock pulses arrived during enable low condition. The programming of the transceiver is done by a 16 bit or 25 bit data word (for the RX clock recovery mode). 3-wire BUS Timing Figure 4. 3-wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TC TPER TL TS TEC TT TH Table 8. 3-wire Bus Protocol Table Description Symbol Minimum Value Unit Clock period TPER 100 ns Set time data to clock TS 20 ns Hold Time data to clock TH 20 ns Clock pulse width TC 60 ns Set time enable to clock TL 100 ns Hold time enable to data TEC 0 ns TT 250 ns Time between two protocols 12 ATR2406 [Preliminary] 4779F–ISM–09/04 RAMP_OUT Pin 21 connected to RAMP_IN of optional PA RSSI Pin 3 RX_DATA Pin 28 TX_ON Pin 25 RX_ON Pin 24 REF_CLK Pin 2 nOLE Pin 26 ENABLE Pin 32 DATA Pin 31 CLOCK Pin 30 TX_DATA Pin 29 PU_TRX Pin 27 PU_REG Pin 1 Signals to TRX (Input) 4779F–ISM–09/04 Signals from TRX (Output) Pin Name MODE Power-down C1 > 40 µs Power-up C2 16/25 bits > 350 µs Programming C3 > 50 µs valid signal Data REF_CLK Active RX-slot C4 Power-up optional Power-down optional > 40 µs C2 C1 16 bits > 350 µs Programming C3 REF_CLK Data > 50 µs Active TX-slot C5 Power-down C1 0V VS 0V VS ATR2406 [Preliminary] Figure 5. Complete TX and RX Timing Diagram 13 Table 9. Description of the Conditions/States Conditiion Description C1 Power-down ATR2406 is switched off and the supply current is lower than 1 µA. C2 Power-up ATR2406 is powered up by toggling PU_REG and PU_RTX to high. PU_REG enables the external AUX-Regulator transistor and PU_TRX enables the internal regulator like VCO_REG (VCO supply voltage regulator) as well as wakes up the PLL, the VCO, the demodulator, mixer, etc. It is necessary to wait at least 40 µs until the different supply voltage regulators have settled. C3 Programming Via the tree-wire-interface the internal register of ATR2406 is programmed. At TX, this is just the PLL (transmit channel) and the deviation (gaussian filter). At RX, this is just the PLL (receive channel) and if the clock recovery is used also the bits to enable this option. At start of the three-wire-programming, the enable signal is toggled from high to low to enable clocking the data into the internal register. When the enable signals rises again to high, the programmed data is latched. This is the time point at which the settling of the PLL is starting. It is necessary to wait the settling time of 350 µs so that the VCO-Frequency is stable. The reference clock needs to be applied to ATR2406 at minimum the time when the PLL is in operation - which is the programming state (C3) and the active slot (C4, C5). Out of the reference clock, several internal signals are also derived, i.e., the gaussian filter circuitry and TX_DATA sampling. C4 This is the receive slot where the transmit burst is received and data as well as recovered clock are available. C5 This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the signal nOLE toggles to low which enables modulation in open-loop-mode. Received Signal Strength The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is shown in Figure 6. Indication RSSI Figure 6. Typical RSSI Value versus Input Power 2.5 RSSI Level (V) 2.0 1.5 1.0 0.5 0.0 -130 -110 -90 -70 -50 -30 -10 10 RF Level (dBm) 14 ATR2406 [Preliminary] 4779F–ISM–09/04 4µ7 C13 100n C12 100n C15 4µ7 C16 4p7 R3 C24 J2 RSSI VS 18p T1 BC808 8 7 6 5 4 3 ENABLE REF_CLK IREF IC RX-CLOCK VS_IFA VS_IFD RSSI CLOCK 31 ENABLE REG_CTRL PU_REG 62k 4n7 RX_DATA 30 ATR2406 CLOCK VS_REG 11 VS_TRX RX_IN2 RX_IN1 TX_OUT RAMP C20, C21, COG dielectric 2n2 C21 TX_ON RAMP_OUT IC IC 17 18 19 20 21 22 23 24 22n C20 RAMP_OUT RX_ON NC J26 TP2 TP1 VBATT µStrip-balun IC2P GND Slug REF_CLK 1p8 C10 1p5 C9 J8 J9 J10 CLOCK RX_ON RSSI J3 J4 J5 J6 J7 C6 VBATT TX_ON TX_DATA PU_TRX C7 µStrip 3n3 C11 REF_CLK C23 2p2 DATA 32 9 PU_TRX nOLE CP 15 µStrip Lowpassfilter R5 3k3 C3 TX_DATA 29 REG_DEC C18 12 470n C17 VREG_VCO 13 NC DATA VREG 10 C19 28 TX_DATA 27 RX_DATA 26 PU_TRX VTUNE 14 68p 25 TX_ON VS_SYN 16 2 C4 nOLE GND G RX_ON 390p PU_REG R4 1 C14 IC2 1k5 5p6 GND2 µStrip GND7 GND8 GND9 GND4 GND5 GND6 GND1 GND3 2p2 C1 820 J24 J1 1p8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 VLSI Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 27 J2 RX_DATA J17 J18 J19 J20 J21 ENABLE DATA nOLE PU_REG RX-CLOCK J12 J13 J14 J15 J16 GND ANT F-antenna VBATT ANT ANT2 J11 GND SMASI NC R2 Select integrated F-antenna or SMA connector by setting the 0R resistor Application Circuit R6 R1 4779F–ISM–09/04 NC RFOUT (Ant) ATR2406 [Preliminary] The ATR2406 requires only few low cost external components for operation. A typical application is shown in Figure 7. Figure 7. Application Circuit 15 RX-CLOCK PCB-layout Design Figure 8. PCB-layout ATR2406-DEV-BOARD 16 ATR2406 [Preliminary] 4779F–ISM–09/04 ATR2406 [Preliminary] Table 10. Bill of Material Part Value C1 5p6 Part Number Vendor Package GJM1555C1H5R6CB01 or GRM1555C1H5R6DZ01 Murata® Comment 0402 C3 1p8 GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata 0402 C4 390p GRM1555C1H391JA01 Murata 0402 C5 4p7 GJM1555C1H4R7CB01 or GRM1555C1H4R7CZ01 Murata 0402 C6 2p2 GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata 0402 C7 2p2 GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata 0402 0402 NC C9 1p5 GJM1555C1H1R5CB01 or GRM1555C1H1R5CZ01 Murata C10 1p8 GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata 0402 C11 18P GRM1555C1H180JB01 Murata 0402 C12 100n GRM15F51H104ZB01 Murata 0402 B45196H2475M109 ® Epcos 3216 Optional2 NC C13 4µ7 C14 1n GRM15R71H102KB01 Murata 0402 C15 100n GRM15F51H104ZB01 Murata 0402 C16 4µ7 B45196H2475M109 Epcos 3216 Optional2 C17 3n3 GRM15R71H332KB01 Murata 0402 NC C18 68p GRM155C1H680JB01 Murata 0402 470n GRM18F51H474ZB01 (0402) or 0603-Version C19 C20 22n, COG GRM21B5C1H223JA01 C21 2n2, COG GRM1885C1H222JA01 Murata 0402/0603 Murata 0805 Murata 0603 C23 4n7 GRM15R71H472KB01 Murata 0402 C24 4p7 GRM1555C1H4R7CB01 Murata 0402 L6 8n2 WE-MK0402 744784082 Würth Electronic® 0402 R3 62k 62k, ←5% Vishay R4 1k5 1k5, ←5% Vishay 0402 R5 3k3 3k3, ←5% Vishay 0402 Ref_Clk-Level, optional1 R6 820R 820R, ←5% Vishay 0402 Ref_Clk-Level, optional1 IC2 ATR2406 Atmel MLF32 T1 BC808-40, any standard type can be used, BC808-40 important is "-40" Vishay, Philips®, ... SOT-23 MSUB Note: FR4 ATR2406 ® NC, µStrip used 0402 Optional2 FR4, e_r = 4.4 at 2.45 GHz, H = 500 µm, T = 35 µm, tand = 0.02, surface i.e. chem. tin or chem. gold 1 Option = no necessary if supplied RefClk level is within specification range Option2 = if no AUX regulator is used, then T1 has to be bypassed To use the integrated F-antenna, set jumper R2 (0R resistor 0603) Table 11. Parts Count Bill of Material Parts Count Required (Minimal BOM) Optional (Depending on Application) Capacitors 0402 14 - Capacitors >0402 2 2 Resistors 0402 2 2 Inductors 0402 - - Semiconductors 1 1 17 4779F–ISM–09/04 Ordering Information Extended Type Number Package Remarks MOQ ATR2406-PNSG QFN32 - 5x5 Tube, Sampling; Pb-free 600 ATR2406-PNQG QFN32 - 5x5 Taped and reeled; Pb-free 6000 ATR2406-DEV-BOARD - RF-module 1 ATR2406-DEV-KIT - Complete Evaluation-kit 1 Package Information 18 ATR2406 [Preliminary] 4779F–ISM–09/04 ATR2406 [Preliminary] Recommended Footprint/Landing Pattern Figure 9. Recommenced Footprint/Landing Pattern Table 1. Recommended Footprint/Landing Pattern Signs Sign Size A 3.2 mm B 1.2 mm C 0.3 mm a 1.1 mm b 0.3 mm c 0.2 mm d 0.55 mm e 0.5 mm 19 4779F–ISM–09/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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