Preliminary January 200115 PBL 402 PBL 402 15 RF Transceiver circuit for the Digital Enhanced Cordless Telecommunications (DECT) system Description. Key features. The PBL 402 15 is a complete RF transceiver to be used in the Digital Enhanced Cordless Telecommunications ( DECT ) system. It is designed to interface to various base-band controllers. The circuit contains transmit and receive functions that share integrated high stability VCO´s and a phase locked loop function ( PLL ). All functionality is controlled through a 3-wire bus interface with optional hard wire lines. The receive section comprises of a low noise image reject down conversion to the first intermediate frequency, an external channel filter, a second down convertion to a second intermediate frequency, an integrated channel pass filter, a high gain limiting amplifier, a received signal strenght indicator with DC compensation loop, a self aligned frequency discriminator and a preamble based data slicer. The transmit section comprises of a signal gate and a pre-power amplifier. Data transmission is achieved by direct open loop modulation of the Tx VCO. • High Tx output power to +7dBm • Integrated PLL and high stability VCO´s • 3-line serial interface bus • Minimum 2.7 V supply voltage • Low current consumption • Differential Rx input and Tx output • Flexible interface to various baseband controllers • Exellent performance with Ericsson´s power amplifier PBL403 09 • Low cost Applications: • DECT Handset and base station • Wireless local area network ( WLAN ) • Wireless local loop ( WLL ) 5 21 0 L4 PB Figure 1. Block diagram. Figure 2. Package outlook. 1 PBL 402 15 C16 10nF PA - Vcc C14 2.2nF C15 8pF L5 4.7nH C17 33pF C12 1pF Vcc MS lines 3 GND L6 4.7nH RxEN TxEN ST CK D 46 45 44 43 -in -out Consult PBL40309 for PA output matching requirements Can also be a balun type of solution GND 42 41 40 GND EN 1 37 36 REF 2 35 47 +out Gate C13 1pF GATE GND 48 +in 39 38 C10 8pF C8 1pF L3 5.6nH RF in to Rx GND L4 8.2nH VccPLL 3 34 4 33 5 32 L2 5.6nF C11 8pF 6 31 PBL402 15 VccCP 7 30 LD NC 8 29 VccIF 28 GND C1 680 pF C4 11pF * L0 180nH * CP R0 3.9k GND MS lines 1 GND C0 6.8nF 9 NC C5 11pF * _ Regulated supply Vcc VTUNE VccVCO 10 27 11 26 in + IF - SAW filter _ + out C6 68pF * C2 100nF Feed from antenna switch. ( 50 ohms ) 1pF C9 MS lines 2 L1 140nH * C7 68pF * 12 13 14 15 16 17 18 20 19 21 22 23 PA Gate 25 24 GND GND MOD DTx Vcc VccFM SHold * These components for matching are not needed if Murata filter is used RSSI C3 2nF C18 22nF DRx DSL Figure 3. DECT application. EUROPEAN DECT Band 1880 - 1900 MHz Frequency TDMA ( time division multiple access ) Frequency and time division. 10 channels Channel spacing 1.728 MHz A-word CNT_A Frequency MHz 9 1 1881.792 8 2 1883.520 7 3 1885.248 6 4 1886.976 5 5 1888.704 4 6 1890.432 3 7 1892.160 2 8 1893.888 9 1895.616 10 1897.344 Base to Mobile 1 Mobile to Base Channel 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 time slots 1 slot = 416.67µs each slot contains, a synchronisation field, control info, data package and error control. Time Frame =10 ms Figure 4. The European DECT band . 2 GndRF TX- TX+ GndRF VccRF GATE D CK ST TXEN DIE RXEN PBL 402 15 EN 1 48 47 46 45 44 43 42 41 40 39 38 37 36 REF 2 35 RX+ VccPLL 3 34 RX- GndPLL 4 33 GndRF GndCP 5 32 IFOUT+ CP 6 31 IFOUT- VccCP 7 30 LD NC 8 29 VccIF GndRF 9 28 GndIF VccVCO 10 27 IFIN+ VTUNE 11 26 IFIN- GndVCO 12 25 PA Gate NC GndRSSI CAP- CAP+ VccRSSI RSSI VccFM DSL DRX SHOLD MOD DTX GndFM 13 14 15 16 17 18 19 20 21 22 23 24 Figure 5. Pinning configuration. Pin Descriptions: Refer to pin configuration. Pin number Name Function Schematic in/output of the pin VCCPLL 165 k 1 EN Enable 3-wire interface and synthesiser. EN GndPLL VCCPLL 2 REF PLL reference clock input REF GndPLL 3 4 5 VCCPLL GndPLL GndCP Voltage supply to the frequency synthesiser. Ground connection to the frequency synthesiser. Ground connection to the charge pump. Clamp to GndPLL A diode to GndCP and GndRF A diode to GndPLL and GndVCO VCCCP 6 CP Charge pump output. CP GndCP 7 VCCCP Voltage supply to the charge pump. Clamp to GndCP 3 PBL 402 15 Pin Descriptions (cont.): Pin number Name 8 9 10 Function Schematic in/output of the pin Not connected Not connected VCCVCO Voltage supply to the VCO N/C Clamp to GndVCO VCCVCO 11 VTUNE Tuning voltage input for the VCO VTUNE GndVCO 12 13 GndVCO GndFM Ground connection to the VCO Ground connection to the FM discriminator section. A diode to GndCP and GndFM VCCFM 14 DTX Tx data input for either analog or logic signal. DTX GndFM VCCFM 15 MOD Apply modulation. The PLL is set into open loop condition and modulation is applied to the VCO. MOD Bias GndFM VCCFM 16 SHOLD Slice level hold logic input. (In Tx mode this input may also act as the MOD pin). SHOLD GndFM VCCFM 17 DRX Rx data output of FM discriminator for either analog or logic signal.(In standby mode outputs lock detect) DRX GndFM VCCFM 18 DSL Data slice level output. DSL GndFM 19 VCCFM Voltage supply to the FM discriminator section. Clamp to GndFM VCCRSSI 20 RSSI RSSI output of limiting strip detector chain. RSSI GndRSSI 21 VCCRSSI Voltage supply to the RSSI section. Clamp to GndRSSI VCCRSSI 22 CAP+ 23 CAP- External stabilising capacitors for limiting strip DC input offset correction loop. CAP+/CAPBoth inputs alike GndRSSI 4 Bias PBL 402 15 Pin Descriptions (cont.): Pin number 24 Name GndRSSI Function Ground connection to the RSSI. Schematic in/output of the pin A diode to GndFM and GndIF VCCRF 25 PA Gate Output control signal for external PA power on/off. PA - Gate GndRF VCCIF 26 IFIN- 27 IFIN+ Rx IF inputs to internal channel filtering, limiting amplifiers,RSSI and FM discriminator. Internally matched to 300 Ω. IFIN-/IFIN+ both inputs alike GndIF 28 GndIF 29 VCCIF Ground connection to the down IF convertor and channel filter sections. Voltage supply to the down IF convertor and channel filter sections. A diode to GndFM and GndIF Clamp to GndIF VCCRF 30 LD Lock detect. LD GndRF VCCRF 31 IFOUT- 32 IFOUT+ 33, 36 37, 40 GndRF Rx IF outputs to external adjacent channel filter. Internally matched to 300Ω. IFOUT-/IFOUT+ both outputs alike GndRF Ground connection to the RF sections. A diode to GndIF and GndPLL VCCRF 34 35 RXRX+ RF inputs to LNA and image reject mixer. Internally matched to 100Ω. RX-/RX+ both inputs alike GndRF VCCRF 38 39 TXTX+ Tx outputs to external PA. Internally matched to 100 Ω. Each output requires an externalchoke to VCC. 41 VCCRF Voltage supply to the RF sections. TX-/TX+ Both inputs alike GndRF Clamp to GndRF VCCPLL 42 GATE Input to gate the Tx output power. GATE Bias GndPLL VCCPLL 43 D Serial interface, Data . D Bias GndPLL 5 PBL 402 15 Pin Descriptions (cont.): Pin number Name Function Schematic in/output of the pin VCCPLL 44 CK Serial interface, Clock . CK Bias GndPLL VCCPLL 45 ST 165 k Serial interface, Strobe . ST GndPLL VCCPLL 46 TXEN Transmitter enable. TXEN Bias GndPLL 47 DIE Gnd. pin used for internal shielding. Connected to DIE substrate. VCCPLL 48 RXEN Receiver enable RXEN GndPLL 6 Bias PBL 402 15 Maximum Ratings Parameter Condition Symbol Supply voltage Voltage applied between two different supply pins, except VccRF (a) Voltage applied between two Grounds are clamped together different ground pins (a) by diodes Maximum input power LNA input Maximum power dissipation IC storage temperature Lead temperature solder, 10 sec. Min. Typ. Max. Unit Vcc Vccdiff 5.5 0.6 V V Gnddiff 0.6 V Pmax PD TS TLEAD 10 250 150 300 dBm mW °C °C -65 (a). Under continous operation and during power-up sequences. Handling Every pin withstands the ESD test in accordance with MIL-STD-883 (method 3050) and IEC 68-2. CAP IFIN IFOUT π/4 π/4 PIN switch + ÷2 ÷2 + RXIN -π/4 -π/4 RSSI RSSI IR RX TXOUT IF Filt IR IF TX PA-GATE FM Demod GATE + Slave PLL IF2 ÷2 ×2 Slice control PLL Modulator DTX LD VTUNE LD MOD ƒ-φ ÷R CP REF Control D CK ST EN RXEN TXEN SHOLD DSL DRX Figure 6. Block diagram. 7 PBL 402 15 Operating conditions: Parameter Condition Symbol Min. Temperature range Fully compliant Operational TAMB -20 -40 2.7 Supply voltage range Shutdown supply current Supply current Stand-by turn on time (a) Receive turn on time (b) Transmit turn on time (b) One slot duplex communication Vcc IOFF IACTIVE τON τRXON τTXON Typ. Max. Unit 70 85 4.5 2 °C V µA mA µs µs µs 6 3 3 3 a. Time may depend upon settling time of the limiting strip DC correction feedback. b. Time for the receive or transmit gain to be within 1 dB of its final value. Typical current consumption 57mA Tx 17mA 51mA Rx 19mA t Transmit, 1 slot Receive, 1 slot 10 slots Setup to transmit, (blind slot) Setup to receive, (blind slot) Figure 7. Typical current consumtion. Digital I/O Parameters The digital output PA_GATE is served of the VCCRF/GndRF supply. All other digital signals are served of the VCCPLL/GndPLL supply. The digital signals are EN, RXEN,TXEN, ST, D, CK, GATE, LD, MOD and SHOLD. Parameter Input voltage high Input voltage low Output voltage high Output voltage low Digital input capacitance Digital input resistance Digital load capacitance Digital load resistance 8 Condition Symbol Min. VIH VIL VOH VOL CDI RDI CDL RDL 2.1 Typ. Max. 0.6 VCC-0.4 VCC-0.2 0.6 2 100 4 30 Unit V V V V pF kΩ pF kΩ PBL 402 15 The 3-Wire Control Bus Interface. The 3-wire serial bus interface controls the various IC parameters and consists of 3 lines, strobe, data and clock ( ST, D, CK ). Alternatively, selected power control modes may be controlled by 3 hard-wire control lines ( EN, RXEN, TXEN ). The 3-wire bus is active when either EN or ST, or both are active. The strobe signal is used to enable the clock and latch the data frame. Each frame consists of 24 bits, built from a word field and a data field. The word address is the last bit to be sent ( LSB ), with the data field being the proceeding 23 bits. Data on D is shifted into the frame register by clock CK. The 3-wire interface allows setting of word A and word B. These control the IC configuration. Frame definition: LSB Last in MSB First in Word Address Data Frame: F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 Description tag: W0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 Digital Interface: Pin Spec. ST Digital input CK Digital input D EN Digital input Digital input RXEN TXEN Digital input Digital input Description The control section is powered up when ST is low. Data is latched on the rising edge. ST has an internal 160kΩ pull up resistor to VCC PLL. 3-wire interface clock. May be running continuously, but to minimise the risk of VCO spurious it is recommended that the clock only runs when required. 3-wire interface data. Data latched by rising edge of CK. IC enable control. Active low. The control section is powered when EN is active. EN has an internal 160 kΩ pull up resistor to VCC PLL. Receiver enable. Active low. Transmitter enable. Active low. Digital Interface: Parameter Serial clock frequency Delay strobe to first rising clock Data setup time: D to CK Data hold time Clock pulse widh high Strobe hold time high Condition Symbol Min. fCK tSCK tDS tDH tCKW tSW 288 18 18 18 144 Typ. Max. Unit 13.9 MHz ns ns ns ns ns 9 PBL 402 15 tSCK tDS ST Clock enabled tSW Clock disabled tDS tDH D MSB tCKW LSB CK Figure 8. 3-wire timing diagram. Word A. Description. Word A has the address W0 = 0. It permits IC operation and defines the synthesiser frequency. IC operation is controlled by the EN pin and the CE flag. If EN is not active then CE must be enabled for the IC to become and remain operational. If CE is disabled then the IC shuts down completely with only the status of ST and EN determining if the control section takes power. All configurations are erased and must be re-programmed if the chip has been disabled. CL determines if the internal flags or the hard wire control lines are used to control section power. The internal flags provide more flexibility. 10 PBL 402 15 Word A Table. Data address Name Default D0 CE 0 D1 CL 0 D2 D3 D4 D5 D6 D7 CNT_A0 CNT_A1 CNT_A2 CNT_A3 CNT_A4 CNT_M 0 0 0 0 0 0 D8 CNT_R 0 D9 D10 D11 D12 D13 D14 D15 D16 TXVCO_EN Reserved DRX_T 0 0 0 (1) 0 0 0 (1) 0 0 D17 D18 TX_P0 TX_P1 0 0 D19 RX_G 0 D20 D21 D22 IFT0 IFT1 IFT2 1 1 0 (a) (a) RXVCO_EN (a) (a) Description 0 = Chip disable 1 = Chip enable Active low on the external EN pin will also enable the chip 0 = Internal control flags 1 = External control lines Synthesiser frequency counter A bit 0 (LSB) to 4 (MSB) Synthesiser frequency counter M 0 → M = 32 (used for receive) 1 → M = 34 (used for transmit) Synthesiser reference counter R 0 → R = 6 used if REF = 10.368 MHz 1 → R = 8 used if REF = 13.824 MHz Receiver VCO enable . 000 = VCO disabled. Any other setting activates the VCO. (default 100) Transmit VCO enable . 000 = VCO disabled. Any other setting activates the VCO. (default 100) (a) 1 = Analog signal output at DRX pin. 0 = Digital data output at DRX pin. Transmit power trim bits 00 = -1.3 dB Min. 0 (LSB) to 1 (MSB) 01 = Nominal power 10 = +1.3 dB 11 = +1.9 dB Max. IRRX gain. 0 = +0dB extra 1 = +9dB extra Demodulation IF frequency trim bits 0 (LSB) to 2 (MSB). This should be programmed to the default settings. a. Use ´0´ only. b. Recommended at all times. 11 PBL 402 15 Word B. Description. Word B has address W0 =1. It controls modes, functionality and configuration. Word B signals are only active when CE is enabled or EN is active. Word B Table. Data address Default D0 SYN_EN 0 D1 IF_EN 0 D2 RX_EN 0 D3 TX_EN 0 D4 SHOLD_P 0 D5 SHOLD_EN 0 D6 MOD_P 0 D7 MOD_EN 0 D8 MOD_SW 0 D9 GATE_P 0 D10 D11 CPC0 CPC1 0 0 D12 to D23 12 Name Description 1 = Synthesiser power on. 0 = Synthesiser power off. 1 = IF receiver enabled. IF mixer + RSSI + Demodulator + Slave PLL 0 = IF receiver disabled. 1 = Receiver power on. LNA + front end mixer 0 = Receiver power off. 1 = Transmit power on. 0 = Transmit power off. 1 = Slice hold pin SHOLD, active high. 0 = Slice hold pin SHOLD, active low. 1 = Slice hold enable. 0 = Slice hold disable. Active level on the external SHOLD pin determined by SHOLD_P will also enable slice hold. 1 = Modulation pin MOD, active high. 0 = Modulation pin MOD, active low. 1 = Enable modulation. 0 = Disable modulation. Active level on the external MOD pin determined by MOD_P will also enable modulation. 1 = Modulation controlled by the SHOLD pin. 0 = Modulation controlled by the MOD pin. The effect is to multiplex between the MOD & SHOLD pins. 1 = TX gating pin, GATE active high. 0 = TX gating pin, GATE active low. Charge pump operation control. 00 = Normal 01 = Force CP voltage down ( =VCO frequency up ) 11 = Tri-state 10 = Force CP voltage up ( =VCO frequency down ) Reserved. These bits need not to be programmed. PBL 402 15 0 SHOLD "hold" SLICE level 0 MOD b). SHOLD_EN 1 0 SHOLD_P 1 Tristate CP 1 MOD_P MOD_EN PA-timing control a). PA_GATE 0 GATE RF enable 1 GATE_P SYN_EN IF_EN RX_EN TX_EN MOD_SW Charge pump control 12 bit B-word latch CK 24 bit shift register Data 165k 23 bit A-word latch ST Nc CE Synth. IF trim. CL RX gain TX power TXVCO power on DRX control RXVCO power on Digital interface power on 165k SYN_EN EN 0 Synth. power on 1 IF_EN RXEN 0 IF power on 1 RX_EN 0 RX power on 1 TX_EN TXEN 0 TX power on 1 a). See figure PA_GATE timing diagram. b). See figure SLICE control. Figure 9. Control logic. 13 PBL 402 15 Hard Wire Control Lines. The 3 hardwire control lines EN, RXEN and TXEN allow control of the IC by a controller with limited interface access or capabilities. Typically, controllers with only one access per slot or no access between slots. For correct operation the 3 hard wire lines require appropriate programming of the CE and CL flags. The hardwire lines directly force the state of the appropriate word B flags as detailed below. Hard wire line Description EN Powers the serial bus interface. Upon the rising edge of ST and provided CL is set to 1, the effect is as SYN_EN. RXEN Provided EN is active and CL is set to 1, the effect is as IF_EN and RX_EN. TXEN Provided EN is active and CL is set to 1, the effect is as TX_EN. LO and Modulation Section. IF Modulator ×2 ÷2 PLL ƒ-φ ÷R The LO section consists of a TX VCO with a frequency doubler, a RX VCO and a charge pump PLL. The VCO´s are fully integrated and are phase/frequency locked to an external reference frequency applied to the REF pin. The frequency is programmed by the 3-wire interface. Lock detect is available on the LD pin. When neither TX_EN or RX_EN are active, lock detect is also available at the DRX output. The RX VCO runs at twice the frequency. The frequency of the RX VCO is divided by 2 for the PLL. The TX VCO runs at half the TX frequency to improve pulling immunity to TX harmonics. A frequency doubler generates the TX LO for the PLL. The TX VCO is modulated by an external signal applied to the DTX pin. The DTX input is permanently connected to the TXVCO. An active MOD_EN signal disables the PLL charge pump output which allows modulation to be applied. A hardware modulation enable signal may be applied to either the MOD pin or SHOLD pin depending upon setting of the MOD_SW flag. 14 PBL 402 15 TX VCO. A fully integrated balanced VCO. The VCO frequency is controlled by the voltage applied to the VTUNE pin, and the applied modulation voltage. Both have a negative sensitivity, i.e., as the voltage increases, the VCO frequency decreases. The base-band must invert the transit modulation data to allow for this. The tuning voltage is referenced to VCCVCO. The VCO is buffered to provide isolation against frequency pulling and reverse injection. TX VCO Table. Parameter Condition Symbol Min. Carrier frequency range Tuning voltage Frequency tuning sensitivity Frequency pulling 0.4≤VT≤VCC-0.4 ƒC VT ƒSEN ƒPULL 940 0.4 ~-40 Frequency pushing Frequency drift Modulation pushing Modulation tuning sensitivity Analog modulation voltage (a) stand-by ↔RX stand-by ↔TX against VCC, CPC = 2 per slot of 417 µs modulation deviation against VCC modulation deviation against VT ± 144 kHz see table below ƒPUSH ƒDRIFT ƒMPUSH ƒMSEN VMOD Typ. Max. Unit ~-72 967 VCC-0.4 ~-140 MHz V MHz/V kHz 1.5 7.5 ± 375 MHz/V kHz kHz/V kHz/V mVpk (a). The input analog signal is expected to vary between 0V and 0.75V Pre-modulation and post-modulation, it is expected to have a level of 0.375. Typical TX VCO analog modulation voltage table. Channel No 0 Supply voltage VCC = 2.7 Condition For ± 144 kHz Symbol VMOD27 31 0 31 20°C 70°C Unit 239 223 ± 222 211 mVpk ± 208 200 ± 339 320 VCC = 3.3 For ± 144 kHz VMOD33 370 344 ± 315 299 VCC = 3.6 For ± 144 kHz VMOD36 460 ± 419 395 426 ± 390 369 31 0 -20°C mVpk mVpk 15 PBL 402 15 RX VCO. A fully integrated balanced VCO. The VCO frequency is controlled by the voltage applied to the VTUNE pin, and has a negative sensitivity, i.e., as the voltage increases, the VCO frequency decreases. The tuning voltage is referenced to VCCVCO. The VCO is buffered to provide isolation against frequency pulling and reverse injection. A divider by 2 stage, reduces the VCO frequency by 2 for the PLL. RX VCO Table. Parameter Carrier frequency range Tuning voltage Frequency sensitivity Frequency pulling Condition 0.4≤VT≤VCC-0.4 stand-by ↔RX stand-by ↔TX against VCC , CPC = 2 nominal output power Frequency pushing Noise floor The PLL. Symbol ƒC VT ƒSEN ƒPULL REF R Min. 3.53 0.4 ~-100 ÷2 ~-280 ƒPUSH NFLR Max. 3.65 VCC-0.4 ~-460 1,0 -140 Unit GHz V MHz/V kHz MHz/V dBc/Hz 864kHz ÷2 ƒ-φ LO Typ. N/N+1 CP M A LD LD & DRX Store The frequency synthesiser is based on a charge pump PLL ( Phase Locked Loop ). Counter R divides the reference clock, REF. The division ratio, R, is determined by the value of CNT_R. Counters N, A and M form a modulus pulse swallow counter which divides the LO clock by M∗N+A . The value of M is determined by CNT_M. The value of A is taken from the CNT_A. A combined 3 state frequency-phase detector compares the divided REF and LO signals and controls the charge pump.The frequency-phase comparator outputs are controlled by the CPC1-0 bits and MOD_EN. The action of the CPC bits are unsynchronised. The action of MOD_EN is synchronised to the charge pump states, holding the charge pump in tri-state mode when MOD becomes active. An active high lock detect signal is provided when frequency lock has been achieved for 148 µs. The signal is available on the LD pin and on the DRX pin when SYN_EN is active and neither of RX_EN or TX_EN are active. The PLL is designed to work with two different reference frequencies, 10.368 MHz ( = 9 x the DECT bitrate of 1.152 MHz ) or 13.824 MHz ( = 12 x the DECT bitrate of 1.152 MHz ) 16 PBL 402 15 The synthesiser frequency is given by, fRF = (fREF / R) (M * N+A) where: fRF = RF frequency fREF = either 10.368 MHz or 13.824 MHz R = 6 or 8 (see CNT_R) M = 32 or 34 (see CNT_M) N = 32 A = 0, 1, ......,31 PLL Table. Parameter Carrier frequency range Lock time (1) Charge pump current Charge pump leakage Reference frequency Condition 0.4≤VT≤VCC-0.4 tri-state CNT_R=0 CNT_R=1 Reference input voltage Symbol ƒC tLOCK ICP ILEAK ƒREF Min. 1769 VREF 50 Typ. 400 100 10.368 13.824 Max. 1934 320 Unit MHz µs µA pA MHz mVpk (1). Depends upon charge pump loop components. Transmit section. TX GATE Description. The transmitter consists of a band-pass filter, a gated amplifier and a pre-power amplifier. The band-pass filter cleans the output signal of the LO modulator prior to amplification. The gated amplifier is controlled by the GATE pin, with signal polarity determined by the GATE_P flag. The attenuation of the gating amplifier should be used in addition to the external PA to meet the transmit power ramp requirements. An active GATE signal causes the output power to ramp up to its required power level. An inactive GATE signal causes the output power to ramp down to a leakage level. Spectral spreading requirements are best met if the external PA turns on before the power ramp up, and turn off after the power ramp down. Should the external PA be controlled by the same GATE signal, a delayed copy of the GATE signal is provided at the PA _GATE output. The TX output is balanced with an impedance of ~100 Ω and requires external inductors to VCCRF. The transmit power may be trimmed by the TX_P 0-1 bits. The TX is designed for easy interfacing to the PBL 403 09 DECT PA circuit, which is enabled with an active low signal. See application diagram for details. 17 PBL 402 15 Transmit section Table. Parameter Frequency range at output Nominal output power Output power Power of 2xLO spurious Power of 3xLO spurious Output power trim about nominal POFF to PNOM time PNOM to POFF time Gate active to PA_GATE active Gate inactive to PA_GATE inactive Noise floor Noise at channel M±1 Noise at channel M±2 Noise at channel M±3 Noise at channel M±4 Output impedance Output VSWR Condition Gate enable Gate disable TX_P1, 0=0, 0 TX_P1, 0=0, 1 TX_P1, 0=1, 0 TX_P1, 0=1, 1 nominal output power ƒ±1.728 MHz ƒ±3.456 MHz ƒ±5.184 MHz ƒ±6.912 MHz Symbol Min. ƒ PNOM POFF P2LO P3LO PTRIM 1800 5 -22 -35 -35 -1.3 0 +1.3 +1.9 2 2 100 3 tON tOFF tPAON tPAOFF NFLR NM1 NM2 NM3 NM4 ZOUT VSWRO RF signal at TX ∼ 2µs Figure 10. GATE / PA_GATE timing diagram, GATE_P = 0. 18 ∼ 2µs Unit 2000 MHz dBm dBc dBc dBc dB -20 -20 5 5 200 6 -135 -93 -115 -129 -132 1.5:1 t PAOFF PA_GATE (active low) Max. 100 t PAON GATE (active low) Typ. µs µs ns µs dBm/Hz dBc dBc dBc dBc Ω - PBL 402 15 Image Reject Front End. π/4 -π/4 ÷2 IR RX The image reject front end consists of an LNA (Low Noise Amplifier) with dual outputs, 2 mixers, quadrature LO generation, 2 low pass filters, a +π/4 and a -π/4 all-pass filters and a summing output stage. The receiver input is a 1.9 GHz LNA with a characteristic balanced input impedance. The inputs are self biassing and require external matching to the source, with DC blocking capacitors if the source passes DC. The high side image rejection mixer, down converts from RF to an IF frequency of 110.6 MHz. The IF outputs are self biasing and define a balanced output impedance of 300 Ω. The output should be matched to an external adjacent channel filter. The gain is switchable to cater for the insertion loss of different external filters. Image Reject Front End Table. Parameter Condition Symbol Min. Typ. Max. Unit Input frequency range ƒIN 1800 1890 2000 MHz Output frequency range ƒOUT 100 110.6 120 MHz Gain 1 RX_G = 0 G1 18 20 22 dB Gain 2 RX_G = 1 G2 23 25 27 dB Input IP3 RX_G = 0 RX_G = 1 IP3 -21 -17 -23 dBm Input 1 dB compression RX_G = 0 RX_G = 1 CPI1 -24 -31 dBm CPO1 -7 dBm -1.5 dBm 35 dB Output 1 dB compression Output saturation Lower image suppression Tested at ƒIN -2•110.6 MHz SSB 29 Noise figure NF 3.6 Input impedance Output impedance Input VSWR Output VSWR ZIN ZOUT VSWRI VSWRO 100 300 4.1 dB 1.5:1 1.5:1 Ω Ω - 19 PBL 402 15 IF Receiver. The IF receiver consists of an upper sideband image reject down converter, a channel blocking filter, a limiting amplifier and RSSI, an FM discriminator, a post detection filter and a data slicer. The IF inputs are self biasing and have a balanced input impedance of 300 Ω. Matching to the external filter is required. A band-pass filter provides additional channel selection and noise filtering prior to the limiting chain. The quadrature based FM discriminator and post detection filter are self tuned to the required frequency by a slave PLL. The FSK data is recovered by a threshold based data slicer. The slice level is determined up to the end of the 16 bit packet preamble, where it should be held by an active SHOLD signal provided from the base-band controller. The slice controller determines a more accurate level from this signal. An external capacitor is required on the DSL pin. IF ReceiverTable. Parameter Frequency range Input IP3 Input 1dB compression Lower image suppression Noise figure Sensitivity Input impedance Input VSWR Attenuation of channel M±1 Attenuation of channel M±2 Attenuation of channel M±3 Attenuation of channel M±4 Group delay deviation Slice hold capacitor Condition Symbol ƒIF IP3 CP1 SSB NF SENS ZIN VSWRI ATT1 ATT2 ATT3 ATT4 GDD CDSL Tested at ƒIF -23.5 MHz Referenced to 300 Ω BER = 10-3 >ƒC ± 1.152 MHz >ƒC ± 2.88 MHz >ƒC ± 4.608 MHz >ƒC ± 6.336 MHz ƒC ± 576 kHz On DSL pin to Gnd Min. -13 -15 29 Typ. 110.6 Max. -13 14 -79 300 1.5:1 µs nF 0.3 2 PLL Unit MHz dBm dBm dB dB dBm Ω - LD 0 DRX Synth. power on Tx power on Rx power on 1 + Demodulator - 0 1 DRX_T R SHOLD activated DSL When the IF section is powered off, the DSL pin is tri-stated. CDSL R = 2k R = 4k 12 x bit time @ (∼10.4µs) Figure 11. Slice control. 20 R = 200k PBL 402 15 Limiting Amplifier and RSSI ( Received Signal Strength Indicator ). The stage consists of a limiting amplifier chain with an RSSI detector. The inputs are internally coupled from the channel selection filter which limits the noise bandwidth. A balanced DC offset correction loop, provides maximum sensitivity, and ensures a short settling time upon power up. An RSSI output provides a voltage proportional to the logarithm of the rectified input level. The rise time response of the RSSI output and the peak hold is dependent upon the external circuit. Limiting Amplifier strip and RSSI, Table. Parameter Condition Symbol Frequency range ƒ Limiter 1 dB bandwidth ƒ1dB Voltage gain G RSSI range RR RSSI minimum detection level measured at IFIN RDMIN RSSI maximum detection level measured at IFIN RDMAX Min. Typ. Max. 11.7 Unit MHz 22 MHz 74 dB 74 dB -83 -9 dBm dBm RSSI slope RSLOPE 15.2 mV/dB Zero scale RSSI output voltage VRZERO 375 mVpk Full scale RSSI output voltage VRFULL 1500 mVpk ±2.5 RSSI relative error best fit to straight line (a) RERR RSSI rise time 20 pF load tRISE 2 µs CCAP 18 nF Feedback capacitance dB a. The RSSI relative accuracy is the deviation of the RSSI value from a best fit straight line fitted to several calibration points. These points are determined for each part. 21 PBL 402 15 TQFP 48 Pin Package mm DIM. MIN. TYP. A 0.05 A2 1.35 B 0.17 C 0.09 22 TYP. 0.063 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.22 0.27 0.006 0.008 0.010 0.20 0.004 0.008 9.00 0.354 D1 7.00 0.276 D3 5.50 0.217 e 0.50 0.020 E 9.00 0.354 E1 7.00 0.276 E3 5.50 0.45 MAX. 0.15 D 0.60 0.217 0.75 0.018 0.024 L1 1.00 K 0∞(min.), 3.5°(typ.), 7∞(max.) Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB's general conditions of sale, unless otherwise confirmed in writing. Ericsson Microelectronics AB S-164 81 Kista-Stockholm, Sweden Telephone: (08) 757 50 00 www.ericsson.se/microe MIN. 1.60 A1 L Specifications subject to change without notice. 1522-PBL 402 15 Uen Rev.A © Ericsson Microelectronics AB January 2001 inch MAX. 0.039 0.030