ETRON EM636165TS/BE-7G

EtronTech
EM636165
1Mega x 16 Synchronous DRAM (SDRAM)
Preliminary (Rev.2.7, Mar./2006)
Ordering Information
Features
•
•
•
•
•
•
Fast access time: 4.5/5/5/5.5/6.5/7.5 ns
Fast clock rate: 200/183/166/143/125/100 MHz
Self refresh mode: standard and low power
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
• Individual byte controlled by LDQM and UDQM
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• JEDEC standard +3.3V±0.3V power supply
• Interface: LVTTL
• 50-pin 400 mil plastic TSOP II package
• 60-ball, 6.4x10.1mm VFBGA package
• Lead Free Package available for both TSOP II
and VFBGA
Part Number
Frequency
Package
EM636165TS/VE-5
200MHz
TSOP II, VFBGA
EM636165TS/BE-5G
200MHz
TSOP II, VFBGA
EM636165TS/VE-55
183MHz
TSOP II, VFBGA
EM636165TS/BE-55G
183MHz
TSOP II, VFBGA
EM636165TS/VE-6
166MHz
TSOP II, VFBGA
EM636165TS/BE-6G
166MHz
TSOP II, VFBGA
EM636165TS/VE-7
143MHz
TSOP II, VFBGA
EM636165TS/BE-7G
143MHz
TSOP II, VFBGA
EM636165TS/VE-7L
143MHz
TSOP II, VFBGA
EM636165TS/BE-7LG
143MHz
TSOP II, VFBGA
EM636165TS/VE-8
125MHz
TSOP II, VFBGA
EM636165TS/BE-8G
125MHz
TSOP II, VFBGA
EM636165TS/VE-10
100MHz
TSOP II, VFBGA
EM636165TS/BE-10G
100MHz
TSOP II, VFBGA
G : indicates Lead Free Package
Key Specifications
tCK3
tRAS
tAC3
tRC
EM636165
-5/55/6/7/7L/8/10
Clock Cycle time(min.)
5/5.5/6/7/7/8/10ns
Row Active time(max.)
30/32/36/42/42/48/60 ns
Access time from CLK(max.)
4.5/5/5/5.5/5.5/6.5/7.5 ns
Row Cycle time(min.)
48/48/54/63/63/72/90 ns
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
EM636165
Ball Assignment (Top View)
1
2
A
VSS
DQ15
DQ0
VDD
B
DQ14
VSSQ
VDDQ
DQ1
C
DQ13
VDDQ
VSSQ
DQ2
D
DQ12
DQ11
DQ4
DQ3
E
DQ10
VSSQ
VDDQ
DQ5
F
DQ9
VDDQ
VSSQ
DQ6
G
DQ8
NC
NC
DQ7
H
NC
NC
NC
NC
J
NC
UDQM
LDQM
WE#
K
NC
CLK
RAS#
CAS#
L
CKE
NC
NC
CS#
M
A11
A9
NC
NC
N
A8
A7
A0
A10
P
A6
A5
A2
A1
VSS
A4
A3
VDD
R
3
4
5
6
Pin Assignment (Top View)
7
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE#
CAS#
RAS#
CS#
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command
which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
devices are well suited for applications requiring high memory bandwidth and particularly well suited to high
performance PC applications
Preliminary
2
Rev. 2.7 Mar. 2006
EtronTech
EM636165
Block Diagram
CLK
CLOCK
BUFFER
Column Decoder
CS#
RAS#
CAS#
WE#
LDQM
UDQM
COMMAND
DECODER
Row Decoder
CKE
CONTROL
SIGNAL
GENERATOR
2048 X 256 X 16
CELL ARRAY
(BANK #0)
Sense Amplifier
COLUMN
COUNTER
DQs Buffer
A0
A11
ADDRESS
BUFFER
DQ0
│
DQ15
MODE
REGISTER
Row Decoder
Sense Amplifier
REFRESH
COUNTER
2048 X 256 X 16
CELL ARRAY
(BANK #1)
Column Decoder
Preliminary
3
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
Pin Descriptions
Table 1. Pin Details of EM636165
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state
of output and burst address is frozen as long as the CKE remains low. When
both banks are in the idle state, deactivating the clock controls the entry to the
Power Down and Self Refresh modes. CKE is synchronous except after the
device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low
standby power.
A11
Input
Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A10
Input
Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 256K available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
Preliminary
4
Rev. 2.7 Mar. 2006
EtronTech
LDQM,
Input
UDQM
1M x 16 SDRAM
EM636165
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent
I/O buffer controls. The I/O buffers are placed in a high-z state when
LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is
sampled HIGH during a write cycle. Output data is masked (two-clock latency)
when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15DQ8, and LDQM masks DQ7-DQ0.
DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
NC
-
VDDQ
Supply
No Connect: These pins should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V± 0.3V )
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
(0V)
VDD
Supply
Power Supply: +3.3V ± 0.3V
VSS
Supply
Ground
Preliminary
5
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#
Idle(3)
H
X
X
V
V
V
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
X
V
L
V
L
H
L
L
Write and AutoPrecharge
Active(3)
H
X
X
V
H
V
L
H
L
L
Read
Active(3)
H
X
X
V
L
V
L
H
L
H
Read and Autoprecharge
Active(3)
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Idle
L
H
X
X
X
X
H
X
X
X
L
H
H
H
BankActivate
Burst Stop
SelfRefresh Exit
(SelfRefresh)
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any(5)
H
L
X
X
X
X
H
X
X
X
L
H
H
H
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
X
H
X
X
X
L
H
H
H
X
X
X
X
H
X
H
X
X
X
X
X
X
Active
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. LDQM and UDQM
X
Power Down Mode Exit
(PowerDown)
Data Write/Output Enable
Active
H
X
Data Mask/Output Disable
Preliminary
6
L
X
X
X
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Commands
1
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care)
The BankPrecharge command precharges the bank disignated by A11 signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
2
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care)
The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.
3
Read command
(RAS# = "H", CAS# = "L", WE# = "H", A11= “V”, A9 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent dataout element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
T7
T8
CLK
COM MAND
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
READ A
NOP
DOUT A0
NOP
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A0
NOP
NOP
DOUT A3
DOUT A2
DOUT A1
DOUT A3
DOUT A2
DOUT A3
Burst Read Operation(Burst Length = 4, CAS# Latency = 1, 2, 3)
Preliminary
7
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks
earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto
precharge function may be interrupted by a subsequent Read or Write command to the same bank
or the other active bank before the end of the burst length. It may be interrupted by a
BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read
command can occur on any clock cycle following a previous Read command (refer to the following
figure).
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
DOUT B1
DOUT B2
T8
CLK
COM MAND
READ A
CAS# latency=1
tCK1, DQ's
READ B
DOUT A0
CAS# latency=2
tCK2, DQ's
NOP
DOUT B0
DOUT A0
CAS# latency=3
tCK3, DQ's
DOUT B0
DOUT A0
NOP
DOUT B3
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt
comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior
to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O
contention, a single cycle with high-impedance on the DQ pins must occur between the last read
data and the Write command (refer to the following three figures). If the data output of the burst
read occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at
least one clock prior to the Write command to avoid internal bus contention.
T0
T1
T2
NOP
READ A
NOP
T3
T4
T5
T6
T7
T8
NOP
NOP
CLK
DQM
COM MAND
NOP
NOP
DQ's
NOP
DOUT A0
Must be Hi-Z before
the Write Command
WRITE B
DI NB 0
DINB1
DINB 2
: "H" or "L"
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 3)
Preliminary
8
Rev. 2.7 Mar. 2006
EtronTech
T0
T1
EM636165
1M x 16 SDRAM
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
COM MAND
NOP
NOP
BANKA
ACTIVATE
NOP
CAS# latency=1
tCK1, DQ's
READ A
WRITE A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
DIN A0
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
CAS# latency=2
tCK2, DQ's
: "H" or "L"
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 1, 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COM MAND
NOP
NOP
READ A
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
NOP
NOP
WRITE B
NOP
NOP
NOP
DOUT A0
DIN B0
Must be Hi-Z before
the Write Command
DIN B 1
DIN B2
DIN B3
DIN B0
DIN B 1
DIN B2
DIN B3
: "H" or "L"
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 1, 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
ADDRESS
Bank,
Col A
Bank,
Row
Bank(s)
tRP
COMM AND
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2 , DQ's
CAS# latency=3
tCK3 , DQ's
READ A
NOP
DOUT A0
NOP
DOUT A1
DOUT A0
NOP
Precharge
DOUT A2
DOUT A1
DOUT A0
NOP
NOP
Activate
NOP
DOUT A3
DOUT A2
DOUT A1
DOUT A3
DOUT A2
DOUT A3
Read to Precharge (CAS# Latency = 1, 2, 3)
Preliminary
9
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
4
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in
this command and the auto precharge function is ignored.
5
Write command
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
don't care
CLK
COM MAND
NOP
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge.
Extra data is masked.
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
CLK
COMM AND
NOP
WRITE A
WRITE B
1 Clk Interval
DQ's
DIN A0
DIN B0
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
Preliminary
10
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B0
DOUT B1
CLK
COM MAND
NOP
WRITE A
READ B
CAS# latency=1
tCK1, DQ's
DIN A0
CAS# latency=2
tCK2, DQ's
DIN A0
don't care
CAS# latency=3
tCK3, DQ's
DIN A0
don't care
DOUT B0
don't care
DOUT B3
DOUT B2
DOUT B3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the
LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the
last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll
command is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COM MAND
WRITE
ADDRESS
BANK
COL n
Precharge
NOP
NOP
NOP
BANK (S)
Activate
NOP
ROW
tWR
DIN
n
DQ
DIN
n+1
: don't care
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
Preliminary
11
Rev. 2.7 Mar. 2006
EtronTech
6
EM636165
1M x 16 SDRAM
Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
Write A
NOP
T5
T6
T7
T8
CLK
Bank A
Activate
COM MAND
NOP
NOP
AutoPrecharge
NOP
NOP
NOP
NOP
tDAL
CAS# latency=1
tCK1, DQ's
DIN A0
DIN A1
CAS# latency=2
tCK2, DQ's
DIN A0
DIN A1
CAS# latency=3
tCK3, DQ's
DIN A0
DIN A1
*
tDAL
*
tDAL
*
*
Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
tDAL= tWR + tRP
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 1, 2, 3)
7
Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as both banks are in the idle
state.
Preliminary
12
Rev. 2.7 Mar. 2006
EtronTech
T0
T1
EM636165
1M x 16 SDRAM
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCK2
CKE
Clock min.
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
tRP
Hi-Z
DQ
PrechargeAll
Mode Register
Set Command
Any
Command
Mode Register Set Cycle (CAS# Latency = 1, 2, 3)
The mode register is divided into various fields depending on functionality.
Burst Length Field (A2~A0)
•
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
Preliminary
A2
A1
A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Full Page
13
Rev. 2.7 Mar. 2006
EtronTech
•
EM636165
1M x 16 SDRAM
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only
supports burst length of 4 and 8.
A3
Addressing Mode
0
Sequential
1
Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n + m), in
the table is larger than 255, only the least significant 8 bits are effective.
Data n
0
1
2
3
4
5
6
7
-
255
256
257
-
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
-
n+255
n
n+1
-
2 words:
Burst Length
4 words:
8 words:
Full Page: Column address is repeated until terminated.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting
the address bits in the sequence shown in the following table.
Data n
•
Preliminary
Column Address
Burst Length
Data 0
A7
A6
A5
A4
A3
A2
A1
A0
Data 1
A7
A6
A5
A4
A3
A2
A1
A0#
Data 2
A7
A6
A5
A4
A3
A2
A1# A0
Data 3
A7
A6
A5
A4
A3
A2
A1# A0#
Data 4
A7
A6
A5
A4
A3
A2# A1
A0
Data 5
A7
A6
A5
A4
A3
A2# A1
A0#
Data 6
A7
A6
A5
A4
A3
A2# A1# A0
Data 7
A7
A6
A5
A4
A3
A2# A1# A0#
4 words
8 words
CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS# Latency depends on the frequency
of CLK. The minimum whole value satisfying the following formula must be programmed
into this field.
tCAC(min) ≤ CAS# Latency X tCK
A6
A5
A4
CAS# Latency
0
0
0
Reserved
0
0
1
1 clock
0
1
0
2 clocks
0
1
1
3 clocks
1
X
X
Reserved
14
Rev. 2.7 Mar. 2006
EtronTech
•
•
EM636165
1M x 16 SDRAM
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8
A7
Test Mode
0
0
normal mode
0
1
Vendor Use Only
1
X
Vendor Use Only
Single Write Mode (A9)
This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-BurstWrite mode is selected. When the BS bit is "1", the Burst-Read-Single-Write mode is
selected.
A9
Single Write Mode
0
Burst-Read-Burst-Write
1
Burst-Read-Single-Write
Note: A10 and A11 should stay “L” during mode set cycle.
8
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
9
Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
CLK
COMMAND
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
READ A
NOP
DOUT A0
NOP
NOP
Burst Stop
The burst ends after a delay equal to the CAS# latency.
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Termination of a Burst Read Operation (Burst Length ＞ 4, CAS# Latency = 1, 2, 3)
Preliminary
15
Rev. 2.7 Mar. 2006
EtronTech
T0
T1
EM636165
1M x 16 SDRAM
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
CLK
COM MAND
CAS# latency=1, 2, 3
DQ's
NOP
WRITE A
NOP
NOP
Burst Stop
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)
10
Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
11
AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need
to be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
12
SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited
by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
13
SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
Preliminary
16
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
14
Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
Timing Waveforms)
(CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from
the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
15
Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms, CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.
16
Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every
word of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output
buffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memory
system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
Preliminary
17
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Absolute Maximum Rating
Symbol
Item
Rating
Unit
Note
-5/55/6/7/7L/8/10
VIN, VOUT
Input, Output Voltage
- 1.0 ~ 4.6
V
1
VDD, VDDQ
Power Supply Voltage
-1.0 ~ 4.6
V
1
TOPR
Operating Temperature
0 ~ 70
°C
1
TSTG
Storage Temperature
- 55 ~ 125
°C
1
PD
Power Dissipation
1
W
1
IOUT
Short Circuit Output Current
50
mA
1
Recommended D.C. Operating Conditions (Ta = -0~70°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
VDD
Power Supply Voltage
3.0
3.3
3.6
V
2
VDDQ
Power Supply Voltage(for I/O Buffer)
3.0
3.3
3.6
V
2
VIH
LVTTL Input High Voltage
2.0
－
VDDQ+0.3
V
2
VIL
LVTTL Input Low Voltage
- 0.3
－
0.8
V
2
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
Symbol
CI
CI/O
Parameter
Min.
Max.
Unit
Input Capacitance
2
5
pF
Input/Output Capacitance
4
7
pF
Note: These parameters are periodically sampled and are not 100% tested.
Preliminary
18
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0~70°C)
Description/Test condition
- 5/55/6/7/8/10
Max.
Symbol
Operating Current
1 bank
tRC ≥ tRC(min), Outputs Open, Input operation
signal one transition per one cycle
Precharge Standby Current in non-power down mode
tCK = tCK(min), CS# ≥ VIH, CKE = VIH
Input signals are changed once during 30ns.
Precharge Standby Current in power down mode
tCK = tCK(min), CKE ≤ VIL(max)
Precharge Standby Current in power down mode
tCK = ∞,CKE ≤ VIL(max)
- 7L
Unit
130/125/115/100/95/85
40
3
115/110/90/85/75/60
15
3
2
0.8
IDD2PS
2
0.8
IDD3P
2
1.5
IDD3N
105/100/90/80/70/55
20
165/160/150/140/130/115
40
3, 4
115/110/100/90/90 /80
40
3
IDD1
IDD2N
IDD2P
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = tCK(min)
Active Standby Current in non-power down mode
CKE ≥ VIL(max), tCK = tCK(min)
Operating Current (Burst mode)
tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless
data
Refresh Current
tRC ≥ tRC(min)
Self Refresh Current
VIH ≥ VDD - 0.2, 0V ≤ VIL ≤ 0.2V
IDD4
IDD5
2
IDD6
Description
Min.
Max.
IIL
Input Leakage Current
( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )
- 10
10
µA
IOL
Output Leakage Current
Output disable, 0V ≤ VOUT ≤ VDDQ)
- 10
10
µA
VOH
LVTTL Output "H" Level Voltage
( IOUT = -2mA )
2.4
－
V
VOL
LVTTL Output "L" Level Voltage
( IOUT = 2mA )
－
0.4
V
19
3
mA
0.6
Parameter
Preliminary
Note
Unit Note
Rev. 2.7 Mar. 2006
3
EtronTech
EM636165
1M x 16 SDRAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, Ta = -0~70°C) (Note: 5, 6, 7, 8)
Symbol
tRC
tRCD
tRP
tRRD
tRAS
tWR
Min.
Row cycle time
(same bank)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate
command (same bank)
Row activate to row activate delay
(different banks)
Row activate to precharge time
(same bank)
Write recovery time
tCK1
tCK2
- 5/55/6/7/7L/8/10
A.C. Parameter
Clock cycle time
tCK3
Max.
9
15/16/16/16/16/16/30
9
ns
15/16/16/1616//16/30
10/11/12/14/14/16/20
30/32/36/42/42/48/60
-/19/20/20/20/20/30
CL* = 2
-/7/7.5/8/8/8/15
CL* = 3
5/5.5/6/7/7/8/10
100,000
Cycle
10
ns
Clock high time
2/2/2/2.5/2.5/3/3.5
tCL
Clock low time
2/2/2/2.5/2.5/3/3.5
tAC1
Access time from CLK
CL* = 1
-/7/8/13/13/18/27
tAC2
(positive edge)
CL* = 2
-/5.5/6/6.5/6.5/7/12
CL* = 3
4.5/5/5/5.5/5.5/6.5/7.5
CAS# to CAS# Delay time
tOH
Data output hold time
tLZ
Data output low impedance
tHZ
Data output high impedance
tIS
Data/Address/Control Input set-up time
tIH
Data/Address/Control Input hold time
tPDE
PowerDown Exit set-up time
tREF
Refresh time
9
9
1
CL* = 1
tCCD
Note
48/48/54/63/63/72/90
tCH
tAC3
Unit
11
11
1
11
Cycle
1.8/2/2/2/2/2/3
10
1/1/1/1/1/2/2
3/3.5/4/5/5/6/8
2/2/2/2/2/2.5/3
8
ns
1
11
11
2/2/2/2/2/2.5/3
64
ms
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 12.
Preliminary
20
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
6. A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2kΩ
Z0= 50 Ω
Output
Output
30pF
30pF
87 0Ω
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
12. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that
LDQM/UDQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required before or after the Mode Register
Set command in step 4 to stabilize the internal circuitry of the device.
Preliminary
21
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Timing Waveforms
Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
tCL
tCH
t IS
CKE
t IS
Begin AutoPrecharge
Bank A
Begin AutoPrecharge
Bank B
tIH
t IS
CS#
RAS#
CAS#
WE#
A11
tIH
A10
RBx
RAx
RAy
RAz
RBy
RAz
RBy
t IS
A0-A9
CAx
RBx
CBx
RBx
RAy
CAy
DQM
tRCD
tDAL
tRC
t IS
DQ
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Activate
Write with
Activate
Write with
Activate
Command AutoPrecharge Command AutoPrecharge Command
Bank A
Command
Bank B
Command
Bank A
Bank A
Bank B
Preliminary
22
t WR
tIH
Hi-Z
Ay0
Ay1
Write
Command
Bank A
Ay2
tRP
tRRD
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 11
T12
T13
CLK
tCK2
tCH tCL
CKE
Begin AutoPrecharge
Bank B
t IS
t IH
tIH
t IS
CS#
RAS#
CAS#
WE#
A11
tIH
A10
RBx
RAx
RAy
t IS
A0-A9
RAx
CAx
CBx
RBx
RAy
tRRD
tRAS
tRC
DQM
tAC2
tLZ
tRCD
Hi-Z
DQ
tAC2
Ax0
tRP
tHZ
Ax1
Bx0
tHZ
tOH
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Activate
Command
Bank B
23
Bx1
Read with
Auto Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
tRC
tRP
DQM
CAx
tRC
Ax0 Ax1
DQ
PrechargeAll
Command
Preliminary
AutoRefresh
Command
AutoRefresh
Command
Activate
Command
Bank A
24
Ax2
Ax3
Read
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High level
is reauired
CKE
Minimum of 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
tRP
DQ
tRC
Hi-Z
PrechargeALL
Command
Inputs must be
stable for 200 µs
1st AutoRefresh
Command
Mode Register
Set Command
(*)
2nd Auto Refresh
Command
(*)
Any
Command
Note (*) : The Auto Refresh command can be issued before or after Mode Register Set command
Preliminary
25
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 5. Self Refresh Entry & Exit Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CLK
*Note 2
*Note 4
*Note 1
tRC(min)
tPDE
*Note 3
CKE
*Note 7
tSRX
*Note 5
t IS
*Note 6
CS#
RAS#
*Note 8
*Note 8
CAS#
A11
A0-A9
WE #
DQM
Hi-Z
DQ
Hi-Z
Self Refresh Enter
SelfRefresh Exit
AutoRefresh
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
1. System clock restart and be stable before returning CKE high.
2. Enable CKE and CKE should be set high for minimum time of tSRX.
3. CS# starts from high.
4. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Preliminary
26
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T
7
T8
T9
T10 T 11 T1
T13 T14 T15 T16 T17 T1
T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
A0-A9
RAx
RAx
CAx
DQM
tHZ
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax3
Ax2
Clock Suspend Clock Suspend
2 Cycles
1 Cycle
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
27
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Clock Suspend
1 Cycle
Ax3
Ax2
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
28
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T 1 T 2 T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
tHZ
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
29
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
Figure 7.1. Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS# Latency = 1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ Hi-Z
DAx0
DAx1
DAx2
Activate Clock Suspend Clock Suspend
Command
1 Cycle
2 Cycles
Bank A
Write
Command
Bank A
DAx3
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Preliminary
30
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
T2
2
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ Hi-Z
DAx0
Activate
Command
Bank A
DAx1
DAx2
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
DAx3
Clock Suspend
3 Cycles
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Preliminary
31
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
Figure 7.3. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ Hi-Z
DAx0
Activate
Command
Bank A
DAx1
DAx2
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
DAx3
Clock Suspend
3 Cycles
Write
Command
Bank A
Note: CKE to CLK disable/enable = 1 clock
Preliminary
32
Rev. 2.7 Mar. 2006
EtronTech
1M x 16 SDRAM
EM636165
Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
tPDE
t IS
CKE
Valid
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
DQM
tHZ
Hi-Z
Ax0
DQ
ACTIVE
STANDBY
Activate
Read
Command
Command
Bank A
Bank A
Power Down
Power Down
Mode Entry
Mode Exit
Preliminary
Ax1
Ax2
Clock Mask
Start
Clock Mask
End
Ax3
Precharge
Command
Bank A
Power Down
Mode Entry
33
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Command
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 9.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAz
RAw
RAw CAw
A0~A9
CAy
CAx
RAz
CAz
DQM
DQ
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
Aw1 Aw2
Aw3 Ax0
Read
Command
Bank A
Ax1
Ay0
Ay1 Ay2
Read
Command
Bank A
Ay3
Az0
Az1 Az2
Az3
Precharge
Read
Command
Command
Bank A
Bank A
Activate
Command
Bank A
34
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 9.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
A0~A9
RAw
RAz
CAw
CAx
RAz
CAy
CAz
DQM
DQ Hi-Z
Aw0
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Aw1 Aw2
Read
Command
Bank A
Aw3
Ax0
Ax1 Ay0
Read
Command
Bank A
Ay1
Ay2
Precharge
Command
Bank A
35
Az0
Ay3
Activate
Command
Bank A
Az1
Az2
Az3
Read
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 9.3. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAz
RAw
A0~A9
RAw
CAw
CAx
CAy
RAz
CAz
DQM
DQ Hi-Z
Aw0
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Aw1 Aw2
Read
Command
Bank A
Aw3
Ax0 Ax1
Read
Command
Bank A
36
Ay0
Ay1
Precharge
Command
Bank A
Ay2
Az0
Ay3
Activate
Command
Bank A
Read
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 10.1. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RBz
RBw
RBw
CBw
CBy
CBx
RBz
CBz
DQM
Hi-Z
DQ
DBw0 DBw1DBw2 DBw3 DBx0
Activate
Command
Bank A
Write
Command
Bank B
Preliminary
DBx1 DBy0 DBy1 DBy2 DBy3
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
37
DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
A0~A9
RBw
RBz
CBw
CBx
RBz
CBy
CBz
DQM
DQ
Hi-Z
DBz0 DBz1 DBz2 DBz3
DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank A
Preliminary
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
38
Activate
Command
Bank B
Write
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 10.3. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
A0~A9
RBw
RBz
CBw
CBx
RBz
CBy
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank A
Preliminary
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
39
DBz0 DBz1 DBz2
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
A0~A9
RBx
RBy
RAx
RAx
CBx
RBy
CAx
CBy
tRCD
tRP
tAC1
DQM
Hi-Z
DQ
Bx0
Activate
Command
Bank B
Read
Command
Bank B
Preliminary
Bx1
Bx2
Bx3 Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2 Ax3
Precharge
Command
Bank B
Activate
Read
Command
Command
Bank B
Bank A
Activate
Command
Bank A
40
Ax4
Ax5
Ax6
Ax7
By0
Read
Command
Bank B
By1
By2
Precharge
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 11.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RBx
A0~A9
RAx
CBx
tRCD
RBy
RBy
CAx
tAC2
tRP
DQM
Hi-Z
DQ
Activate
Command
Bank B
Preliminary
Bx0
Read
Command
Bank B
CBy
Bx1
Bx2
Bx3 Bx4
Activate
Command
Bank A
Bx5
Bx6
Bx7
Ax0
Precharge
Command
Bank B
Read
Command
Bank A
41
Ax1
Activate
Command
Bank B
Ax2 Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
Read
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 11.3. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RBx
A0~A9
RAx
CBx
tRCD
RBy
RBy
CAx
CBy
tRP
tAC3
DQM
Hi-Z
DQ
Activate
Command
Bank B
Preliminary
Bx0
Read
Command
Bank B
Bx1 Bx2
Activate
Command
Bank A
Bx3
Bx4
Bx5
Read
Command
Bank A
42
Bx6 Bx7
Precharge
Command
Bank B
Ax0
Ax1 Ax2
Activate
Command
Bank B
Ax3
Ax4
Ax5 Ax6
Read
Command
Bank B
Ax7
By0
Precharge
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 12.1. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKEHigh
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
RBx
RAy
RBx CBx
RAy
tRCD
tRP
CAy
tWR
DQM
Hi-Z
DQ
DAx0
DAx1 DAx2DAx3
Activate
Command
Bank A
Write
Command
Bank A
Preliminary
DAx4
DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6 DBx7
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
43
DAy0 DAy1 DAy2 DAy3
Precharge
Command
Bank B
Write
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
RBx
tRCD
DQM
RAy
RBx
DQHi-Z
Activate
Command
Bank A
CBx
tWR*
RAy
tRP
CAy
tWR*
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1DAy2
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
DAy3 DAy4
Write
Command
Bank A
Precharge
Command
Bank B
* tWR > tWR(min.)
Preliminary
44
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RAy
RBx
CAx
RBx
CBx
tRCD
RAy
tWR*
tRP
CAy
tWR*
DQM
DQHi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
DBx3 DBx4 DBx5 DBx6 DBx7 DAy0
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
DAy1 DAy2 DAy3
Precharge
Command
Bank B
* tWR > tWR(min.)
Preliminary
45
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
CAy
CAz
DQM
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Read
Write
The Write Data
Command is Masked with a Command
Bank A
Bank A
Zero Clock
Latency
46
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
CAz
CAy
DQM
DQ Hi-Z
Ax0
Activate
Command
Bank A
Preliminary
Read
Command
Bank A
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Write The Write Data
Command is Masked with a
Bank A
Zero Clock
Latency
47
Az0
Read
Command
Bank A
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAy
CAx
CAz
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Preliminary
Ax1
Ax2
Ax3
DAy0 DAy1
Read
Command
Bank A
DAy3
Write
The Write Data
Read
Command is Masked with a Command
Bank A
Zero Clock
Bank A
Latency
48
Az0
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RAx
RBw
RAx RAx
RBw
CBw
Ax2
Ax3
CBy
CBx
CAy
CBz
tRCD tAC1
DQM
DQ Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
Ax1
Bw0
Activate
Command
Bank B
Read
Command
Bank B
Bw1
Bx0
Read
Command
Bank B
Bx1
By0
Read
Command
Bank B
49
By1 Ay0
Read
Command
Bank A
Ay1
Bz0
Read
Command
Bank B
Bz1
Bz2
Precharge
Command
Bank A
Bz3
Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RAx
CAy
tRCD
DQM
RAx
Ax0
Preliminary
CBy
CAy
CBz
By0
By1 Ay0
tAC2
DQ Hi-Z
Activate
Command
Bank A
CBx
CBw
Read
Command
Bank A
Ax1
Activate
Command
Bank B
Ax2
Ax3 Bw0
Read
Command
Bank B
Read
Command
Bank B
Bw1
Bx0
Bx1
Read
Command
Bank B
50
Read
Command
Bank A
Ay1
Read
Command
Bank B
Precharge
Command
Bank A
Bz0
Bz1
Bz2 Bz3
Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBx
CAx
tRCD
DQM
RBx
CBx
Ax0
Preliminary
CBz
CAy
tAC3
DQ Hi-Z
Activate
Command
Bank A
CBy
Read
Command
Bank A
Activate
Command
Bank B
Ax1 Ax2
Read
Command
Bank B
Ax3 Bx0
Read
Command
Bank B
51
Bx1
By0 By1
Read
Command
Bank B
Bz0
Bz1 Ay0
Read Prechaerge
Command Command
Bank B
Bank A
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBw
CAx
RBw
CBw
CBx
CBy
CBz
CAy
tRP
tWR tRP
tRCD
DQM
tRRD
DQ
Hi-Z
DAx0
Activate
Command
Bank A
DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Preliminary
52
Write
Command
Bank A
DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBw
CAx
RBw
CBw
CBx
CBy
CAy
tRCD
DQM
CBz
tRP
tWR
tRP
tRRD
DQ Hi-Z
DAx0 DAx1 DAx2
Activate
Command
Bank A
Preliminary
Write
Command
Bank A
Activate
Command
Bank B
DAx3 DBw0 DBw1 DBx0
Write
Command
Bank B
Write
Command
Bank B
DBx1 DBy0
DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Write
Command
Bank B
53
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
A0~A9
RAx
CAx RBw
CBw
CBx
CBy
CAy
tRCD
DQM
CBz
tWR
tRP
tWR(min)
tRRD > tRRD(min)
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank A
Preliminary
Activate
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
54
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBy
RBx
RBx CBx
CAx
RBz
CAy
RBy
Bx3
Ay0
CBy
RBz
CBz
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Preliminary
Ax1
Ax2
Ax3
Bx0
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Bx1
Bx2
Ay1
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank A
55
Ay2
Ay3
By0
Read with
Auto Precharge
Command
Bank B
By1
By2
By3
Bz0
Bz1
Bz2
Bz3
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CAS#
WE #
A11
A10
RAx
A0~A9
RAx
RBx
CAx
RAz
RBy
RBx
CBx
RBy
RAy
CBy
CAz
RAz
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
Ax0
Read
Command
Bank A
Ax1
Ax2
Ax3
Activate
Read with
Command Auto Precharge
Bank B
Command
Bank B
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3
Az0
Az1
Az2
Read with
Activate
Read with
Activate
Read with
Auto Precharge Command Auto Precharge Command Auto Precharge
Command
Bank B
Command
Bank A
Command
Bank A
Bank B
Bank A
56
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
A0~A9
RAx
CAx RBx
RBy
CBx
CAy
CBy
RBy
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
Ax0
Activate
Command
Bank B
Read
Command
Bank A
Ax1
Ax2
Read with
Auto Precharge
Command
Bank B
Ax3
Bx0
Bx1 Bx2
Read with
Auto Precharge
Command
Bank A
57
Bx3
Ay0
Activate
Command
Bank B
Ay1
Ay2 Ay3
By0 By1
By2
By3
Read with
Auto Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RAx
RBx
RAx CAx
RBx
RAz
RBy
CBx
CAy
RBy
CBy
RAz
CAz
DQM
DQ Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank A
Write
Command
Bank A
Preliminary
Write with
Activate
Command Auto Precharge
Command
Bank B
Bank B
Write with
Auto Precharge
Command
Bank A
Write with
Activate
Command Auto Precharge
Command
Bank B
Bank B
58
DAz0 DAz0 DAz0 DAz0
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RAx
RAx
RBy
RBx
CAx
RBx
CBx
CAy
RBy
RAz
CBy
RAz
CAz
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Write with
Activate
Command Auto Precharge
Command
Bank B
Bank B
Write with
Auto Precharge
Command
Bank A
59
DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3
Write with
Activate
Write with
Activate
Command Auto Precharge Command Auto Precharge
Command
Bank A
Command
Bank B
Bank B
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE High
CS#
RAS#
CAS#
WE#
`
A11
A10
RAx
A0~A9
RAx
RBy
RBx
CAx
RBx
CBx
CAy
RBy
CBy
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank B
Write
Command
Bank A
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
60
Activate
Command
Bank B
DBy0 DBy1 DBy2 DBy3
Write with
Auto Precharge
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBy
CAx RBx
RBy
CBx
tRP
tRRD
DQM
DQ
RBx
Hi-Z
Ax
Activate
Command
Bank A
Ax+1 Ax+2 Ax-2 Ax-1
Activate
Command
Bank B The burst counter wraps
from the highest order
Read
page address back to zero
Command
during this time interval
Bank A
Preliminary
Ax
Ax+1 Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Read
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
61
Bx+6 Bx+7
Precharge
Command
Bank B
Activate
Burst Stop
Command
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CL K
tCK2
CKE
High
CS#
RAS#
CAS#
WE #
A11
A10
RAx
A0~A9
RAx
RBx
CAx
RBy
CBx
RBx
RBy
tRP
DQM
DQ Hi-Z
Activate
Command
Bank A
Preliminary
Ax
Read
Command
Bank A
Ax+1 Ax+2 Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3
Bx+4 Bx+5
Bx+6
Activate
Read
Precharge
Full Page burst operation does not
Command
Command
Command
Bank B
Bank B terminate when the burst length is satisfied;
Bank B
The burst counter wraps
the burst counter increments and continues
from the highest order
bursting beginning with the starting address.
page address back to zero
Burst Stop
during this time interval
Command
62
Activate
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBy
RBx
CAx
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
Ax
Read
Command
Bank A
Activate
Command
Bank B
Ax+1 Ax+2 Ax-2
Ax-1
Ax
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Full Page burst operation does not Precharge
Command
terminate when the burst length is
Bank B
satisfied; the burst counter
increments and continues
bursting beginning with the
Burst Stop
starting address.
Command
63
Activate
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBx
CAx
RBx
RBy
RBy
CBx
DQM
DQ
Hi-Z
DBx
DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1
Activate
Command
Bank B
The burst counter wraps
from the highest order
Write
page address back to zero
Command
during this time interval
Bank A
Activate
Command
Bank A
Preliminary
DBx+1
DBx+ 2 DBx+ 3 DBx+4 DBx+5 DBx+6 DBx+7
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
64
Data is ignored
Precharge
Command
Bank B
Burst Stop
Activate
Command
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RAx
RAx
RBx
CAx
RBx
RBy
RBy
CBx
DQM
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx DBx+1 DBx+ 2 DBx+ 3 DBx+4 DBx+ 5 DBx+ 6
Write
Command
Bank A
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
65
Data is ignored
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RBx
CAx
RBx
RBy
RBy
CBx
DQM
Data is ignored
DQ
Hi-Z
Activate
Command
Bank A
Preliminary
DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5
Write
Command
Bank A
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
66
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAy
CAx
CAz
LDQM
UDQM
DQ0 - DQ7
Ax0
DQ8 - DQ15
Activate
Command
Bank A
Preliminary
Read Upper 3 Bytes
Command are masked
Bank A
Ax1
Ax2
Ax1
Ax2
Lower Byte
is masked
DAy1 DAy2
Ax3
DAy0 DAy1
DAy3
Write
Upper 3 Bytes Read
Command are masked Command
Bank A
Bank A
67
Az0
Az1
Az2
Az1
Az2
Lower Byte
is masked
Az3
Lower Byte
is masked
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 21. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
High
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RBu
RBu
CBu
RAu
RBv
RAv
RAu CAu
RBv CBv
RAv
tRP
DQM
DQ
Bu0
Bu1 Au0
CAv
tRP
Au1
RAw
RBw
RBw CBw
tRP
Bv0 Bv1
Av0
RAw CAw RBx
t RP
Av1
RBx
tRP
Bw0 Bw1
RAx
CBx RAx CAx
t RP
Aw0
Aw1 Bx0
RAy
RBy CBy
RAy CAy RBz
tRP
Bx1
RBz
RBy
tRP
Ax0
Ax1 By0
tRP
By1
RAz
CBz RAz
t RP
Ay0 Ay1
Bz0
Activate
Command
Bank B
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Activate
Command
Command
Command
Command
Command
Command
Command
Command
Command
Command
Command
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
with Auto
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Precharge
Preliminary
68
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CL K
tCK2
CKE
CS#
RAS#
CAS#
WE #
A11
A10
RAx
A0~A9
RAx
RBx
RBx
RBw
CAx
CBx
CAy
CBy
CAz
CBz
RBw
tRP
DQM
tRRD
tRCD
DQ
Ax0
Activate
Command
Bank A
Preliminary
Activate
Command
Bank B
Read
Command
Bank B Read
Read
Command
Command
Bank A
Bank A
Bx0
Ay0 Ay1
Read
Command
Bank B
By0
By1
Read
Command
Bank A
69
Az0 Az1
Read
Command
Bank B
Az2
Bz0 Bz1
Bz2
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RAx
A0~A9
RBw
RBx CAx
CBx
CAy
CBy
CAz
CBz
RBw
t WR
tRP
DQM
tRRD
tRCD
DQ
DAx0 DBx0 DAy0
Activate
Command
Bank A
Preliminary
Activate
Command
Bank B
DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1
Write
Command
Bank B
Write
Write
Command Command
Bank A
Bank A
Write
Command
Bank B
Write
Command
Bank A
70
Write
Command
Bank B
DBz2
Precharge
Command Bank B
(Precharge Temination)
Activate
Write Data Command
Bank B
is masked
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RAx
RAx
RAy
CAx
RAy
RAz
CAy
RAz CAz
tRP
tWR tRP
DQM
DQ
DAx0
DAx1DAx2 DAx3 DAx4
Ay0
Read
Activate
Precharge Termination Precharge
Command
Command
Command
of a Write Burst.
Bank
A
Bank A
Bank A
Write data is masked.
Write
Activate
Command
Command
Bank A
Bank A
Preliminary
71
Precharge
Termination of
a Read Burst.
DAz0
Ay1 Ay2
Precharge
Command
Bank A
DAz1 DAz2DAz3
DAz4 DAz5
DAz6 DAz7
Write
Command
Bank A
Activate
Command
Bank A
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 24.2. Precharge Termination of a Burst
(Burst Length=8 or Full Page, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
RAy
RAy
CAx
tWR
RAz
CAy
RAz
tRP
CAz
tRP
tRP
DQM
DQ
DAx0 DAx1DAx2 DAx3
Activate
Command
Bank A
Write
Command
Bank A
Ay0
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge Termination
of a Write Burst.
Write data is masked.
Preliminary
72
Ay1
Ay2
Precharge
Command
Bank A
Activate
Command
Bank A
Az0
Az1
Az2
Precharge
Read
Command
Command
Bank A
Bank A
Precharge Termination
of a Read Burst
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
Figure 24.3. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
High
CS#
RAS#
CAS#
WE#
A11
A10
A0~A9
RAx
RAx
RAy
RAy
CAx
t WR
RAz
CAy
RAz
tRP
tRP
DQM
DQ
Ay0
DAx0 DAx1
Activate
Command
Bank A
Write
Command
Bank A
Write Data
is masked
Preliminary
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Ay1
Ay2
Activate Precharge Termination
Command
of a Read Burst
Bank A
Precharge Termination
of a Write Burst
73
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
50 Pin TSOP II Package Outline Drawing Information
50
HE
E
0.254
26
θ°
L
L1
1
25
S
Symbol
B
e
L
L1
y
Dimension in inch
Min
Normal
Max
0.047
－
－
0.002
0.005
0.008
0.039
－
－
0.012
0.015
0.018
0.006
－
－
0.82
0.825
0.83
0.398
0.400
0.402
0.031
－
－
0.459
0.463
0.467
0.016
0.020
0.024
0.0315
－
－
0.035
－
－
0.004
－
－
－
0°
5°
Min
－
0.05
－
0.3
－
20.82
10.11
－
11.66
0.40
－
－
－
0°
A
A1
A2
B
c
D
E
e
HE
L
L1
S
y
θ
Notes :
1. Dimension D&E do not include interiead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension : mm
Preliminary
C
A1 A2
A
D
74
Dimension in mm
Normal
－
0.125
－
0.375
0.155
20.95
10.16
0.80
11.76
0.50
0.80
0.88
－
－
Max
1.20
0.20
1
0.45
－
21.08
10.21
－
11.86
0.60
－
－
0.10
5°
Rev. 2.7 Mar. 2006
EtronTech
EM636165
1M x 16 SDRAM
1Mx16 SDRAM Package Diagrams
60-Ball (6.4mm x 10.1mm)VFBGA
Units in mm
BOTTOM VIEW
⊕
TOP VIEW
∅ 0.08 M
A1 CORNER
∅ 0.16 M
A1 CORNER
1
2
3
C
C
A
B
∅=0.30
4
5
6
7
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
F
F
G
G
H
J
H
9.10
10.10±0.10
A
J
K
L
L
M
M
N
N
0.65
K
P
P
R
R
0.65
A
3.90
D
B
0.10(4X)
C
D
EM636165VE : 1.00 MAX
EM636165BE : 1.20 MAX
6.40±0.10
0.10(4X)
C
SEATING PLANE
Preliminary
75
Rev. 2.7 Mar. 2006