EXAR ST16C1450

ST16C1450
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2.97V TO 5.5V UART
AUGUST 2005
REV. 4.2.1
GENERAL DESCRIPTION
FEATURES
The ST16C1450 is a universal asynchronous
receiver and transmitter (UART). The 1450 is foot
print compatible to the SSI 73M1550 and SSI
73M2550 UART with one byte FIFO and higher
operating speed and lower access time. The 1450
provides enhanced UART functions with a modem
control interface, independent programmable baud
rate generators with clock rates to 1.5 Mbps. On
board status registers provide the user with error
indications and operational status. System interrupts
and modem control features may be tailored by
external software to meet specific user requirements.
An internal loop-back capability allows on board
diagnostics. The 1450 is available in a 28-pin PLCC
and 48-pin TQFP packages. The baud rate generator
can be configured for either crystal or external clock
input. The 48-pin TQFP package provides a buffered
reset output that can be controlled through user
software. The 1450 is fabricated in an advanced
CMOS process to achieve low drain power and high
speed requirements.
The ST16C1450 is not
compatible with the industry standard 16450 and will
not work with the standard serial port driver in MS
Windows (see pages 12-13 for details). For a MS
Windows compatible UART, see the ST16C450.
• Pin and functionally compatible to SSI 73M1550/
2550
• 1 byte Transmit FIFO (THR)
• 1 byte Receive FIFO with error tags (RHR)
• Four levels of prioritized interrupts
• Modem Control Signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
• Programmable character lengths (5, 6, 7, 8) with
even, odd or no parity
• Crystal or external clock input
• 1.5 Mbps Transmit/Receive operation (24 MHz)
with programmable clock control
• Power Down Mode (50 uA at 3.3 V, 200 uA at 5 V)
• Software controllable reset output
• 2.97 to 5.5 Volt operation
APPLICATIONS
• Battery Operated Electronics
• Internet Appliances
• Handheld Terminal
• Personal Digital Assistants
• Cellular Phones DataPort
FIGURE 1. BLOCK DIAGRAM
THR
A 2:A 0
T ran sm itter
D 7:D 0
TX
IO R #
IO W #
CS#
IN T
D ata B u s
In terface
UART
C o n fig u ratio n
R eg s
D T R #, R T S #
M o d em C o n tro l Sig n a ls
R eceiver
D S R #, C T S #,
C D #, R I#
RX
RHR
B au d R ate G e n erato r
R ESE T
RST
C rys ta l O s c/B u ffer
XT A L 1/C L K
XT A L 2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
FIGURE 2. ST16C1450 PINOUTS
N.C.
D3
D2
D1
N.C.
D0
N.C.
VCC
CD#
DSR#
N.C.
N.C.
48
47
46
45
44
43
42
41
40
39
38
37
48-TQFP PACKAGE
N.C.
1
36
N.C.
N.C.
2
35
N.C.
D4
3
34
CTS#
D5
4
33
RESET
D6
5
32
DTR#
D7
6
31
RTS#
RX
7
30
A0
ST16C1450CQ48
TX
8
29
N.C.
CS#
9
28
A1
N.C.
10
27
A2
N.C.
11
26
N.C.
N.C.
12
25
N.C.
NOTE: PINOUTS NOT TO SCALE.
ACTUAL SIZE OF TQFP PACKAGE
IS SMALLER THAN PLCC PACKAGE.
D0
VCC
CD#
1
28
27
6
24
RESET
D6
7
23
DTR#
D7
8
22
RTS#
RX
9
21
A0
TX
10
20
A1
CS# 11
19
A2
15
16
17
18
GND
IOR#
RI#
INT
14
ST16C1450CJ28
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING
TEMPERATURE
RANGE
DEVICE STATUS
ST16C1450CJ28
28-Lead PLCC
0°C to +70°C
Active
ST16C1450CQ48
48-Lead TQFP
0°C to +70°C
Active
ST16C1450IJ28
28-Lead PLCC
-40°C to +85°C
Active
ST16C1450IQ48
48-Lead TQFP
-40°C to +85°C
Active
2
26 DSR#
D1
2
D5
IOW#
24
N.C.
D2
CTS#
13
23
INT
3
25
XTAL2
22
RST
D3
5
12
21
RI#
4
D4
XTAL1
20
IOR#
17
IOW#
19
16
XTAL2
18
15
XTAL1
N.C.
14
N.C.
GND
13
N.C.
28-PLCC PACKAGES
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
PIN DESCRIPTIONS
NAME
28-PIN
PLCC
48-PIN
TQFP
TYPE
DESCRIPTION
DATA BUS INTERFACE
A0
A1
A2
21
20
19
30
28
27
I
Address data lines [2:0]. A2:A0 selects internal UART’s configuration registers.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
43
45
46
47
3
4
5
6
I/O
IOR#
16
20
I
Input/Output Read (active low). The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed by the address lines [A2:A0],
places it on the data bus to allow the host processor to read it on the leading edge.
IOW#
14
17
I
Input/Output Write (active low). The falling edge instigates the internal write cycle and
the rising edge transfers the data byte on the data bus to an internal register pointed by
the address lines [A2:A0].
CS#
11
9
I
Chip Select input (active low). A logic 0 on this pin selects the ST16C1450 device.
INT
18
23
O
Interrupt Output (three-state, active high). INT output defaults to three-state mode and
becomes active high when MCR bit-3 is set to a logic 1. INT output becomes a logic
high level when interrupts are enabled in the interrupt enable register (IER), and
whenever the transmitter, receiver, line and/or modem status register has an active
condition.
Data bus lines [7:0] (bidirectional).
MODEM OR SERIAL I/O INTERFACE
TX
10
8
O
Transmit Data. This output is associated with individual serial transmit channel data
from the 1450. The TX signal will be a logic 1 during reset, idle (no data), or when the
transmitter is disabled. During the local loopback mode, the TX output pin is disabled
and TX data is internally connected to the UART RX input.
RX
9
7
I
Receive Data. This input is associated with individual serial channel data to the 1450.
Normal received data input idles at logic 1 condition. This input must be connected to
its idle logic state, logic 1, else the receiver may report “receive break” and/or “error”
condition(s).
RTS#
22
31
O
Request to Send or general purpose output (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, leave it
unconnected.
CTS#
25
34
I
Clear to Send or general purpose input (active low). If this pin is not needed for modem
communication, then it can be used as a general I/O. If it is not used, connect it to
VCC.
DTR#
23
32
O
Data Terminal Ready or general purpose output (active low). If this pin is not needed
for modem communication, then it can be used as a general I/O. If it is not used, leave
it unconnected.
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
NAME
28-PIN
PLCC
48-PIN
TQFP
TYPE
DESCRIPTION
DSR#
26
39
I
Data Set Ready input or general purpose input (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, connect
it to VCC.
CD#
27
40
I
Carrier Detect input or general purpose input (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, connect
it to VCC.
RI#
17
21
I
Ring Indicator input or general purpose input (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, connect
it to VCC.
ANCILLARY SIGNALS
XTAL1
12
15
I
Crystal or external clock input. See Figure 3 for typical oscillator connections.
XTAL2
13
16
O
Crystal or buffered clock output. See Figure 3 for typical oscillator connections.
RESET
24
33
I
Reset Input (active high). When it is asserted, the UART configuration registers are
reset to default values, see Table 6.
RST
-
22
O
Reset Output (active high). This output is only available on the ST16C1451. When
IER bit-5 is a logic 0, RST will follow the logical state of the RESET pin. When IER bit5 is a logic 1, the user may send software (soft) resets via MCR bit-2. Soft resets from
MCR bit-2 are “ORed” with the state of the RESET pin.
VCC
28
41
Pwr Power supply input of 2.97 to 5.5V.
GND
15
19
Pwr Power supply common ground.
N.C.
-
1, 2,
10-14,
18,
24-26,
29,
35-38,
42, 44,
48
-
Not connected.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION
The ST16C1450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-toparallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required in digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The 1450 is capable of
operation up to 1.5 Mbps with a 24 MHz crystal or external clock input with a 16X sampling clock (at VCC =
5.0V). With a crystal of 14.7456 MHz and through a software option, the user can select data rates up to 921.6
Kbps.
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1
Internal Registers
The 1450 has a set of enhanced registers for controlling, monitoring and data loading and unloading. These
registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO
control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers
(MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpad
register (SPR). All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL
REGISTERS” on page 10.
2.2
Crystal Oscillator or External Clock
The 1450 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to
the Baud Rate Generators (BRG) in the UART. XTAL1 is the input to the oscillator or external clock buffer input
with XTAL2 pin being the output. For programming details, see “Section 2.3, Programmable Baud Rate
Generator” on page 5.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 3). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typical oscillator connections are shown in Figure 3. For further reading on oscillator circuit please see
application note DAN108 on EXAR’s web site.
FIGURE 3. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R2
500K - 1M
Y1
2.3
C1
C2
22-47pF
22-47pF
R1
0-120
(Optional)
1.8432 MHz
to
24 MHz
Programmable Baud Rate Generator
The UART has its own Baud Rate Generator (BRG). The BRG divides the input crystal or external clock by a
programmable divisor between 1 and (216 -1) to obtain a 16X sampling clock of the serial data rate. The
sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor
(DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG must be
programmed during initialization to the operating data rate. Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the operating data rate. Table 1 shows the standard data
rates available with a 14.7456 MHz crystal or external clock at 16X clock rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
TABLE 1: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00
0
2400
384
180
01
80
0
4800
192
C0
00
C0
0
9600
96
60
00
60
0
19.2k
48
30
00
30
0
38.4k
24
18
00
18
0
76.8k
12
0C
00
0C
0
153.6k
6
06
00
06
0
230.4k
4
04
00
04
0
460.8k
2
02
00
02
0
921.6k
1
01
00
01
0
2.4
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and an 8-bit Transmit Holding
Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods. The
transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and
adds the stop-bit(s). The status of the THR and TSR are reported in the Line Status Register (LSR bit-5 and bit6).
2.4.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out.
2.4.2
Transmitter Operation
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. The THR flag can generate a transmit empty interrupt (ISR bit-1) when it is
enabled by IER bit-1. The TSR flag (LSR bit-6) is set when both the THR and TSR become completely empty.
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
FIGURE 4. TRANSMITTER OPERATION
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
Transmit Shift Register (TSR)
M
S
B
L
S
B
TXNOFIFO1
2.5
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and an 8-bit Receive Holding Register
(RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in
the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this
time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled
and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the
LSR register bits 2-4. Upon unloading the receive data byte from RHR, the error tags are immediately updated
to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon
receiving a character. The RHR interrupt is enabled by IER bit-0.
2.5.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. When there is data in the RHR register,
the 3 error tags in LSR register (bits 2-4) indicates if there are any errors associated with that byte.
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
FIGURE 5. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
Data Bit
Validation
Receive Data Characters
RHR Interrupt (ISR bit-2)
RXFIFO1
2.6
Special (Enhanced Feature) Mode
The 1450 supports the standard features of the ST16C450. In addition, the 1450 supports some enhanced
features not available for the ST16C450. These features are enabled by IER bit-5 and include a software
controllable (SOFT) reset, power down feature and FIFO monitoring bits.
2.6.1
Soft Reset
Soft resets are useful when the user desires the capability of resetting an externally connected device only.
MCR bit-2 can be used to initiate a SOFT reset at the RST output pin. This does not reset the 1450 (only the
RESET input pin can reset the 1450). Soft resets from MCR bit-2 are “ORed” with the RESET input pin.
Therefore both reset types will be seen at the RST output pin.
2.6.2
Power Down Mode
The power down feature (controlled by MCR bit-7) provides the user with the capability to conserve power
when the package is not in actual use without destroying internal register configuration data. This allows quick
turnarounds from power down to normal operation. For complete details, see the MCR bit-7 description on
page 16.
2.7
Internal Loopback
The 1450 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 6 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
FIGURE 6. INTERNAL LOOPBACK
VCC
TX
Transmit Shift Register
Receive Shift Register
RX
VCC
RTS#
RTS#
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
MCR bit-4=1
CTS#
CTS#
VCC
DTR#
DTR#
DSR#
DSR#
OP1#
RI#
RI#
OP2#
CD#
CD#
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
3.0 UART INTERNAL REGISTERS
The 1450 has a set of configuration registers selected by address lines A0, A1 and A2. The 16C450
compatible registers can be accessed when LCR[7] = 0 and the baud rate generator divisor registers can be
accessed when LCR[7] = 1. The complete register set is shown on Table 2 and Table 3.
TABLE 2: ST16C1450 UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
LCR[7] = 0
0
0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
0
0 0
DLL - Div Latch Low Byte
Read/Write
0
0 1
DLM - Div Latch High Byte
Read/Write
0
0 1
IER - Interrupt Enable Register
Read/Write
0
1 0
ISR - Interrupt Status Register
Reserved
Read-only
Write-only
0
1 1
LCR - Line Control Register
Read/Write
1
0 0
MCR - Modem Control Register
Read/Write
1
0 1
LSR - Line Status Register
Reserved
Read-only
Write-only
1
1 0
MSR - Modem Status Register
Reserved
Read-only
Write-only
1
1 1
SPR - Scratch Pad Register
Read/Write
10
LCR[7] = 1
LCR[7] = 0
LCR[7] = 0
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
.
TABLE 3: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
000
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
000
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
IER
RD/WR
0
0
Special
Mode
Enable
0
Modem
Status
Int.
Enable
RX Line
TX
RX
Status Empty
Data
Int.
Int.
Int.
Enable Enable Enable
INT
INT
INT
Source Source Source
Bit-2
Bit-1
Bit-0
(Enable
MCR bits
7, 2)
010
ISR
RD
0
0
0
0
INT
Source
Bit-3
011
LCR
RD/WR
Divisor
Enable
Set TX
Break
Set
Parity
Even
Parity
Parity
Enable
100
MCR
RD/WR
0/
0
0
Internal
Loopback
Enable
(OP2#)/
INT
Output
Enable
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Framing
Error
RX
Parity
Error
RX
Overrun
Error
RX
Data
Ready
Power
Down
Mode
101
LSR
RD
0
Stop
Bits
LCR[7] = 0
Word
Word
Length Length
Bit-1
Bit-0
(OP1#)/ RTS# DTR#
Output Output
SOFT Control Control
Reset
110
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
111
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 0
Baud Rate Generator Divisor
000
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
11
LCR[7] = 1
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 7.
4.2
Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 6.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR is empty. If the THR is empty
when this bit is enabled, an interrupt will be generated. Note that this interrupt does not behave in the same
manner as the industry standard 16C550. SEE”INTERRUPT CLEARING:” ON PAGE 13.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in the RHR.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved
IER[5]: Special Mode Enable
• Logic 0 = Disable special mode functions (default).
• Logic 1 = Enable special mode functions in addition to basic ST16C1450 functions. Enables ISR bits 4-5
(TXRDY/RXRDY), MCR bit-2 (soft reset) and MCR bit-7 (power down) functions.
IER[7:6]: Reserved
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 4, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
12
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
4.4.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by received data in RHR.
• TXRDY is by THR empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptied or cleared from RHR).
• RXRDY interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register AND disabling the TXRDY interrupt (set IER bit-1 =
0), or by loading data into the TX FIFO.
• MSR interrupt is cleared by a read to the MSR register.
]
TABLE 4: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
1
0
LSR (Receiver Line Status Register)
2
0
1
0
0
RXRDY (Received Data Ready)
3
0
0
1
0
TXRDY (Transmit Ready)
4
0
0
0
0
MSR (Modem Status Register)
-
0
0
0
1
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 4).
ISR[7:4]: Reserved
4.5
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
13
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2
WORD LENGTH
STOP BIT LENGTH (BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 5 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR bit-5 selects the forced parity format.
• LCR[5] = logic 0, parity is not forced (default).
• LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
• LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 5: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark, “1”
1
1
1
Forced parity to space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
14
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.6
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: OP1# Output/Soft Reset
OP1# is not available as an output pin on the 1450. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
• Logic 0 = OP1# output (RI# input) is at logic 1 (default).
• Logic 1 = OP1# output (RI# input) is at logic 0.
In normal operation, this bit is associated with the RST (buffered reset) output pin. The logical state of the RST
pin will follow exactly the logical state of the RESET pin. When IER bit-5 = 1, soft resets from MCR bit-2 are
ORed with the state of the RESET input pin. Therefore both reset types will be seen at the RST pin. Note that
asserting MCR bit-2 does not reset the 1450.
• Logic 0 = The RST output pin is a logic 0 (default).
• Logic 1 = The RST output pin is a logic 1.
MCR[3]: OP2# or INT Output Enable
When not in Internal Loopback Mode:
• Logic 0 = INT output is three-state (default).
• Logic 1 = INT output is active high.
OP2# is not available as an output pin on the 1450. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem CD# interface signal.
• Logic 0 = OP2# output (CD# input) is a logic 1 (default).
• Logic 1 = OP2# output (CD# input) is a logic 0.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 6.
MCR[6:5]: Reserved
15
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
MCR[7]: Power Down Enable
This bit can only be accessed when IER bit-5 = 1.
• Logic 0 = Normal mode (default).
• Logic 1 = Power down mode. SEE”POWER DOWN MODE” ON PAGE 8.
4.7
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic
1, an LSR interrupt will be generated when the character that is in the RHR has an error (parity, framing,
overrun, break).
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register (default).
• Logic 1 = Data has been received and is saved in the receive holding register.
LSR[1]: Receiver Overrun Error Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift
register is overwritten. Note that under this condition the data byte in the receive shift register is not
transferred into the RHR, therefore the data in the RHR is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The received character in RHR does not have correct parity information and is
suspect. This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The received character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Error Tag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time).
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the data byte is
transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently
with the data loading to the transmit holding register by the host.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character.
LSR[7]: Reserved
4.8
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
16
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# (active high, logical 1). Normally this bit is the compliment of the CTS# input. In the loopback mode, this
bit is equivalent to bit-1 in the MCR register. The CTS# input may be used as a general purpose input when the
modem interface is not used.
MSR[5]: DSR Input Status
DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this
bit is equivalent to bit-0 in the MCR register. The DSR# input may be used as a general purpose input when the
modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is
equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the
modem interface is not used.
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the
modem interface is not used.
4.9
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
17
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
TABLE 6: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
I/O SIGNALS
RESET STATE
TX
Logic 1
RTS#
Logic 1
DTR#
Logic 1
RST
Logic 1
INT
Three-State Condition
18
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
7 Volts
Voltage at Any Pin
GND-0.3 V to 7 V
Operating Temperature
-40o to +85oC
Storage Temperature
-65o to +150oC
Package Dissipation
500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (48-TQFP)
theta-ja = 59oC/W, theta-jc = 16oC/W
Thermal Resistance (28-PLCC)
theta-ja = 55oC/W, theta-jc = 28oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V
TO 5.5V
SYMBOL
LIMITS
3.3V
MIN
MAX
PARAMETER
LIMITS
5.0V
MIN
MAX
UNITS
CONDITIONS
VILCK
Clock Input Low Level
-0.3
0.6
-0.5
0.6
V
VIHCK
Clock Input High Level
2.4
VCC
3.0
VCC
V
VIL
Input Low Voltage
-0.3
0.8
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC
2.2
VCC
V
VOL
Output Low Voltage
0.4
V
IOL = 6 mA
VOL
Output Low Voltage
V
IOL = 4 mA
VOH
Output High Voltage
V
IOH = -6 mA
VOH
Output High Voltage
V
IOH = -1 mA
0.4
2.4
2.0
IIL
Input Low Leakage Current
±10
±10
uA
IIH
Input High Leakage Current
±10
±10
uA
CIN
Input Pin Capacitance
5
5
pF
ICC
Power Supply Current
1.3
3
mA
IPWRDN
Power Down Current
50
200
uA
See Test 1
Test 1: The following inputs should remain steady at VCC or GND state to minimize Power Down current: A0-A2, D0-D7,
IOR#, IOW#, CS# and modem inputs. Also, RX input must idle at logic 1 state while in Power Down mode.
19
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V
SYMBOL
LIMITS
3.3V
PARAMETER
MIN
LIMITS
5.0V
MAX
63
MIN
UNIT
CLK
Clock Pulse Duration
21
OSC
Oscillator/External Clock Frequency
TAS
Address Setup Time
5
0
ns
TAH
Address Hold Time
10
5
ns
TCS
Chip Select Width
50
40
ns
TRD
IOR# Strobe Width
35
25
ns
TDY
Read/Write Cycle Delay
40
30
ns
TRDV
Data Access Time
TDD
Data Disable Time
0
TWR
IOW# Strobe Width
40
25
ns
TDS
Data Setup Time
20
15
ns
TDH
Data Hold Time
5
5
ns
8
25
ns
24
35
0
CONDITIONS
MAX
MHz
25
ns
15
ns
TWDO
Delay From IOW# To Output
50
40
ns
100 pF load
TMOD
Delay To Set Interrupt From MODEM Input
40
35
ns
100 pF load
TRSI
Delay To Reset Interrupt From IOR#
40
35
ns
100 pF load
TSSI
Delay From Stop To Set Interrupt
1
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
45
40
ns
TSI
Delay From Stop To Interrupt
45
40
ns
TINT
Delay From Initial INT Reset To Transmit Start
8
24
Bclk
TRST
Reset Pulse Width
40
N
Baud Rate Divisor
1
Bclk
Baud Clock
24
8
40
216-1
1
16X of data rate
20
ns
216-1
Hz
100 pF load
xr
ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
FIGURE 7. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
FIGURE 8. MODEM INPUT/OUTPUT TIMING
IOW#
IOW
Active
T WDO
RTS#
DTR#
Change of state
Change of state
CD#
CTS#
DSR#
Change of state
Change of state
T MOD
T MOD
INT
Active
Active
Active
T RSI
IOR#
IOR
Active
Active
Active
T MOD
Change of state
RI#
21
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
FIGURE 9. DATA BUS READ TIMING
A0A2
Valid
Address
Valid
Address
TAS
TAS
TAH
CS2#
TAH
TCS
TCS
TDY
IOR#
TRD
TRD
TDD
TRDV
TDD
TRDV
Valid
Data
D0-D7
Valid
Data
FIGURE 10. DATA BUS WRITE TIMING
A0A2
Valid
Address
Valid
Address
TAS
CS2#
TAS
TAH
TAH
TCS
TCS
TDY
IOW#
TWR
TWR
TDS
D0-D7
TDH
Valid
Data
TDS
Valid
Data
22
TDH
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
FIGURE 11. RECEIVE READY & INTERRUPT TIMING
RX
Start
Bit
Stop
Bit
D0:D7
INT
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
in RHR
1 Byte
in RHR
1 Byte
in RHR
TSSR
TSSR
Active
Data
Ready
Active
Data
Ready
RXRDY
(ISR bit-5)
TRR
TSSR
Active
Data
Ready
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 12. TRANSMIT READY & INTERRUPT TIMING
TX
(Unloading)
Start
Bit
IER[1]
enabled
D0:D7
Stop
Bit
INT cleared*
D0:D7
IER[1]
enabled
INT cleared*
D0:D7
IER[1]
enabled
INT cleared*
INT*
TSRT
TSRT
TSRT
TXRDY
(ISR bit-4)
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read and IER[1] is disabled.
23
TXNonFIFO
xr
ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D
D1
36
25
37
24
D1
48
13
1
2
1
B
e
A2
C
A
Seating
Plane
α
A1
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.039
0.047
1.00
1.20
A1
0.002
0.006
0.05
0.15
A2
0.037
0.041
0.95
1.05
B
0.007
0.011
0.17
0.27
C
0.004
0.008
0.09
0.20
D
0.346
0.362
8.80
9.20
D1
0.272
0.280
6.90
7.10
e
0.020 BSC
0.50 BSC
L
0.018
0.030
0.45
0.75
α
0°
7°
0°
7°
24
D
xr
ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
PACKAGE DIMENSIONS (28 PIN PLCC)
Note: The control dimension is the inch column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.165
0.180
4.19
4.57
A1
0.090
0.120
2.29
3.05
A2
0.020
-
0.51
-
B
0.013
0.021
0.33
0.53
B1
0.026
0.032
0.66
0.81
C
0.008
0.013
0.19
0.32
D
0.485
0.495
12.32
12.57
D1
0.450
0.456
11.43
11.58
D2
0.390
0.430
9.91
10.92
D3
0.300 typ.
7.62 typ.
e
0.050 BSC
1.27 BSC
H1
0.042
0.056
1.07
1.42
H2
0.042
0.048
1.07
1.22
R
0.025
0.045
0.64
1.14
25
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ST16C1450
2.97V TO 5.5V UART
REV. 4.2.1
REVISION HISTORY
DATE
REVISION
DESCRIPTION
January 2003
Rev 4.0.0
Changed to single column format. Clarified that the TX interrupt is not MS Windows
compatible. Clarified timing diagrams. Renamed Rclk (Receive Clock) to Bclk
(Baud Clock) and timing symbols. Added TAH, TCS and OSC.
April 2003
Rev 4.0.1
Updated Ordering Information.
September 2003
Rev 4.1.0
Added Status Column to Ordering Information.
October 2003
Rev 4.2.0
Clarified compatibility to industry standard 16450 and MS Windows standard serial
port driver in General Description. Removed Auto RTS flow control from MCR bit-1
description since that feature is not available in this device.
August 2005
Rev 4.2.1
Removed discontinued ST16C1451 and discontinued packages of ST16C1450 from
Ordering Information.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet August 2005.
Send your UART technical inquiry with technical details to hotline: [email protected].
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
26
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ST16C1450/51
2.97V TO 5.5VUART
REV. 4.2.1
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
FEATURES ..................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. ST16C1450 PINOUTS ..................................................................................................................................................... 2
ORDERING INFORMATION ................................................................................................................................ 2
PIN DESCRIPTIONS ......................................................................................................... 3
DATA BUS INTERFACE ............................................................................................................................................. 3
MODEM OR SERIAL I/O INTERFACE ....................................................................................................................... 3
1.0 PRODUCT DESCRIPTION .................................................................................................................... 4
ANCILLARY SIGNALS ................................................................................................................................................ 4
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 5
2.1 INTERNAL REGISTERS ................................................................................................................................... 5
2.2 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK ......................................................................................... 5
FIGURE 3. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 5
2.3 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 5
TABLE 1: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ........................................................................ 6
2.4 TRANSMITTER ................................................................................................................................................. 6
2.4.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 6
2.4.2 TRANSMITTER OPERATION....................................................................................................................................... 6
FIGURE 4. TRANSMITTER OPERATION ............................................................................................................................................... 7
2.5 RECEIVER ........................................................................................................................................................ 7
2.5.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 7
FIGURE 5. RECEIVER OPERATION IN NON-FIFO MODE ...................................................................................................................... 8
2.6 SPECIAL (ENHANCED FEATURE) MODE ..................................................................................................... 8
2.6.1 SOFT RESET ................................................................................................................................................................ 8
2.6.2 POWER DOWN MODE ................................................................................................................................................. 8
2.7
INTERNAL LOOPBACK .................................................................................................................................. 8
FIGURE 6. INTERNAL LOOPBACK ....................................................................................................................................................... 9
3.0 UART INTERNAL REGISTERS ........................................................................................................... 10
TABLE 2: ST16C1450 UART INTERNAL REGISTERS................................................................................................................ 10
TABLE 3: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 11
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 12
4.1
4.2
4.3
4.4
RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ...............................................................................
TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................
INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................
INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ...............................................................................
12
12
12
12
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 13
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 13
TABLE 4: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 13
4.5 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 13
TABLE 5: PARITY SELECTION .......................................................................................................................................................... 14
4.6
4.7
4.8
4.9
MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE
LINE STATUS REGISTER (LSR) - READ ONLY ...........................................................................................
MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................
SCRATCH PAD REGISTER (SPR) - READ/WRITE ......................................................................................
15
16
16
17
TABLE 6: UART RESET CONDITIONS........................................................................................................................................ 18
ABSOLUTE MAXIMUM RATINGS .................................................................................. 19
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) ................................................. 19
ELECTRICAL CHARACTERISTICS................................................................................ 19
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 19
AC ELECTRICAL CHARACTERISTICS .............................................................................................................. 20
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V...................... 20
FIGURE 7. CLOCK TIMING............................................................................................................................................................... 21
FIGURE 8. MODEM INPUT/OUTPUT TIMING ...................................................................................................................................... 21
FIGURE 9. DATA BUS READ TIMING ................................................................................................................................................ 22
FIGURE 10. DATA BUS WRITE TIMING ............................................................................................................................................ 22
FIGURE 11. RECEIVE READY & INTERRUPT TIMING ......................................................................................................................... 23
I
xr
ST16C1450/51
2.97V TO 5.5VUART
REV. 4.2.1
FIGURE 12. TRANSMIT READY & INTERRUPT TIMING ....................................................................................................................... 23
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM) ....................................................................................24
PACKAGE DIMENSIONS (28 PIN PLCC) .........................................................................................................25
REVISION HISTORY.......................................................................................................................................26
TABLE OF CONTENTS ............................................................................................................I
II