XRD64L42 Dual 10-Bit 40MSPS CMOS ADC January 2001-1 APPLICATIONS FEATURES • 10-Bit Resolution • Medical Ultrasound Imaging • Two Monolithic Complete 10-Bit ADCs • I & Q Modems • • • • • • • • • • • 40 MSPS Conversion Rate BENEFITS On-Chip Track-and-Hold • • • • On-Chip Voltage Reference Low 5 pF Input Capacitance TTL/CMOS Outputs Tri-State Output Buffers Reduction of Components Reduction of System Cost High Performance @ Low Power Dissipation Long Term Time and Temperature Stability Single +3.0V Power Supply Operation Low Power Dissipation: 200mW-typ @ 2.7V Power Down Mode Less Than 5mW 75dB Crosstalk (fin=1.0MHz) -40°C to +85°C Operation Temperature Range GENERAL DESCRIPTION The XRD64L42 is two 10-bit, monolithic, 40 MSPS ADCs. Manufactured using a standard CMOS process, the XRD64L42 offers low power, low cost and excellent performance. The on-chip track-and-hold amplifier(T/H) and voltage reference (VREF) eliminate the need for external active components, requiring only an external ADC conversion clock for the application. The XRD64L42 analog input can be driven with ease due to the high input impedance. user after the initial 3.4ms calibration (168,000 initial clock cycles). The design architecture uses 17 time- interleaved 10bit SAR ADCs in each converter to achieve high conversion rate of 40 MSPS minimum. In order to insure and maintain accurate 10-bit operation with respect to time and temperature, XRD64L42 incorporates an auto-calibration circuit which continuously adjusts and matches the offset and linearity of each ADC. This auto-calibration circuit is transparent to the The XRD64L42 internal reference provides cost savings and simplifies the design/development. The output voltage of the internal reference is set by two external resistors. The internal reference can be disabled if an external reference is used for a power savings of 50mW. The power dissipation is only 200mW at 40 MSPS with +2.7V power supply. The digital output data is straight binary format, and the tri-state disable function is provided for common bus interface. ORDERING INFORMATION Part Number Package Type Temperature Range XRD64L42AIV 64-Lead TQFP -40°C to +85°C Rev. P2.10 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 XRD64L42 VINA+VINA- 10 Bit A/D's Bandgap ADC A A/D 1a VBG + VFBK - 11 DA9 - DA0, OTRA VRHF TRI_A A/D 17a K DIFF SYNCO PD CKIN CONTROL LOGIC 10 Bit A/D's ADC B A/D 1b VRLF 11 VCMO + A/D 17b VINB+VINB- Figure 1. XRD64L42 Simplified Block Diagram Rev. P2.10 2 DB9 - DB0, OTRB TRI_B AGND AGND AVDD AVDD AGND VINA- VINA+ AGND VINB+ VINB- AGND AGND AVDD AGND DGND VCMO Rev. P2.10 TRI_A CKIN SYNCO DB0 DB1 DB2 DOGND DOVDD DGND DB3 DB4 DB5 DB6 DB7 DB8 DB9 XRD64L42 33 32 34 16 31 35 15 30 36 14 29 37 13 28 38 12 27 39 11 26 40 10 25 41 9 24 42 8 23 43 7 22 44 6 XRD64L42 64QFP 5 21 45 4 20 46 3 19 47 2 18 48 1 3 17 OTRB AGND 49 DA0 DIFF 50 DA1 TRI_B 51 DA2 DVDD 52 DA3 PD 53 DA4 DGND 54 DOVDD DGND 55 DOGND AGND 56 DVDD AGND 57 DGND AGND 58 DA5 VRLF 59 DA6 VRLF 60 DA7 VRHF 61 DA8 VRHF 62 DA9 VFBK 63 OTRA VBG 64 XRD64L42 PIN DESCRIPTION Pin # 1 2 Symbol VBG Description Bandgap Voltage Output VFBK Analog Reference Feedback 3 VRHF Top Voltage Reference Force 4 VRHF Top Voltage Reference Force 5 VRLF Bottom Voltage Reference Force 6 VRLF Bottom Voltage Reference Force 7 AGND Analog Ground 8 AGND Analog Ground 9 AGND Analog Ground 10 DGND Digital Ground 11 DGND 12 PD 13 DVDD 14 TRI_B 15 DIFF 16 AGND Analog Ground 17 TRI_A Tri-state for the A Channel Outputs, Active High 18 19 SYNCO Data Valid Output (Rising Edge) 20 DB0 Digital Output Bit 0 (LSB) ADC B 21 DB1 Digital Output Bit 1 ADC B 22 DB2 Digital Output Bit 2 ADC B 23 DOGND 24 DOVDD 25 DGND 26 DB3 Digital Output Bit 3 ADC B 27 DB4 Digital Output Bit 4 ADC B 28 DB5 Digital Output Bit 5 ADC B 29 DB6 Digital Output Bit 6 ADC B 30 DB7 Digital Output Bit 7 ADC B CKIN Digital Ground Power Down, Active High Digital Supply Voltage Tri-state for the B Channel Outputs, Active High Hi=Differential Mode, Lo=Single-Ended Mode Clock Input Digital Output Ground Digital Output Supply Voltage Digital Ground 31 DB8 Digital Output Bit 8 ADC B 32 DB9 Digital Output Bit 9 (MSB) ADC B 33 OTRB 34 DA0 Digital Output Bit 0 (LSB) ADC A 35 DA1 Digital Output Bit 1 ADC A 36 DA2 Digital Output Bit 2 ADC A 37 DA3 Digital Output Bit 3 ADC A 38 DA4 Digital Output Bit 4 ADC A Over Range Digital Output Bit ADC B 39 DOVDD Digital Output Supply Voltage 40 DOGND Digital Output Ground 41 DVDD Digital Supply Voltage Rev. P2.10 4 XRD64L42 PIN DESCRIPTION (CONT'D) Pin # 42 Symbol DGND 43 DA5 Digital Output Bit 5 ADC A 44 DA6 Digital Output Bit 6 ADC A 45 DA7 Digital Output Bit 7 ADC A 46 DA8 Digital Output Bit 8 ADC A 47 DA9 Digital Output Bit 9 ADC A 48 OTRA 49 VCMO Differential Common Mode Voltage Output 50 DGND Digital Ground 51 AGND Analog Ground 52 AVDD Analog Supply Voltage 53 AGND Analog Ground 54 AGND Analog Ground Description Digital Ground Over Range Digital Output Bit ADC A 55 VINB- Analog Input B(-) 56 VINB+ Analog Input B(+) 57 AGND Analog Ground 58 VINA+ Analog Input A(+) 59 VINA- Analog Input A(-) 60 AGND Analog Ground 61 AVDD Analog Supply Voltage 62 AVDD Analog Supply Voltage 63 AGND Analog Ground 64 AGND Analog Ground Rev. P2.10 5 XRD64L42 ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty Cycle, Differential Input Mode Symbol Parameter Min. Typ. Max. Unit -0.75 +/-0.25 .75 LSB Conditions DC ACCURACY DNL Differential Non-Linearity INL Integral Non-Linearity +/-0.5 LSB MON Monotonicity No Missing Codes Guaranteed by Test FSE Full Scale Error +10 mV F.S. = (VRHF - VRLF)x0.97 ZSE Zero Scale Error 5 mV Single Ended Mode 1 ANALOG INPUT INVR Input Voltage Range 1 VRHFx0.97 V INRES Input Resistance 20 KOhms INCAP Input Capacitance 5 pF INBW Input Bandwidth 400 MHz VRLF Grounded -1dB Small Signal REFERENCE INPUT, INTERNAL BANDGAP REFERENCE AND REFERENCE BUFFER RLAD RLADTCO Ladder Resistance Ladder Resistance Tempco Bandgap Output Voltage VBG 100 125 150 +0.8 1.15 1.25 Ohms Ohms/°C 1.35 V Range VBGTC Bandgap Reference 30 ppm/°C Tempco VRLF 0.0 VRHF VRLF+ 0.0 2.0 V AVdd-0.3 V Internal Reference Buffer AVdd V External 1.0 VRHF External Reference VRLF+ 2.5 1.0 VRHF PSRR Internal Reference Buffer 6 mV/V VCMO, Common Mode Voltage VCMO Common Mode Voltage 1.15 1.25 Isource Current Source 200 500 1.35 V uA Notes: 1 There is a series resistor (approximately 3 to 4 ohms) between VRHF and the ladder resistance. The voltage drop associated with this series resistance accounts for the 0.97 multiplication factor. Rev. P2.10 6 XRD64L42 ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40MSPS, 50% Duty Cycle, Differential Input Mode Symbol Parameter Min. Typ. Max. Unit Conditions DYNAMIC PERFORMANCE Fs = 40MHz SNR Signal-to-Noise Ratio SINAD Not Including Harmonics fin = 1.0 MHz 58 60 dB fin = 4.0 MHz 57 60 dB fin = 10.0 MHz 57 59 dB Signal-to Noise and Distortion Including Harmonics fin = 1.0 MHz 58 60 dB fin = 4.0 MHz 57 59 dB fin = 10 MHz 56 58 dB fin = 1.0 MHz 9.3 9.7 Bit fin = 4.0 MHz 9.2 9.5 Bit fin = 10 MHz 9.0 9.2 Bit ENOB EFFECTIVE NUMBER OF BITS SFDR SPURIOUS FREE DYNAMIC RANGE SFDR fin = 1.0 MHz 70 dB Crosstalk fin = 1.0 MHz 75 dB IMD fin1 = 2.5 MHz 70 dB Intermodulation Distortion fin2 = 3.5 MHz CONVERSION AND TIMING CHARACTERISTICS (CL = 10pF) MAXCON MINCON Lat Maximum Conversion 40 50 MSPS Minimum Conversion 100 KSPS Latency 17 cycles Aperture Jitter Time 12 ps Guaranteed by Design APJT tr Digital Output Rise Time 3 ns tf Digital Output Fall Time 3 ns Output Data Propagation 6 25 ns 6 20 ns Guaranteed by Design 5 20 ns Guaranteed by Design 50 60 % Guaranteed by Design tpd Peak-to Peak Delay tden Output Data Enable Delay tdis Output Data Disable Delay CLKDC Clock Duty Cycle 40 Rev. P2.10 7 XRD64L42 ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty Cycle, Differential Input Mode Symbol Parameter Min. Typ. Max. Unit 0.5 V Conditions DIGITAL INPUTS DVINH Digital Input High Voltage DVINL Digital Input Low Voltage DIINH Digital Input High Leakage 2.5 V CKIN Clock Input -1.0 0.05 1.0 mA DIFF Differential/Single-Ended -1.0 -0.25 1.0 uA Internal pull-up resistor A/B Channel Tri-State -125.0 -90.0 -50.0 uA Internal pull-down resistor Power Down -125.0 -90.0 -50.0 uA Internal pull-down resistor Input TRI_A/TRI_B PD DIINL Digital Input Low Leakage CKIN Clock Input -5.0 0.05 5.0 nA DIFF Differential/Single-Ended 50.0 90.0 125.0 uA Internal pull-up resistor A/B Channel Tri-State -1.0 0.25 1.0 uA Internal pull-down resistor Power Down -1.0 0.25 1.0 uA Internal pull-down resistor 5 8 pF Input TRI_A/TRI_B PD DINC Digital Input capacitance DIGITAL OUTPUTS (CL = 10 pF) DOHV Digital Output High DVdd DVdd- Voltage -0.4V 0.3V DOLV Digital Output Low V IOH = 1.5 mA IOL = 1.5 mA 0.3 0.4 V 0.2 100 nA Voltage IOZ High-Z Leakage -100 Rev. P2.10 8 XRD64L42 ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.0V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 40 MSPS, 50% Duty Cycle, Differential Input Mode Symbol Parameter Min. Typ. Max. Unit 2.7 3.0 3.3 V 2.7 AVDD 3.3 V Conditions POWER SUPPLIES Analog Power Supply AVDD Voltage Digital Power Supply DVDD DVDD = AVDD Range Fs = 40 MHz, AVDD = DVDD = 2.7V, CL = 10pF, Fin = 10MHz (Includes Iref Current) AIDD Analog Supply Current 55 mA DIDD Digital Supply Current 13 mA DOIDD Output Driver Current 6 mA PDISS Power Dissipation 200 mW Fs = 40 MHz, AVDD = DVDD = 3.3V, CL = 10pF, Fin = 10MHz (Includes Iref Current) AIDD Analog Supply Current 37 70 mA DIDD Digital Supply Current 15 20 mA DOIDD Output Driver Current 15 20 mA 225 365 mW 100 300 mA PDISS Power Dissipation POWER DOWN CURRENT IPD Power Down Current ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND ○ ○ ○ ○ ○ VRT & VRB VIN All Inputs All Outputs Storage Temperature ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ +7.0V Lead Temperature (Soldering 10 seconds) 300°C Maximum Junction Temperature 150°C Package Power Dissipation Ratings (TA= +70°C) TQFP GJA = 89.4°C/W ○ VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V -65°C to 150°C ○ ○ ○ ○ ○ ○ ESD ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 2000V min ○ ○ ○ Notes: 1 2 3 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. VDD refers to AVDD and DVDD. GND refers to AGND and DGND Rev. P2.10 9 XRD64L42 APPLICATION SECTION Bandgap XRD64L42 VBG Voltage References The top ladder voltage for the XRD64L42 can be provided from an internal bandgap reference. The bandgap reference and its feedback path, Pins 1 and 2 respectively, can be used to set the voltage for VRHF. Select Rf and Ri (if gain is necessary) so that VRHF=VBG(1+Rf/Ri). The internal bandgap voltage is 1.24 volts. The XRD64L42 has a low impedence ladder, therefore, the typical value for Rf and Ri is 10K (Rf and Ri are recommended to be greater than 5K).See Figure 1. for a simplified diagram. AVdd VFBK Direct Input VRHF Resistive Ladder Direct Input VRLF Figure 3. Voltage Reference Provided by an External Source as Direct Inputs Bandgap XRD64L42 Single-Ended Inputs The XRD64L42 can be used in either single-ended or differential input mode. For differential inputs, see the Differential Inputs Section. Single-ended inputs minimize the amount of external components necessary to interface with the XRD64L42. The common inputs, VINA(-) and VINB(-) should be tied to ground. VINA(+) and VINB(+) can be used to apply direct inputs to the XRD64L42. Figure 3. is a simplied diagram for singleended inputs. Pin 15, DIFF should be held low to select single-ended inputs. VBG VFBK Ri Rf VRHF Resistive Ladder VRLF Figure 2. Voltage Reference Generated from the Internal Bandgap Voltage Input A VINA(+) VINA(-) 50 External voltage references can be forced at VRHF and VRLF. If VRHF and VRLF are driven externally, VFBK should be connected to AVdd, which tri-states the bandgap reference. Direct inputs or inputs driven by external amplifiers can be used to drive the ladder reference voltages of the XRD64L42. See Figure 2. for a simplified diagram. VINB(+) VINB(-) Input B 50 Figure 4. Single-Ended Inputs for the XRD64L42 Rev. P2.10 10 XRD64L42 Differential Inputs The XRD64L42 can be used in either differential or single-ended input mode. For single-ended inputs, see the Single-Ended Inputs Section. Differential inputs reduce system noise by removing noise components common at both input pins. Figure 4. is a simplified diagram that is used as a common test circuit with our XRD64L42/64L44EVAL application board. This circuit is used to evaluate the dynamic performance of the XRD64L42 using differential inputs. Pin 15, DIFF should be held high to select differential inputs. Note: To avoid auto-calibration after power down, do not disable CKIN. CKIN can be slowed down significantly to save power without losing calibration. 22 Transformer Input A Auto-Calibration The XRD64L42 incorporates an auto-calibration circuit which continuously adjusts and matches the offset and linearity of each ADC. This auto-calibration circuit is transparent to the user after the initial 3.4ms calibration (168,000 initial clock cycles). VINA(+) VCMO VINA(-) 22 50 22 Transformer Input B VINB(+) VINB(-) 22 50 Figure 5. Common Test Circuit for the Differential Input Mode SYNCO, Data Valid Delay and Latency SYNCO is an output pin provided by the XRD64L42. Valid data is available on the rising edge of SYNCO, see Figure 6. The Latency for the XRD64L42 is 17 clock cycles. CKIN N N+1 Valid Data N-17 N+2 N-16 N-15 tden=20ns SYNCO tsynco=2ns (typical) Figure 6. SYNCO, Data Valid Delay and Latency for the XRD64L42 Rev. P2.10 11 D A [ 9: 0] , O TR A 0. 1 uF 10 K 10 K 1 2 3 4 2u F 5 6 VIN A 6 0 1 22 AGN D 58 59 2 49 4 3 22 56 55 Tra ns f orm e r D A0 D A1 D A2 D A3 D A4 D A5 D A6 D A7 D A8 D A9 O TR A VBG VF BK VR H F VR H F V R LF V R LF VIN A+ VIN AV C MO VIN B+ VIN B- 50 10 pF AGN D 10 pF 0. 1 uF VIN B XRD64L42 +3 . 0V 6 1 22 AGN D 0 52 61 62 2 4 3 22 Tra ns f orm e r 13 41 50 12 10 pF AGN D AGN D 10 11 25 42 50 +3 . 0V Note: bypass capacitors for pins 13, 24, 39, 41, 52, 61, 62 23 40 0. 1 uF 0. 1 uF D VD D D VD D 10 pF 24 39 0. 1 uF AVD D AVD D AVD D 0. 1 uF 0. 1 uF 0. 1 uF 0. 1 uF AGN D D OVD D D OVD D D GN D D GN D D GN D D GN D D GN D D OGN D D OGN D D B0 D B1 D B2 D B3 D B4 D B5 D B6 D B7 D B8 D B9 O TR B C KIN SY N C O PD D IF F TR I _A TR I _B AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D AGN D 34 35 36 37 38 43 44 45 46 47 48 D A0 D A1 D A2 D A3 D A4 D A5 D A6 D A7 D A8 D A9 O TR A 20 21 22 26 27 28 29 30 31 32 33 D B0 D B1 D B2 D B3 D B4 D B5 D B6 D B7 D B8 D B9 O TR B D B [ 9: 0] , O TR B 18 19 12 15 17 14 C KIN SY N C O D IF F 7 8 9 16 51 53 54 57 60 63 64 AGN D AGN D +3 . 0V Note: bypass capacitors for pins 13, 24, 39, 41, 52, 61, 62 0. 0 1uF 0. 0 1uF 0. 0 1uF 0. 0 1uF 0. 0 1uF 0. 0 1uF 0. 0 1uF AGN D Figure 7. Typical Application Circuit for the XRD64L42 Operating in Differential Mode XRD64L42 Rev. P2.10 0. 2 uF Note: VRHF=1.25[(10K/10K)+1]=2.5V XRD64L42 XRD6442 INTEGRAL NONLINEARITY XRD6442 DIFFERENTIAL NONLINEARITY ERROR Fc = 40MHz 0.8 INL ERROR in LSB 0.8 0.4 0.2 0 -0.2 -0.4 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 950 1000 900 850 800 750 700 650 600 550 500 450 OUTPUT CODE OUTPUT CODE Figure 8. Differential Non-Linearity, Differential Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V, VDD=3V Figure 9. Integral Non-Linearity, Differential Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V, VDD=3V XRD64L42 Crosstalk Fs=40MSPS Singel-Ended and Differential Modes Channel 1=1MHz, Channel 2=(1.5MHz-10.5MHz) XRD64L42 IMD Fin1 = 2.51Mhz, Fin2 = 3.4375Mhz 8192-Point FFT, Fclock =40.0MHz, Differential input mode 0.00 -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 -110.00 -120.00 -20 -40 Single-Ended Input -60 Differential Input -80 -100 1.5 19.233 18.271 17.310 16.348 15.386 14.424 13.462 12.500 11.538 10.576 9.614 8.652 7.690 6.729 5.767 4.805 3.843 2.881 1.919 Fbin Crosstalk (dB) 0 0.957 Relative Power in db 400 350 300 250 200 150 0 951 1001 901 851 801 751 701 651 601 551 501 451 401 351 301 251 201 151 101 1 51 100 -0.8 -0.8 50 DNL Error in LSB 0.6 3 4.5 6 7.5 9 10.5 Input Frequency (MHz) Frequency Figure 10. Intermodulation Distortion, Fin1=2.51MHz, Fin2=3.4375MHz, 8192-point FFT, Fc=40MHz, Differential Input Mode Figure 11. Crosstalk vs Input Frequency, VDD=3V, Differential and Single Ended Inputs Rev. P2.10 13 XRD64L42 0 0 SingleTone 8192 Point FFT SFDR -71.19 SINAD -59.89 -20 -40 -40 Relative Power in dB Relative Power in dB SingleTone 8192 Point FFT SFDR -73.18 SINAD -59.77 -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 DC 2.4 4.9 7.3 9.8 12.2 14.6 17.1 19.5 DC 2.4 4.9 Frequency in MHz 9.8 12.2 14.6 17.1 19.5 Frequency in MHz Figure 12. FFT Spectrum @Fclock = 40.0MHz, Fin = 1.0MHz, DIFFERENTIAL INPUT MODE Figure 13. FFT Spectrum @Fclock = 40.0MHz, Fin = 4.0MHz, DIFFERENTIAL INPUT MODE 0 SNR vs Input Frequency SingleTone 8192 Point FFT SFDR -67.12 SINAD -58.28 -20 70.00 Relative Power in dB -40 Relative Power in dB 7.3 -60 -80 -100 -120 Differential Input 60.00 50.00 Single-ended 40.00 30.00 20.00 ClockRate: 40MHz AVDD,DVDD @3.0v 10.00 -140 DC 2.4 4.9 7.3 9.8 12.2 14.6 17.1 19.5 30 14 10 8 7 5 4 3 2 1 0 0.00 -160 fIN (MHz) Frequency in MHz Figure 14. FFT Spectrum @Fclock = 40.0MHz, Fin = 10.0MHz, DIFFERENTIAL INPUT MODE Figure 15. SNR vs Input Frequency, Differential and Single Ended Inputs, VDD=3V Rev. P2.10 14 XRD64L42 Supply Current vs Sample Clock Frequency SINAD vs Input Frequency 70 AIDD 60 60.00 Dif f erent ial Input Supply Current (mA) Relative Power in dB 70.00 50.00 Single-ended 40.00 30.00 20.00 50 40 30 TA=25°C, 1MHz<Fin<10MHz DIDD 20 ClockRat e: 40MHz 10.00 AVDD,DVDD @3.0v 10 DOIDD 0.00 30 10 7 4 2 0 0 10 15 20 25 30 35 40 45 50 55 60 fs (MSPS) fIN (MHz) Figure 17. Supply Current vs Sample Clock Frequency Figure 16. SINAD vs Input Frequency, Differential and Single Ended Inputs, VDD=3V R in vs T em p erature VCMO and VBG vs Temp 1.26 26.5 26.4 VCMO 1.255 (Voltage) 26.3 26.2 1.25 26.1 VBG 1.245 26 25.9 1.24 25.8 @VDD=3.0V 1.235 25.7 -40 +25 -40 +85 +25 +85 T em p. (°C ) Temp (Degree C) Figure 18. VCMO and VBG vs Temperature Figure 19. Rin of VINA+, VINB+ vs Temperature at Fc=40MSPS Rev. P2.10 15 XRD64L42 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet January 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. P2.10 16