xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR JUNE 2004 REV. 1.0.1 GENERAL DESCRIPTION The XRD9818 is a fully integrated, high-performance analog signal processor/digitizer specifically designed for use in 3-channel/2-channel/1-channel CCD/CIS document imaging applications. Each channel of the XRD9818 includes a Correlated Double Sampler (CDS), Offset adjustment, Programmable Gain Amplifier (PGA). After the gain and offset adjustments the analog inputs are sequentially sampled and digitized by a 16-bit A/D converter. The digital output data is available in 8 or 4-bit wide multiplexed format. The analog front-end can be configured for use in CCD or CIS data acquisition applications. The CDS mode of operation supports both line and pixel-clamp modes and can be used to achieve significant reduction in system 1/f noise and CCD reset clock feed-through. Five programmable clamp levels are available in CCD mode to adjust for CCD signal swing and reset pulse size. For CIS mode there are 3 selectable reference options, two internally generated and one external applied reference. Two PGA ranges, programmable through the serial port, help interface the XRD9818 to CCD imagers that have either a 3V or 2V output swings. The range of 1x to 5x is used for 3V inputs and the range of 1.5x to 7.5x is used for 2V inputs. Each channel has an offset range of -180mV to 180mV (1.4mV/step) for fine adjustment and an additional -100mV to 200mV (100mV/step) of gross offset adjustment to correct for any system offsets. FEATURES • 16-Bit A/D Converter • Triple-Channel, 4MSPS Color Scan Mode • Single-Channel, 8MSPS Monochrome Scan Mode • Multiplexed 8-Bit or 4-Bit Output Data Formats • Triple Correlated Double Sampler • Triple 9-Bit Programmable Gain Amplifier • Two Programmable Gain Ranges • Triple 10-Bit Offset Compensation DAC • -280mV to +380mV Offset Compensation • 28-pin TSSOP Package • Internal Voltage Reference • 3V Operation with 5V Tolerant inputs • Low Power CMOS: 190mW @ 3.3V (typ), Power Down 1mW (typ) APPLICATIONS • 48-Bit Color Scanners • High-performance CCD or CIS Color Scanners • Multifunction Peripherals • Film Scanners Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 FIGURE 1. BLOCK DIAGRAM OF THE XRD9818 BSAMP VSAMP ADCLK LCLMP INTERNAL TIMING CONTROL AVDD AVDD 9-BIT RED(+) Programmable Buffered CDS or S/H PGA AGND AGND REGISTER REGISTER VREF 1.24V 10-Bit Offset DAC DVDD DGND GRN(+) CMN(-) Programmable Buffered CDS or S/H 3-1 MUX PGA 16-BIT A/D 16 OUTPUT PORT REFIN 9-BIT 4/8 Output Data Bus VREF- VCM VREF+ REGISTER REGISTER CAPP CMREF CAPN 10-Bit Offset DAC 9-BIT BLU(+) Programmable Buffered CDS or S/H PGA REGISTER I/O CONTROL AND CONFIGURATION REGISTERS REGISTER Clamp/ Reference DAC SDI SCLK LOAD 10-Bit Offset DAC PRODUCT ORDERING INFORMATION Product Number Package Type Operating Temperature Range XRD9818ACG 28-Lead TSSOP 0°C to +70°C 2 XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 FIGURE 2. PIN OUT OF THE XRD9818 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 XRD9818 21 9 20 10 19 11 18 12 17 13 16 14 15 3 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 PIN DESCRIPTIONS Pin # Name Type Description 1 RED+ analog RED Analog Positive Input 2 AGND ground ANALOG GROUND 3 AVDD power ANALOG VDD 4 LCLMP clock Line Clamp clock 5 VSAMP clock Video Sample clock 6 BSAMP clock Black Sample clock 7 ADCLK clock ADC clock 8 DGND ground Digital GROUND 9 LOAD digital in Serial Port Load 10 DVDD power 11 SDI digital in 12 SCLK clock Serial Port Clock 13 ADCO[0] output ADC parallel out 0 14 ADCO[1] output ADC parallel out 1 15 ADCO[2] output ADC parallel out 2 16 ADCO[3] output ADC parallel out 3 17 ADCO[4] output ADC parallel out 4 18 ADCO[5] output ADC parallel out 5 19 ADCO[6] output ADC parallel out 6 20 ADCO[7] output ADC parallel out 7 21 AVDD power ANALOG VDD 22 AGND ground ANALOG GROUND 23 CAPN analog ADC Reference By-Pass 24 CAPP analog ADC Reference By-Pass 25 CMREF analog Common Mode Reference for ADC 26 CMN- analog COMMON Analog Reference Negative Input 27 BLU+ analog BLUE Analog Positive Input 28 GRN+ analog GREEN Analog Positive Input Digital VDD Serial Port Data Input 4 (8-bit LSB) (4-bit LSB) (8-bit/4-bit MSB) xr xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 ELECTRICAL CHARACTERISTICS - XRD9818 AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions SYSTEM SPECIFICATIONS (INCLUDES CDS, PGA AND A/D) Differential Non-Linearity DNL Integral Non-Linearity INL Output Noise Low Gain -1.0 LSB PGA Gain = min 50 LSB PGA Gain = min NMin 15 LSBrms PGA Gain = min, GS=0 Output Noise High Gain NMax 34 LSBrms PGA Gain = max, GS=0 System Offset Low Gain SOMin mV PGA Gain = min System Offset High Gain SOMax mV PGA Gain = max Parameter Symbol Unit Conditions -50 -0.9/+0.9 20 2.5 100 20 Min Typ Max VOLTAGE REFERENCE SPECIFICATIONS Vref(+) CAPP 1.9 2.2 2.5 V Vref(-) CAPN 0.5 0.7 0.9 V Delta Vref [Vref(+) - Vref(-)] ∆VREF 1.25 1.5 1.75 V VCMREF VCM 1.05 1.2 1.35 V Parameter Symbol Min Typ Max Unit Conditions 150 Ω Clamp Enabled MΩ Clamp Disabled CDS - S/H SPECIFICATIONS Input Switch-On Resistance Ron Input Switch-Off Resistance Roff 66 330 Internal Voltage Clamp Vclmp1 2.8 3.0 3.125 V CL[2:0]=110 Internal Voltage Clamp Vclmp2 -0.1 0.0 0.1 V CL[2:0]=001 Max Reset Pulse Vrst 1.5 Input Voltage Range INVR V 3.0 2.0 V V 5 GS=0 GS=1 XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR xr REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818 AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions OFFSET SPECIFICATIONS Fine Offset Range Min FOFR- -255 -180 -120 mV Fine Offset Range Max FOFR+ +120 +180 +255 mV Fine Offset Step FOFRES 1.4 mV Fine Offset Range Linearity FOFRL +/-1.5 %FS Gross Offset Range Min GOFR- -260 -200 -150 Gross Offset Range Max GOFR+ +75 +100 +135 Gross Offset Step GOFRES Parameter Symbol 100 Min Typ Max 8-bit (256 settings) mV 2-bit (4 setting) Unit Conditions PGA SPECIFICATIONS Gain Range Min GRMin 0.84 1 1.2 V/V default Gain Select, GS=0 Gain Range Max GRMax 4.5 5 6.20 V/V default Gain Select, GS=0 Gain Resolution GRES -10.0 7.8 - mV/lsb default Gain Select ,GS=0 Gain Range Min GRMin 1.3 1.5 1.7 V/V Gain Select , GS=1 Gain Range Max GRMax 6.65 7.5 8.90 V/V Gain Select , GS=1 Gain Resolution GRES mV/lsb Gain Select , GS=1 Parameter Symbol Unit Conditions 11.7 Min Typ Max DIGITAL INPUT SPECIFICATIONS Valid Input Logic Low Vil 0.5 V Valid Input Logic High Vih 2.60 Low Level Input Current Iil -5 0.1 5 µA High Level Input Current Iih 10 65 150 µA Input Capacitance CIN V 10 pf 6 w/internal 50K pull down R’s xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818 AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions V ISink = 2.0mA, CL=10pf V ISource = 2.0mA, CL=10pf DIGITAL OUTPUT SPECIFICATIONS Valid Output Logic Low Vol Valid Output Logic High Voh VDD-0.5 Tristate Leakage IOLeak -10 Parameter Symbol 0.5 Min 0.1 +10 µA Typ Max Unit Conditions POWER SUPPLIES - 3 CHANNEL MODE Analog Power Supply AVDD 3.0 3.3 3.6 V Digital Power Supply DVDD 3.0 3.3 3.6 V Analog IDD IAVDD 30 57 70 mA AVDD = DVDD = 3.6V Digital IDD IDVDD 0.1 7 20 mA AVDD = DVDD = 3.6V IDD Total IDD 31 64 90 mA AVDD = DVDD = 3.6V Power Dissipation PD 112 230 325 mW AVDD = DVDD = 3.6V Power Down Current IDDPDN 0.2 1.3 Parameter Symbol Typ Max Unit Conditions Min POWER SUPPLIES - 1 CHANNEL MODE Analog Power Supply AVDD 3.0 3.3 3.6 V Digital Power Supply DVDD 3.0 3.3 3.6 V IDD Total IDD 40 mA AVDD = DVDD = 3.6V Power Dissipation PD 145 mW AVDD = DVDD = 3.6V Power Down Current IDDPDN 0.2 1.3 7 mA XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR xr REV. 1.0.1 ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818 AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions SERIAL PORT WRITE TIMING SPECIFICATIONS Data Setup Time Tds 10 ns Data Hold Time Tdh 10 ns Load Setup Time Tls 10 Load Hold Time Tlh 10 ns SCLK Period Tsclk 125 ns Load Pulse High Period Tlpw 125 ns 1 SCLK period Unit Conditions Parameter Symbol Min ∞ Typ Max ns TIMING SPECIFICATIONS ADCLK Duty Cycle daclk 50 % ADCLK Period tcp3b tcp3n tcp2b tcp2n tcp1b tcp1n 83.3 41.7 83.3 41.7 125 62.5 ns ns ns ns ns ns 3-CH, 8bit (byte) output 3-CH, 4bit (nibble) output 2-CH, 8bit (byte) output 2-CH, 4bit (nibble) output 1-CH, 8bit (byte) output 1-CH, 4bit (nibble) output Conversion Period tcr3 tcr2 tcr1 250 167 125 ns ns ns 3-Channel Mode 2-Channel Mode 1-Channel Mode BSAMP Pulse Width tpwb 15 30 ns VSAMP Pulse Width tpwv 15 30 ns VSAMP ↓ edge delay from rising ADCLK tvfcr 12 ns Settling time tstl 15 ns Aperture Delay tap 3 ns Output Delay todv 12 ns Latency lat 9 18 ADCLK cycles 8 B/N=0 (byte mode) B/N=1 (nibble mode) xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 PRODUCT DESCRIPTION 1.0 INTRODUCTION The XRD9818 contains all of the circuitry required to create a complete 3-channel signal processor/digitizer for use in CCD/CIS imaging systems. It can be configured to operate in a 3-CH rotating (RGB), 2-CH rotating (RG, GR, GB or BR), or a 1-CH fixed (R, G or B) mode. Each channel includes a correlated-double-sampler/sample-hold (CDS/SH), channel offset adjustment and programmable gain amplifier (PGA). After signal conditioning the channel outputs are multiplexed and digitized by a 16-bit A/D converter. The XRD9818 has selectable 8-bit (byte) or 4-bit (nibble) data output modes. The ADCLK runs up to 12MHz in the 8-bit data output mode or 24MHz in the 4-bit data output mode. In order to maximize flexibility, the specific operating mode is programmable through internal configuration registers. In addition, the offset and gain of each channel can be independently programmed through separate offset and gain registers. The configuration, offset and gain register information is loaded through a 3-pin serial interface. 2.0 MODES OF OPERATION 2.1 3-CH CCD Mode In 3-CH mode the XRD9818 simultaneously samples the red, green and blue channel inputs. The CDS extracts the video information which corresponds to the difference between the sample black reference and video level for each pixel. The black reference level is sampled on the falling edge of BSAMP and the video level is sampled on the falling edge of VSAMP. This information is then level shifted and gained up according to the contents of the Offset and PGA registers respectively. The data is then sequentially converted (Red → Green → Blue) by a 16-bit A/D converter. In CCD mode, each channel input is sampled with respect to the CMN- input. This provides a sudo-differential input. Typically the CMN- input is connected to the CCD ground through a capacitor. This coupling capacitor should be at least 3 times the capacitor value used to couple the RED+, GRN+ and BLU+ inputs. The timing for this mode is shown in Figure 15. 2.2 2-CH CCD Mode The 2-CH mode operates identically to the 3-CH CCD mode except that only 2 channels are actively used to process CCD output signals. The two channels to be used and the order in which they process data is determined from the configuration of the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are four possible 2-CH configurations, RG, GR, GB and BR. To conserve power that channel not being utilized is powered down. The timing for this mode is shown in Figure 16. 2.3 1-CH CCD Mode The 1-CH mode operates identically to the 3-CH or 2-CH CCD modes except that the channel sampled is fixed to only one input. The channel selection is set by the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are three possible one channel modes: R, G or B. The channels not being used will be powered down to conserve power. The timing for this mode is shown in Figure 17. 9 XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR xr REV. 1.0.1 2.4 3-CH CIS Mode In this mode the XRD9818 simultaneously samples (S/H) the red, green and blue channel inputs. The video level is sampled on the falling edge of VSAMP. Each channels S/H extracts the video information from each pixel. This data is level shifted and gained up according to the contents of the Offset and PGA registers respectively. The data is then sequentially converted (Red → Green → Blue) by a 16-bit A/D converter. In CIS mode, each channel input is sampled with respect to the voltage at the CMN- input. The voltage at CMN- can be either generated by a programmable internal reference (C/R DAC) or supplied by an external source. The timing for this mode is shown in Figure 18. 2.5 2-CH CIS Mode The 2-CH mode operates identically to the 3-CH CIS mode except that only 2 channels are actively used to process CIS output signals. The two channels to be used and the order in which they process data is determined from the configuration of the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are four possible 2-CH configurations, RG, GR, GB and BR. To conserve power the channel not being utilized is powered down. 2.6 1-CH CIS Mode The 1-CH mode operates identically to the 3-CH or 2-CH CIS modes except that the channel sampled is fixed to only one input. The channel selection is set by the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are three possible one channel modes: R, G or B. The channels not being used will be powered down. 10 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 3.0 REGISTER MAP INTERNAL REGISTER MAP Register Name A3 A2 A1 A0 D9 RED Gain 0 0 0 0 msb lsb GREEN Gain 0 0 0 1 msb lsb BLUE Gain 0 0 1 0 msb lsb RED Offset 0 0 1 1 COR[1] COR[0] FOR[7] FOR[6] FOR[5] FOR[4] FOR[3] FOR[2] FOR[1] FOR[0] GREEN Offset 0 1 0 0 COG[1] COG[0] FOG[7] FOG[6] FOG[5] FOG[4] FOG[3] FOG[2] FOG[1] FOG[0] BLUE Offset 0 1 0 1 COB[1] COB[0] FOB[7] FOB[6] FOB[5] FOB[4] FOB[3] FOB[2] FOB[1] FOB[0] MODE 1 0 1 1 0 CH[2] CH[1] MODE 2 0 1 1 1 PD OE BSAMPDelay 1 0 0 0 BL[4] BL[3] BL[2] BL[1] BL[0] VSAMPDelay 1 0 0 1 VL[4] VL[3] VL[2] VL[1] ADCLKDelay 1 0 1 0 A[4] A[3] A[2] TEST 1 0 1 1 * * * RESET/RB 1 1 1 1 Reset READ Note: Address Data Bits D8 D7 D6 CH[0] GS D5 LC D4 CCDEN D3 D2 D1 D0 B/N C/R[2] C/R[1] C/R[0] Lpol ADCpol Bpol Vpol BT[4] BT[3] BT[2] BT[1] BT[0] VL[0] VT[4] VT[3] VT[2] VT[1] VT[0] A[1] A[0] DO[4] DO[3] DO[2] DO[1] DO[0] * * * * * * * RB[3] RB[2] RB[1] RB[0] * Exar test bits, do not over write the default values. Shaded cells represent unused bits. 3.1 PGA Gain Registers There are three PGA registers for individually programming the gain in the RED, GREEN, and BLUE channels. Each gain register has 9 bits of resolution. Bits D[9:1] control the gain while bit D0 is N/A (don’t care). The XRD9818 has two gain ranges to help interface to imagers that have 3V or 2V of output signal swing. The GS bit, located in the MODE 1 register, defaults to GS=0 for a gain of 1x to 5x or if GS=1 the gain would be 1.5x to 7.5x. The gain range of 1 to 5x (GS=0) is intended for use with imagers that have a 3V output swing, while the gain range 1.5 to 7.5x is intended for imagers with 2V or less of output swing. The coding for the PGA registers is straight binary. See “Section 4.3, Programmable Gain” on page 20 for a functional description of the XRD9818’s gain stage. GAIN REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 msb 000000000* … 111111111 * Power-on default value 11 D1 D0 Gain (V/V) Gain (V/V) lsb N/A w/GS bit = 0* w/GS bit = 1 not used 1x … 5x 1.5x … 7.5x xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 3.2 Offset Registers There are three Offset registers for individual control of the offsets applied to the RED, GREEN, and BLUE channels. There are separate course and fine controls to set the desired offset compensation for each channel. Bits D9 and D8 set the course offset from -100mV to +200mV in 100mV increments. Bits D7:D0 set the fine offset range from -180mV to +180mV in 1.4mV increments. The polarity of the offset correction is defined as positive for the normal direction in which offsets occur in an imager, see Figure 11. Please see “Section 4.2, Programmable Offset Adjust” on page 19 for a description of the XRD9818’s offset correction circuitry. OFFSET REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COx[1] COx[0] FOx[7] FOx[6] FOx[5] FOx[4] FOx[3] FOx[2] FOx[1] FOx[0] Fine offset control 01111111 → 150mV … 00000000* → 0mV 10000000 → 0mV … 11111111 → -150mV Course offset control 00* → 0mV 01→ -100mV 10 → 100mV 11 → 200mV * Power-on default value 3.3 Mode Registers There are two mode registers that control the configuration and operation of the XRD9818. The Mode 1 register controls the configuration of input mux mode, gain range, Line Clamp enable, CCD or CIS select, byte or nibble data output mode and clamp level select. The Mode 2 register controls the power down, output enable and polarities of the input timing signals. MODE 1 REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CH[2] CH[1] CH[0] GS LC CCDEN B/N C/R[2] C/R[1] C/R[0] 0* → 1x to 5x 0* → Line Clamp Off 0* → CCD 0 → byte output mode 000* → 3CH (RGB) 001 → RED channel 010 → GRN channel 011 → BLU channel 100 → 2CH (RG) 101 → 2CH (GR) 110 → 2CH (GB) 111 → 2CH (BR) 1 → 1.5x to 7.5x 1 → CIS 1 → Line Clamp On 1* → nibble output mode 000 → high Z 001 → 0V 010 → 1.25V 011 → 2.0V 100 → 2.6V 101 → 2.8V 110* →3.0V 111 → VDD * Power-on default value CH[2:0] - Input Mux/Channel select. Selects between 3-CH (RGB), 1-CH RED, 1-CH GRN, 1-CH BLU, 2-CH (RG), 2-CH (GR), 2-CH (GB) or 2-CH (BR) input mux modes. GS - Gain Range Select. Gain range 1x to 5x for 3V input signals, range 1.5x to 7.5x for 2V signals. LC- Line Clamp enable. Gates clamping function with the timing signal LCLMP. CCDEN - CCD enable. Defines operation for a CCD or CIS imager input. B/N - Byte or Nibble output mode. Defines 8bit (byte) or 4bit (nibble) data output format. C/R[2:0] - Clamp/Reference Select. The setting determines the clamp/reference voltage applied to the CMN- input. The settings 2.0V through VDD are intended for use in CCD applications. The 0V, 1.25V or "high Z" settings are intended for use for CIS applications. If "high Z" is selected an external source can be applied to CMN- for the reference. For a description of the C/R DAC please See “Section 4.1.2, Clamp/Reference (C/R) DAC” on page 17. 12 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 MODE 2 REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PD OE N/A N/A N/A N/A LPOL ADCPOL BPOL VPOL 0* → Normal Operation 0* → Normal Operation Not used Not used Not used Not used 0*→ NonInverted 0*→ NonInverted 0*→ NonInverted 0*→ NonInverted 1 → PWR Down 1 → Data bus tri-stated 1 → Inverted 1 → Inverted 1 → Inverted 1 → Inverted * Power-on default lt value PD - Power Down. Does not affect the internal register settings but does power down the entire part excluding the serial interface. There will be some power up settling time required to reestablish the ADC reference, CAPP and CAPN, voltages. OE - Output Enable. Tristate control for the output data bus. LPOL - LCLMP input polarity select. (Noninverting pol ⇒ active high, inverted pol ⇒ active low) ADCPOL - ADCLK polarity select. (Noninverting pol ⇒ begins high, inverted pol ⇒ begins low) BPOL - BSAMP polarity select. (Noninverting pol ⇒ active high, inverted pol ⇒ active low) VPOL - VSAMP polarity select. (Noninverting pol ⇒ active high, inverted pol ⇒ active low) 3.4 BSAMP Delay Register The BSAMP Delay register controls the internal delays added to the leading and the trailing edges of the BSAMP timing signal. The width and position of the BSAMP pulse can be adjusted through the leading and trailing edge delay settings. This is useful to match the sampling requirements of the incoming CCD waveform. BSAMP DELAY REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BL[4] BL[3] BL[2] BL[1] BL[0] BT[4] BT[3] BT[2] BT[1] BT[0] BSAMP Trailing edge delay 00000* → 0ns 00001 → 1ns … 11110 → 30ns 11111 → 31ns BSAMP Leading edge delay 00000* → 0ns 00001 → 1ns … 11110 → 30ns 11111 → 31ns * Power-on default value BL[4:0] - Sets the amount of delay added to the leading edge of BSAMP. BT[4:0] - Sets the amount of delay added to the trailing edge of BSAMP. 13 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 3.5 VSAMP Delay Register The VSAMP Delay register controls the internal delays added to the leading and the trailing edges of the VSAMP timing signal. The width and position of the VSAMP pulse can be adjusted through the leading and trailing edge delay settings. This is useful to match the sampling requirements of the incoming CCD/CIS waveform. VSAMP DELAY REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VL[4] VL[3] VL[2] VL[1] VL[0] VT[4] VT[3] VT[2] VT[1] VT[0] VSAMP Trailing edge delay 00000* → 0ns 00001 → 1ns … 11110 → 30ns 11111 → 31ns VSAMP Leading edge delay 00000* → 0ns 00001 → 1ns … 11110 → 30ns 11111 → 31ns * Power-on default value VL[4:0] - Sets the amount of delay added to the leading edge of VSAMP. VT[4:0] - Sets the amount of delay added to the trailing edge of VSAMP. 3.6 ADCLK Delay Register The ADCLK Delay register controls the delay added to the ADCLK timing signal and Data Output. ADCLK DELAY REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A[4] A[3] A[2] A[1] A[0] DO[4] DO[3] DO[2] DO[1] DO[0] Output Data valid delay 00000* → 0ns 00001 → 0.5ns … 11110 → 15.0ns 11111 → 15.5ns ADCLK delay 00000* → 0ns 00001 → 1ns … 11110 → 30ns 11111 → 31ns * Power-on default value A[4:0] - Sets the amount of internal delay added to the ADCLK signal. DO[4:0] - Sets the amount of delay from internal ADCLK to valid data out. 3.7 Test Register The TEST register is used for EXAR internal test requirements. Do not over write this register. TEST REGISTER SETTINGS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Test Only Test Only Test Only Test Only Test Only Test Only Test Only Test Only Test Only Test Only 00000000* → Do not modify * Power-on default value 14 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 3.8 Reset and ReadBack Register This register controls the reset and readback function of the XRD9818. The part can be reset to its power-up default state by writing to the RESET bit. This will reset all register contents to their default state, reset the serial port contents and counters and configure the input mux to the red input channel. The XRD9818 will automatically recover approximately 10ns after the RESET bit is set high. After the reset recovery the register contents will be reset to their default conditions and the RESET bit will be set back to a low. The readback function is controlled through this register also. The READ bit simply enables the readback function. When the READ bit is set high the contents of the register pointed to by the address in RB[3:0] is put out on the data output bus. The register contents are output to the 10 LSB’s and the 6 MSB’s are padded with zeros. The output data format is set to either Byte or Nibble format as controlled by the B/N bit (D3) in the MODE 1 register. The register contents will continually be output to the data bus until the readback bit is set low. RESET/READBACK REGISTER D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reset Read N/A N/A N/A N/A RB[3] RB[2] RB[1] RB[0] Not used Not used Not used Not used 0* → Normal Oper- 0* → Normal Operation ation 1 → Reset Device 1 → Readback Enabled Address of register to be read 0000* → RED Gain register 0001 → GREEN Gain register … 1111 → RESET/RB register * Power-on default value Reset - Returns all internal register values back to their default settings. Read - Readback enable. RB[3:0] - Readback register address. Points to the internal register of interest to be read. 15 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 4.0 CIRCUIT OPERATION 4.1 4.1.1 Analog Inputs Sampling The XRD9818’s analog front end (AFE) uses a switched capacitor network to achieve a correlated double sample (CDS) of the input in CCD mode or a sample and hold (S/H) of the input in CIS mode. Figure 3 shows the 9818’s AFE (CDS/SH + PGA) which samples and gains the input signal. Figure 4 shows the external and internal timing requirements to achieve a correlated double sample and gain of a CCD input signal. FIGURE 3. XRD9818 INPUT CIRCUITRY φB φV SW8 SW4 SW2 Input SW1 Reference φR φCL SW3 C3 C1 φV SW6 C7 C5 to ADC C2 C6 φR SW7 C4 SW5 φV C8 SW9 φB φV C1 = C2 = 7.5pf C3 = C4 = 7.5pf or 11pf C5 = C6 = 1.5pf or 7.89pf C7 = C8 = 1pf In addition to sampling and gaining the CCD signal the 9818 input is designed to reject the reset pulse noise present also. The XRD9818 can withstand reset pulses up to 1.5V or more depending upon the input conditions. The timing signal φR controls SW2 and SW3 is generated internally by the XRD9818. SW2 and SW3 open after a short delay following the sampling edge of VSAMP and close at the leading edge of BSAMP. FIGURE 4. INTERNAL AFE SAMPLE TIMING (EX. 3CH CCD MODE) CCDIN ADCLK byte ADCLK nibble BSAMP VSAMP φR φB φV Note : φV = ADCLK VSAMP The XRD9818 utilizes a differential input and signal path which samples the CCD reference level on capacitors C1 and C2. When φB goes high, SW4 and SW5 close storing the CCD reference level on C1 and C2. When φB goes low a fixed gain is applied to the input signal as it tracks the video input. When φV goes high the video content is applied to capacitors C5 and C6. The final video level is stored on C5 and C6 when φV goes low. The video content is then amplified again and sampled by the ADC at the proper time 16 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 4.1.2 Clamp/Reference (C/R) DAC 4.1.2.1 Clamp Operation in CCD Mode In CCD mode a clamp is required to level shift the CCD output signal into XRD9818’s input common mode range. The clamp circuitry ensures that the signals present at the analog inputs fall within the operating range of those pins. The clamp operation takes place while BSAMP is active. When BSAMP is active, SW1 is closed connecting the C/R DAC to the analog input pin. This establishes the C/R DAC voltage on the external coupling cap. When SW1 is opened, the C/R DAC voltage is stored on the external coupling cap. This clamping operation will occur while BSAMP is active. The C/R DAC clamp voltage is programmable. This gives the system designer added flexibility to make adjustments for different sensor signal swing and reset pulse characteristics. FIGURE 5. CCD MODE INPUT CLAMP (ALL THREE CHANNELS ARE IDENTICAL) CCD ouput CIN φR RED+ SW2 C1 RED+ 1nf CREF SW1 φCL SW3 CMN- to PGA C2 φR 0.1uf C/R DAC CL[2] CL[1] CL[0] Clamp/Reference DAC The XRD9818 has 2 clamp modes available for used in CCD applications, Line Clamp and Pixel Clamp. Line Clamp mode only performs the clamp when the LCLMP pin is active. The control timing, φCL, for SW1 is generated by the “ANDing” of the external timing signals LCLMP & BSAMP and is shown in Figure 6. FIGURE 6. LINE CLAMP MODE TIMING CCDIN ADCLK BSAMP VSAMP LCLMP φCL 17 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 Pixel Clamp mode eliminates the gating function of BSAMP with LCLMP. In Pixel Clamp mode the clamping function is performed with every BSAMP, see Figure 7. Selection of the Line Clamp or Pixel Clamp modes is defined by the state of the LC bit (D5) located in the MODE 1 register. FIGURE 7. PIXEL CLAMP MODE TIMING CCDIN ADCLK BSAMP VSAMP φCL 4.1.2.2 Reference Operation in CIS Mode In most CIS applications the imager output is connected directly to the inputs. With no external coupling capacitor, there is no need to perform a clamp. Unlike a CCD output signal that has a black reference level for each pixel a CIS output is sampled with respect to a black reference voltage. In CIS mode, the C/R DAC is used to provide that reference as shown below in Figure 8. The reference voltage is programmable to help interface to a variety of CIS imagers. If a CIS imager provides its own reference voltage the C/R DAC can be configured into a "high Z" state so that an external reference can be connected directly to the CMN- pin. See the MODE 1 Register definition of bits C/R[2:0]. FIGURE 8. CIS MODE REFERENCE (INTERNAL OR EXTERNAL) C1 CIS Signal to PGA C2 0.1uf CMN- C/R DAC CL[2] CL[1] CL[0] Clamp/Reference DAC 18 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 4.2 Programmable Offset Adjust The offset adjustment circuitry of the XRD9818 is designed to compensate for any offsets present in the CCD or CIS output signal and/or overall scanner system. The total range of compensation available is -280mV to +380mV. This is achieved via a 10-bit Offset DAC that applies gain independent offset correction. The 10-bits of control is broken into 2 ranges, course and fine. There are 2 bits of course control that is designed to remove offsets in 100mV increments. The remaining 8-bits determine the fine control and has a range of +/-180mV in 1.4mV increments. Each channel has its own independent offset control. FIGURE 9. XRD9818 CHANNEL OFFSET BLOCK DIAGRAM VA CDS SH 8-Bit VB 16-Bit PGA 3:1 MUX ADC 8-Bit Offset DAC Fine Adjust 2-Bit Offset 2-Bit Programmable Serial Port Input 9-Bit Course Adjust Offset Block The offset correction range of both the Course and Fine DAC’s are shown in Figure 10. The Course DAC has four settings: 0mv, -100mV, 100mV and 200mV. The 2 msb’s, D[9:8], select the desired course offset setting. The Fine DAC has a range of +/-180mV. The Offset registers 8 lsb’s, D[7:0], select the desired fine setting. Bits D[6:0] program the magnitude while D[7] selects the polarity of the Fine DAC’s compensation. FIGURE 10. OFFSET CORRECTION (COURSE & FINE DAC’S) Course DAC Settings COx[1:0] 00 01 10 11 150mV Offset (mV) 0 -100 100 200 10h Fine DAC Range 00h 0Fh FFh Code -150mV As can be seen in the Course Offset DAC’s range settings there is more correction range in the positive direction. This allows the system designer to maximize the usable offset correction range of the XRD9818 for a variety of imagers. Positive offset is defined as the normal offset direction found in either a CCD or CIS input signal, as shown in Figure 11. FIGURE 11. SIGNAL OFFSET POLARITY (CCD AND CIS) CCD C IS Negative Offset Positive Offset Ideal Black W hite CCD Dark Offset S ig n a l S ig n a l Positive Offset W hite Negative Offset 19 Ideal Black xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 The affect of the XRD9818’s offset correction DAC’s (Course & Fine) is defined as follows: VA = VInput - (VOSCourse + VOSFine ) note: positive offset values subtract from the input signal The course DAC value, VOSCOURSE, is defined in Figure 10 and the Fine DAC value is determined as follows: VOSFine = FBx[7] Offset Code (FBx[6:0]) 150mV 127 Note : FB[7] = 0 -> (+), FB[7] = 1 -> (-) The XRD9818 offset adjustment range is designed to maximize the correction range whether being used in a CCD or CIS application. 4.3 Programmable Gain There are three independent PGA’s, one for each input channel: Red, Green and Blue. The individual gain values are controlled by separate Red, Green and Blue gain registers. Each PGA has 9 bits of control for the full gain range. See Figure 12 for the PGA transfer function. The gain increments in a binary fashion from a minimum at code 0 to a maximum at code 511. The PGA has two gain ranges 1x to 5x and 1.5x to 7.5x to help interface to imagers with 3V or 2V outputs respectively. To select the 1x to 5x gain range for an imager that has a 3V single swing the GS bit in the MODE 1 register must be set low, GS=0 (default). To select the 1.5x to 7.5x gain range for use with imagers that have a 2V maximum signal swing the GS bit in the MODE 1 register must be set high, GS=1. FIGURE 12. XRD9818 PGA TRANSFER FUNCTION 8 7 GS=1 Gain (V/V) 6 GS=0 5 4 3 2 1 0 0 64 128 192 256 320 384 448 512 PGA Gain Code The XRD9818 channel gain equations are as follows: G a in 1 to 5 = 4 Gain Code 511 1 or G a in 1.5 to 7.5 = 6.0 20 Gain Code 511 1.5 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 5.0 SERIAL PORT INTERFACE The XRD9818 can be configured through a three pin interface (LOAD, SDI, and SCLK) with the serial port write timing shown below. Each write will include 4 bits of address, two dummy bits and 10 bits of data. To insure a valid write operation, the serial port control must detect minimum of 16 rising SCLK edges. Upon a valid write the XRD9818 will latch the last 16 bits of data presented at the rising edge of LOAD. The register address will be decoded and the 10bits of data will over write the contents of the addressed register. The LOAD setup time "Tls" can be indefinitely long. FIGURE 13. SERIAL PORT WRITE TIMING Tls Tlpw Tsclk Tlh Tds Tdh LOAD SCLK msb SDI E1 D u m m y A3 lsb A2 A1 A0 Register Address msb E0 D9 lsb D8 D u m m y D7 D6 D5 D4 D3 D2 D1 D0 Write Register Data LOAD is used to gate the SCLK input into the XRD9818. In order to eliminate any unintended high speed clocks into the part it is recommended that the LOAD signal only be active during the write operation. FIGURE 14. LOAD GATING OF SCLK SCLK (internal) LOAD SCLK 21 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 6.0 TIMING FIGURE 15. 3-CH CCD MODE SYSTEM TIMING (BYTE & NIBBLE MODES) Pixel (n) Pixel (n+3) Pixel (n+4) tcr3 tap ..... CCDIN tap tcp3b ..... ADCLK BYTE tcp3n ADCLK NIBBLE ..... tvfcr ..... BSAMP tstl ..... VSAMP todv OUTPUT DATA ADCO(7:0) BYTE ..... OUTPUT DATA ADCO(7:4) NIBBLE ..... An Bn Cn Dn En Fn todv BYTE Mode A=> Red (DB15-DB8) B=> Red (DB7-DB0) C=> GRN (DB15-DB8) D=> GRN (DB7-DB0) E=> BLU (DB15-DB8) F=> BLU (DB7-DB0) an bn cn dn en fn gn hn in jn kn ln NIBBLE Mode a=> RED (DB15-DB12) b=> RED (DB11-DB8) c=> RED (DB7-DB4) d=> RED (DB3-DB0) e=> GRN (DB15-DB12) f=> GRN(DB11-DB8) g=> GRN (DB7-DB4) h=> GRN (DB3-DB0) i=> BLU (DB15-DB12) j=> BLU (DB11-DB8) k=> BLU (DB7-DB4) l=> BLU (DB3-DB0) FIGURE 16. 2-CH CCD MODE SYSTEM TIMING (BYTE & NIBBLE MODES) Pixel (n) Pixel (n+5) Pixel (n+6) tcr2 tap ..... CCDIN tap tcp2b ..... ADCLKBYTE tcp2n ..... ADCLKNIBBLE tvfcr ..... BSAMP tstl ..... VSAMP todv OUTPUT DATA ADCO(7:0)BYTE ..... OUTPUT DATA ADCO(7:4)NIBBLE ..... An Bn Cn Dn todv BYTE Mode An=> 1ST CH (DB15-DB8) Bn=> 1ST CH (DB7-DB0) Cn=> 2ND CH (DB15-DB8) Dn=> 2ND CH (DB7-DB0) a n bn cn dn en fn NIBBLE Mode a=> 1ST CH (DB15-DB12) b=> 1ST CH (DB11-DB8) c=> 1ST CH (DB7-DB4) d=> 1ST CH (DB3-DB0) 22 gn hn e=> 2ND CH (DB15-DB12) f=> 2ND CH (DB11-DB8) g=> 2ND CH (DB7-DB4) h=> 2ND CH (DB3-DB0) xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 FIGURE 17. 1-CH CCD MODE SYSTEM TIMING (BYTE & NIBBLE MODES) Pixel (n) Pixel (n+9) Pixel (n+10) tcr1 tap ..... CCDIN tap tcp1b ..... ADCLKBYTE tcp1n ADCLK ..... BSAMP ..... tvfcr tstl ..... VSAMP todv OUTPUT DATA ADCO(7:0)BYTE ..... MSB (n-1) LSB (n-1) MSB (n) LSB (n) MSB(n+1) todv OUTPUT DATA ADCO(7:4)NIBBLE ..... An BYTE Mode Bn Cn Dn NIBBLE Mode A=> DB15-DB12 B=> DB11-DB8 C=> DB7-DB4 D=> DB3-DB0 MSB =>DB(15:8) LSB =>DB(7:0) FIGURE 18. 3-CH CIS MODE SYSTEM TIMING (BYTE & NIBBLE MODES) Pixel (n) Pixel (n+3) Pixel (n+4) tcr3 ..... CISIN tap tcp3b ..... ADCLK BYTE tcp3n ADCLK NIBBLE tvfcr ..... tstl ..... VSAMP todv OUTPUT DATA ADCO(7:0) BYTE ..... OUTPUT DATA ADCO(7:4) NIBBLE ..... An Bn Cn Dn En Fn todv BYTE Mode A=> Red (DB15-DB8) B=> Red (DB7-DB0) C=> GRN (DB15-DB8) D=> GRN (DB7-DB0) E=> BLU (DB15-DB8) F=> BLU (DB7-DB0) an bn cn dn en fn gn hn in jn kn ln NIBBLE Mode a=> RED (DB15-DB12) b=> RED (DB11-DB8) c=> RED (DB7-DB4) d=> RED (DB3-DB0) 23 e=> GRN (DB15-DB12) f=> GRN(DB11-DB8) g=> GRN (DB7-DB4) h=> GRN (DB3-DB0) i=> BLU (DB15-DB12) j=> BLU (DB11-DB8) k=> BLU (DB7-DB4) l=> BLU (DB3-DB0) xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 7.0 APPLICATION HOOK-UP DIAGRAMS FIGURE 19. TYPICAL HOOK-UP DIAGRAM FOR THE XRD9818 (AC COUPLED, CCD EXAMPLE) 15V AVDD DVDD 1nf CCD 1nf 1nf 0.1uf RED+ GRN+ AA VV DD DD BLU+ CMN- D V D ADCO7 D ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADC OUTPUT BUS 9818 CAPP 0.1uf A G N D D G N D 0.1uf 0.1uf 2.2uf A G N D 0.1uf 24 2.2uf LOAD SCLK SDI ASIC CMREF 2.2uf 0.1uf It is recommended that each power pin be 1uf decoupled to ground with capacitors placed as close to power pin as possible. 2.2uf CAPN ADCLK VSAMP BSAMP LCMP TG (timing generator) xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 8.0 PERFORMANCE DATA FIGURE 20. SYSTEM DNL, 3-CH OPERATION 9818 System 3CH DNL 1 0.8 0.6 0.4 Dnl (lsb) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 8192 16384 24576 32768 40960 49152 57344 65536 Code FIGURE 21. XRD9818 IDD VS TEMPERATURE XRD9818 IDD vs Temperture 70 60 IDD (mA) 50 40 IAVDD IDVDD IDDTOT 30 20 10 0 -40 -30 -20 -10 0 10 20 30 Temp 25 40 50 60 70 80 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 FIGURE 22. XRD9818 REFERENCE VS TEMPERATURE XRD9818 Reference vs Temperture 2.5 Voltage (V) 2 CAPP CAPN CAPP-CAPN VCM 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 Temperture (C) 26 40 50 60 70 80 xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 PACKAGE DIMENSIONS 28 LEAD THIN SHRINK SMALL OUTLINE (4.4mm TSSOP) Rev. 2.00 D 28 15 E1 E 1 14 Seating Plane C A A2 e SYMBOL A A1 A2 B C D E E1 e L α B INCHES MIN MAX 0.033 0.047 0.002 0.006 0.031 0.041 0.007 0.012 0.004 0.008 0.378 0.386 0.248 0.260 0.169 0.177 0.0256 BSC 0.018 0.030 0° 8° A1 MILLIMETERS MIN MAX 0.85 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.80 6.30 6.60 4.30 4.50 0.65 BSC 0.45 0.75 0° 8° Note: The control dimension is in millimeter column 27 α L xr XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR REV. 1.0.1 REVISION HISTORY Revision # Date Description A1.0.0 08/20/02 1st release of the XRD9818 advanced data sheet. A1.0.1 09/26/02 Modified Serial Port Read/Write timing diagrams, system specs INL, IRNMIN and IRNMAX A1.1.0 10/17/02 Changed definition of PGA to 9bit & overall system gain 1x to 5x, redefined serial port timing, added 3-CH & 1-CH timing diagrams for 8bit and 4bit data output modes, A1.2.0 11/13/02 Added pin def, updated black diagram including VCMREF pin & removing LCLP pin, updated 8bit 1-CH timing diagram A1.3.0 1/30/03 Updated pin def type for CMREF. Updated serial port timing diagram. Added input signal swing, reset pulse, Load pulse width and PGA spec’s to elec tables. Added register map & bit definitions. Remove IB spec from CDS-S/H Specifications. P1.0.0 11/14/03 Changed data sheet to Preliminary status. Added timing diagrams, functional descriptions and electrical table updates to reflect part performance. 1.0.0 1/29/04 Released version. Updated electrical tables & document with char data, some minor text edits to advance description, added performace data and application hook-up diagram. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet June 2004. 28