Complete 14-Bit CCD/CIS Signal Processor AD9822 FEATURES GENERAL DESCRIPTION 14-bit 15 MSPS ADC No missing codes guaranteed 3-channel operation up to 15 MSPS 1-channel operation up to 12.5 MSPS Correlated double sampling 1–6× programmable gain ±350 mV programmable offset Input clamp circuitry Internal voltage reference Multiplexed byte-wide output (8 + 6 format) 3-wire serial digital interface 3 V/5 V digital I/O compatibility 28-Lead SOIC or SSOP Low power CMOS: 385 mW (typ) Power-down mode: <1 mW The AD9822 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, correlated double sampler (CDS), offset DAC, and programmable gain amplifier (PGA) multiplexed to a high performance 14-bit ADC. The CDS amplifiers may be disabled for use with sensors such as contact image sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface and provide adjustment of the gain, offset, and operating mode. The AD9822 operates from a single 5 V power supply, consumes 385 mW of power typically, and is packaged in a 28-lead SOIC or SSOP. APPLICATIONS Flatbed document scanners Film scanners Digital color copiers Multifunction peripherals FUNCTIONAL BLOCK DIAGRAM VINR AVSS CML CDS CAPT CAPB AVDD CDS 14:8 MUX 8 MUX REGISTER PGA INPUT CLAMP BIAS 14 DOUT CONFIGURATION REGISTER 6 CDSCLK1 14-BIT ADC 3:1 MUX 9-BIT DAC OFFSET OEB BAND GAP REFERENCE PGA CDS DRVSS AD9822 9-BIT DAC VINB DRVDD PGA 9-BIT DAC VING AVSS 9 RED GREEN BLUE RED GREEN BLUE CDSCLK2 SCLK DIGITAL CONTROL INTERFACE GAIN REGISTERS SLOAD SDATA OFFSET REGISTERS ADCCLK 00623-001 AVDD Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. AD9822 TABLE OF CONTENTS Specifications..................................................................................... 3 1-Channel CDS Mode ............................................................... 12 Analog Specifications................................................................... 3 1-Channel SHA Mode ............................................................... 12 Digital Specifications ................................................................... 4 Internal Register Descriptions.................................................. 13 Timing Specifications .................................................................. 5 Circuit Operation ........................................................................... 15 Absolute Maximum Ratings............................................................ 6 Analog Inputs—CDS Mode ...................................................... 15 Thermal Characteristics .............................................................. 6 External Input Coupling Capacitors........................................ 15 ESD Caution.................................................................................. 6 Analog Inputs—SHA Mode...................................................... 16 Pin Configuration and Function Descriptions............................. 7 Programmable Gain AmplifierS (PGA) .................................. 16 Terminology ...................................................................................... 8 Applications..................................................................................... 17 Functional Description .................................................................. 12 Circuit and Layout Recommendations ................................... 17 3-Channel CDS Mode................................................................ 12 Outline Dimensions ....................................................................... 18 3-Channel SHA Mode................................................................ 12 Ordering Guide .......................................................................... 18 REVISION HISTORY 2/05—Rev. A to Rev. B Changes to Format .............................................................Universal Changes to Ordering Guide .......................................................... 18 Updated Outline Dimensions ....................................................... 18 12/99—Rev. 0 to Rev. A Rev. B | Page 2 of 20 AD9822 SPECIFICATIONS ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA gain = 1, unless otherwise noted. Table 1. Parameter MAXIMUM CONVERSION RATE 3-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY (ENTIRE SIGNAL PATH) ADC Resolution Integral Nonlinearity (INL) INL @ 6 MHz Differential Nonlinearity (DNL) DNL @ 6 MHz No Missing Codes No Missing Codes @ 6 MHz Offset Error Gain Error ANALOG INPUTS Input Signal Range1 Allowable Reset Transient1 Input Limits2 Input Capacitance Input Bias Current AMPLIFIERS PGA Gain at Minimum PGA Gain at Maximum PGA Gain Resolution2 PGA Gain Monotonicity Programmable Offset at Minimum Programmable Offset at Maximum Programmable Offset Resolution Programmable Offset Monotonicity NOISE AND CROSSTALK Total Output Noise @ PGA Minimum Total Output Noise @ PGA Maximum Channel-to-Channel Crosstalk @ 6 MHz POWER SUPPLY REJECTION AVDD = 5 V ± 0.25 V DIFFERENTIAL VREF (@ 25°C) CAPT to CAPB (2 V ADC Full-Scale Range) TEMPERATURE RANGE Operating Storage POWER SUPPLIES AVDD DRVDD OPERATING CURRENT AVDD DRVDD Power-Down Mode Current Min Typ Max 15 12.5 −1.0 14 −240 −1.4 MSPS MSPS 14 −17.0/+3.5 −10.5/+1.5 −0.65/+0.75 −0.6/+0.65 14 −19 +3.5 +1.1 +200 +6.9 2.0 1.0 AVSS − 0.3 AVDD + 0.3 10 10 1 5.7 64 Guaranteed −350 +350 512 Guaranteed mV mV Steps LSB rms LSB rms LSB 0.9 % FSR 1.0 1.06 V +70 +150 °C °C 5.25 5.25 V V 5.0 5.0 73 4 150 Rev. B | Page 3 of 20 V p-p V V pF nA 0.063 0 −65 4.75 3.0 Bits LSB LSB LSB LSB Bits Bits mV % FSR V/V V/V Steps 1.5 6.0 <1 0.94 Unit mA mA µA AD9822 Parameter POWER DISSIPATION 3-Channel Mode 3-Channel Mode @ 6 MHz 1-Channel Mode 1-Channel Mode @ 6 MHz 1 Min Typ Max Unit 385 335 300 250 450 410 mW mW mW mW Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp. 2 00623-002 4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 1V TYP RESET TRANSIENT 2V p-p MAX INPUT SIGNAL RANGE The PGA gain is approximately linear-in-dB and follows the equation: Gain = [ 5.7 ⎡ 63 − G ⎤ 1 + 4 .7 ⎢ ⎥ ⎣ 63 ⎦ ] where G is the register value. See Figure 15. DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, CL = 10 pF, unless otherwise noted. Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current Symbol Min VIH VIL IIH IIL CIN 2.0 VOH VOL IOH IOL 4.5 Rev. B | Page 4 of 20 Typ Max 0.8 10 10 10 0.1 50 50 Unit V V µA µA pF V V µA µA AD9822 TIMING SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V. Table 3. Parameter CLOCK PARAMETERS 3-Channel Pixel Rate 1-Channel Pixel Rate ADCCLK Pulse Width CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK1 Falling to CDSCLK2 Rising ADCCLK Falling to CDSCLK2 Rising CDSCLK2 Rising to ADCCLK Rising CDSCLK2 Falling to ADCCLK Falling CDSCLK2 Falling to CDSCLK1 Rising ADCCLK Falling to CDSCLK1 Rising Aperture Delay for CDS Clocks SERIAL INTERFACE Maximum SCLK Frequency SLOAD to SCLK Setup Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Setup Time SCLK Rising to SDATA Hold Time SCLK Falling to SDATA Valid DATA OUTPUT Output Delay Three-State to Data Valid Output Enable High to Three-State Latency (Pipeline Delay) Symbol Min tPRA tPRB tADCLK tC1 tC2 tC1C2 tADC2 tC2ADR tC2ADF tC2C1 tADC1 tAD 67 80 30 10 10 0 0 0 30 30 0 fSCLK tLS tLH tDS tDH tRDV 10 10 10 10 10 10 tOD tDV tHZ Rev. B | Page 5 of 20 Typ 40 40 2 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns 8 10 10 3 (Fixed) ns ns ns Cycles AD9822 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VIN, CAPT, CAPB Digital Inputs AVDD DRVDD AVSS Digital Outputs Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect To AVSS AVSS AVSS DRVSS DRVSS DRVSS THERMAL CHARACTERISTICS Min −0.3 −0.3 −0.5 −0.5 −0.3 −0.3 −65 Max AVDD + 0.3 AVDD + 0.3 +6.5 +6.5 +0.3 DRVDD + 0.3 150 +150 300 Unit V V V V V V °C °C °C 28-Lead 300 Mil SOIC θJA = 71.4°C/W θJC = 23°C/W 28-Lead 5.3 mm SSOP θJA = 109°C/W θJC = 39°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 20 AD9822 CDSCLK1 1 28 AVDD CDSCLK2 2 27 AVSS ADCCLK 3 26 VINR OEB 4 25 OFFSET DRVDD 5 24 VING 23 CML 22 VINB D6 8 21 CAPT D5 9 20 CAPB D4 10 19 AVSS D3 11 18 AVDD D2 12 17 SLOAD D1 13 16 SCLK (LSB) D0 14 15 SDATA DRVSS 6 (MSB) D7 7 AD9822 TOP VIEW (Not to Scale) 00623-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 Mnemonic CDSCLK1 CDSCLK2 ADCCLK OEB DRVDD DRVSS D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) SDATA SCLK SLOAD AVDD AVSS CAPB CAPT VINB CML VING OFFSET VINR AVSS AVDD Type1 DI DI DI DI P P DO DO DO DO DO DO DO DO DI/DO DI DI P P AO AO AI AO AI AO AI P P Description CDS Reference Level Sampling Clock. CDS Data Level Sampling Clock. ADC Sampling Clock. Output Enable, Active Low. Digital Output Driver Supply. Digital Output Driver Ground. Data Output MSB. ADC DB13 High Byte, ADC DB5 Low Byte. Data Output. ADC DB12 High Byte, ADC DB4 Low Byte. Data Output. ADC DB11 High Byte, ADC DB3 Low Byte. Data Output. ADC DB10 High Byte, ADC DB2 Low Byte. Data Output. ADC DB9 High Byte, ADC DB1 Low Byte. Data Output. ADC DB8 High Byte, ADC DB0 Low Byte. Data Output. ADC DB7 High Byte, Don’t Care Low Byte. Data Output LSB. ADC DB6 High Byte, Don’t Care Low Byte. Serial Interface Data Input/Output. Serial Interface Clock Input. Serial Interface Load Pulse. 5 V Analog Supply. Analog Ground. ADC Bottom Reference Voltage Decoupling. ADC Top Reference Voltage Decoupling. Analog Input, Blue Channel. Internal Bias Level Decoupling. Analog Input, Green Channel. Clamp Bias Level Decoupling. Analog Input, Red Channel. Analog Ground. 5 V Analog Supply. Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. Rev. B | Page 7 of 20 AD9822 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1 ½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value; therefore, every code must have a finite width. No missing codes guaranteed to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. Offset Error The first ADC code transition should occur at a level ½ LSB above the nominal zero-scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog value 1 ½ LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. Input Referred Noise The rms output noise is measured using histogram techniques. The ADC output codes’ standard deviation is calculated in LSB and converted to an equivalent voltage, using the relationship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the input of the AD9822 by dividing by the PGA gain. Channel-to-Channel Crosstalk In an ideal 3-channel system, the signal in one channel will not influence the signal level of another channel. The channel-tochannel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. In the AD9822, one channel is grounded and the other two channels are exercised with full-scale input signals. The change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB. Aperture Delay The time delay that occurs from when a sampling edge is applied to the AD9822 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low; therefore, the aperture delay is measured from each clock’s falling edge to the instant the actual internal sample is taken. Power Supply Rejection It specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits. Rev. B | Page 8 of 20 AD9822 ANALOG INPUTS tAD PIXEL N (R, G, B) PIXEL (N + 2) PIXEL (N + 1) tAD tC1 tC2C1 tPRA CDSCLK1 tC1C2 tC2 tC2ADF CDSCLK2 tADCLK tADC2 tADC1 tC2ADR ADCCLK R (N– 2) G (N– 2) G (N– 2) B (N– 2) B (N– 2) R (N– 1) R (N– 1) G (N– 1) G (N– 1) B (N– 1) B (N– 1) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE R (N) R (N) G (N) G (N) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE 00623-004 tOD tADCLK OUTPUT DATA D<7:0> Figure 3. 3-Channel CDS Mode Timing ANALOG INPUTS PIXEL N tAD PIXEL (N + 1) PIXEL (N + 2) tAD tC2C1 tC1 tPRB CDSCLK1 tC1C2 tC2 tADC1 CDSCLK2 tC2ADR tADCLK tADCLK tOD PIXEL (N – 4) PIXEL (N – 4) PIXEL (N – 3) PIXEL (N – 3) PIXEL (N – 2) PIXEL (N – 2) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE Figure 4. 1-Channel CDS Mode Timing Rev. B | Page 9 of 20 00623-005 ADCCLK OUTPUT DATA D<7:0> tC2ADF AD9822 PIXEL N (R, G, B) PIXEL (N + 1) tAD ANALOG INPUTS tPRA tC2 tC2ADF CDSCLK2 tADCLK tC2ADR tADC2 ADCCLK OUTPUT DATA D<7:0> R (N– 2) G (N– 2) G (N– 2) B (N– 2) B (N– 2) R (N– 1) R (N– 1) G (N– 1) G (N– 1) B (N– 1) B (N– 1) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE R (N) R (N) G (N) G (N) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE 00623-006 tOD tADCLK Figure 5. 3-Channel SHA Mode Timing PIXEL N tAD ANALOG INPUTS tPRB tC2 CDSCLK2 tC2ADR tADCLK tADCLK tOD PIXEL (N – 4) PIXEL (N – 4) PIXEL (N – 3) PIXEL (N – 3) PIXEL (N – 2) PIXEL (N – 2) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE Figure 6. 1-Channel SHA Mode Timing Rev. B | Page 10 of 20 00623-007 ADCCLK OUTPUT DATA D<7:0> tC2ADF AD9822 ADCCLK tOD HIGH BYTE DB13–DB6 LOW BYTE DB5–DB0 PIXEL N PIXEL N LOW BYTE N+2 LOW BYTE N+1 HIGH BYTE N+1 tHZ HIGH BYTE N+3 tDV 00623-008 OUTPUT DATA <D7:D0> tOD OEB Figure 7. Digital Output Data Timing SDATA R/Wb A2 A1 A0 XX tDH XX XX D8 D7 D6 D5 D4 D3 D2 D1 D0 tDS SCLK tLH 00623-009 tLS SLOAD Figure 8. Serial Write Operation Timing SDATA R/Wb A2 tDH A1 A0 XX XX tDS XX D8 D7 D6 D5 D4 D3 D2 D1 D0 tRDV SCLK tLH 00623-010 tLS SLOAD Figure 9. Serial Read Operation Timing Rev. B | Page 11 of 20 AD9822 FUNCTIONAL DESCRIPTION The AD9822 can be operated in four different modes: 3-channel CDS mode, 3-channel SHA mode, 1-channel CDS mode, and 1-channel SHA mode. Each mode is selected by programming the configuration register through the serial interface. For more information on CDS or SHA mode operation, see the Circuit Operation section. 3-CHANNEL CDS MODE In 3-channel CDS mode, the AD9822 simultaneously samples the red, green, and blue input voltages from the CCD outputs. The sampling points for each CDS are controlled by CDSCLK1 and CDSCLK2 (see Figure 10 and Figure 11). CDSCLK1’s falling edge samples the reference level of the CCD waveform, and CDSCLK2’s falling edge samples the data level of the CCD waveform. Each CDS amplifier outputs the difference between the CCD’s reference and data levels. The output voltage of each CDS amplifier is then level-shifted by an offset DAC. The voltages are scaled by the three PGAs before being multiplexed through the 14-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The offset and gain values for the red, green, and blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX register. Timing for this mode is shown in Figure 3. It is recommended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK. However, this is not required to satisfy the minimum timing constraints. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three clock cycles. The input signal is sampled with respect to the voltage applied to the OFFSET pin (see Figure 12). With the OFFSET pin grounded, a 0 V input corresponds to the ADC’s zero-scale output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin is subtracted from the voltages applied to the red, green, and blue inputs in the first amplifier stage of the AD9822. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 5. CDSCLK1 should be grounded in this mode. Although not required, it is recommended that the falling edge of CDSCLK2 occur coincident with or before the rising edge of ADCCLK. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three ADCCLK cycles. The offset and gain values for the red, green, and blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX register. 1-CHANNEL CDS MODE This mode operates in the same way as the 3-channel CDS mode. The difference is that the multiplexer remains fixed in this mode; therefore, only the channel specified in the MUX register is processed. Timing for this mode is shown in Figure 4. 1-CHANNEL SHA MODE 3-CHANNEL SHA MODE This mode operates in the same way as the 3-channel SHA mode, except the multiplexer remains stationary. Only the channel specified in the MUX register is processed. In 3-channel SHA mode, the AD9822 simultaneously samples the red, green, and blue input voltages. The sampling point is controlled by CDSCLK2. CDSCLK2’s falling edge samples the input waveforms on each channel. The output voltages from the three SHAs are modified by the offset DACs and then scaled by the three PGAs. The outputs of the PGAs are then multiplexed through the 14-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The input signal is sampled with respect to the voltage applied to the OFFSET pin. With the OFFSET pin grounded, a 0 V input corresponds to the ADC’s zero-scale output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin is subtracted from the voltages applied to the red, green, and blue inputs in the first amplifier stage of the AD9822. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 6. CDSCLK1 should be grounded in this mode of operation. Rev. B | Page 12 of 20 AD9822 INTERNAL REGISTER DESCRIPTIONS Table 6. Internal Register Map Register Name Configuration MUX Red PGA Green PGA Blue PGA Red Offset Green Offset Blue Offset Address A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D8 0 0 0 0 0 MSB MSB MSB D7 0 RGB/BGR 0 0 0 D6 VREF Red 0 0 0 Data Bits D D4 3Ch/1Ch CDS On Green Blue MSB MSB MSB D3 Clamp 0 D2 Pwr Dn 0 D1 0 0 D0 0 0 LSB LSB LSB LSB LSB LSB Configuration Register The Configuration Register controls the AD9822’s operating mode and bias levels. Bits D8, D1, and D0 should always be set low. Bit D7 sets the full-scale voltage range of the AD9822’s ADC to either 4 V (high) or 2 V (low). Bit D6 controls the internal voltage reference. If the AD9822’s internal voltage reference is used, this bit is set high. Setting Bit D6 low disables the internal voltage reference, allowing an external voltage reference to be used. Bit D5 configures the AD9822 for either the 3-channel (high) or 1-channel (low) mode of operation. Setting Bit D4 high enables the CDS mode of operation and setting this bit low enables the SHA mode of operation. Bit D3 sets the dc bias level of the AD9822’s input clamp. This bit should always be set high for the 4 V clamp bias, unless a CCD with a reset feedthrough transient exceeding 2 V is used. If the 3 V clamp bias level is used, the peak-to-peak input signal range to the AD9822 is reduced to 3 V maximum. Bit D2 controls the power-down mode. Setting Bit D2 high places the AD9822 into a very low power “sleep” mode. All register contents are retained while the AD9822 is in the power-down state. Table 7. Configuration Register Settings D8 Set to 0 1 D7 Set to 0 D6 Internal VREF 1 = Enabled1 0 = Disabled D5 No. of Channels 1 = 3-Ch Mode1 0 = 1-Ch Mode D4 CDS Operation 1 = CDS Mode1 0 = SHA Mode D3 Input Clamp Bias 1 = 4 V1 0=3V D2 Power-Down 1 = On 0 = Off (Normal)1 D1 Set to 0 D0 Set to 0 Power-on default value. MUX Register The MUX register controls the sampling channel order in the AD9822. Bits D8, D3, D2, D1, and D0 should always be set low. Bit D7 is used when operating in 3-channel mode. Setting Bit D7 high sequences the MUX to sample the red channel first, then the green channel, and then the blue channel. When in this mode, the CDSCLK2 pulse always resets the MUX to sample the red channel first (see Figure 3). When Bit D7 is set low, the channel order is reversed to blue first, green second, and red third. The CDSCLK2 pulse always resets the MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in 1-channel mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX remains stationary during 1-channel mode. Table 8. MUX Register Settings D8 Set to 0 1 D7 3-Channel Select 1 = R-G-B1 0 = B-G-R D6 1-Channel Select 1 = RED1 0 = Off D5 1-Channel Select 1 = GREEN 0 = Off1 D4 1-Channel Select 1 = BLUE 0 = Off1 Power-on default value. Rev. B | Page 13 of 20 D3 Set to 0 D2 Set to 0 D1 Set to 0 D0 Set to 0 AD9822 PGA Gain Registers There are three PGA registers for individually programming the gain in the red, green, and blue channels. Bits D8, D7, and D6 in each register must be set low, and Bits D5 through D0 control the gain range in 64 increments. See Figure 15 for the PGA gain vs. the PGA register code. The coding for the PGA registers is straight binary, with an all 0s word corresponding to the minimum gain setting (1×) and an all 1s word corresponding to the maximum gain setting (5.7×). Table 9. PGA Gain Register Settings D8 Set to 0 0 0 D7 Set to 0 0 0 D6 Set to 0 0 0 D5 MSB 0 0 D4 0 0 0 0 0 0 1 1 1 1 1 D3 0 0 D2 0 0 • • • 1 1 D1 0 0 0 0 D0 LSB 01 1 1 1 1 1 0 1 Gain (V/V) 1.0 1.013 • • • 5.4 5.7 Gain (dB) 0.0 0.12 • • • 14.6 15.1 Power-on default value. Offset Registers There are three PGA registers for individually programming the offset in the red, green, and blue channels. Bits D8 through D0 control the offset range from −350 mV to +350 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. Table 10 shows the offset range as a function of the Bits D8 through D0. Table 10. Offset Register Settings D8 (MSB) 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 D3 0 0 • • • 1 0 0 • • • 1 D2 0 0 D1 0 0 D0 (LSB) 01 1 1 0 0 1 0 0 1 0 1 1 1 1 Power-on default value. Rev. B | Page 14 of 20 Offset (mV) 0 +1.2 • • • +350 0 −1.2 • • • −350 AD9822 CIRCUIT OPERATION ANALOG INPUTS—CDS MODE EXTERNAL INPUT COUPLING CAPACITORS Figure 10 shows the analog input configuration for the CDS mode of operation. Figure 11 shows the internal timing for the sampling switches. The CCD reference level is sampled when CDSCLK1 transitions from high to low, opening S1. The CCD data level is sampled when CDSCLK2 transitions from high to low, opening S2. S3 is then closed, generating a differential output voltage representing the difference between the two sampled levels. The recommended value for the input coupling capacitors is 0.1 µF. While it is possible to use a smaller capacitor, this larger value is chosen for several reasons: • Signal Attenuation: The input coupling capacitor creates a capacitive divider with a CMOS integrated circuit’s input capacitance, attenuating the CCD signal level. CIN should be large relative to the IC’s 10 pF input capacitance in order to minimize this effect. The input clamp is controlled by CDSCLK1. When CDSCLK1 is high, S4 closes and the internal bias voltage is connected to the analog input. The bias voltage charges the external 0.1 µF input capacitor, level-shifting the CCD signal into the AD9822’s input common-mode range. The time constant of the input clamp is determined by the internal 5 kΩ resistance and the external 0.1 µF input capacitance. AD9822 S1 VINR 2pF CML CCD SIGNAL CIN 0.1µF S3 5kΩ CML S2 AVDD OFFSET 1µF 1.7kΩ 4V 0.1µF • Sampling Errors: The internal 2 pF sample capacitors have a “memory” of the previously sampled pixel. There is a charge redistribution error between CIN and the internal sample capacitors for larger pixel-to-pixel voltage swings. As the value of CIN is reduced, the resulting error in the sampled voltage increases. With a CIN value of 0.1 µF, the charge redistribution error is less than 1 LSB for a full-scale, pixel-topixel voltage swing. INPUT CLAMP LEVEL 2.2kΩ IS SELECTED IN THE CONFIGURATION REGISTER. 6.9kΩ 3V 00362-011 S4 + 2pF • Linearity: Some of the input capacitance of a CMOS IC is junction capacitance, which varies nonlinearly with applied voltage. If the input coupling capacitor is too small, the attenuation of the CCD signal varies nonlinearly with signal level. This degrades the system linearity performance. Figure 10. CDS Mode Input Configuration (All Three Channels are Identical) S1, S4 CLOSED S1, S4 CLOSED S1, S4 OPEN S2 CLOSED CDSCLK2 S2 OPEN Q3 (INTERNAL) S3 OPEN S2 CLOSED S3 CLOSED S3 CLOSED 00623-012 CDSCLK1 Figure 11. CDS Mode Internal Switch Timing Rev. B | Page 15 of 20 AD9822 ANALOG INPUTS—SHA MODE AD9822 Figure 12 shows the analog input configuration for the SHA mode of operation. Figure 13 shows the internal timing for the sampling switches. The input signal is sampled when CDSCLK2 transitions from high to low, opening S1. The voltage on the OFFSET pin is also sampled on the falling edge of CDSCLK2, when S2 opens. S3 is then closed, generating a differential output voltage representing the difference between the sampled input voltage and the OFFSET voltage. The input clamp is disabled during SHA mode operation. VINR RED SHA BLUE-OFFSET VINB BLUE VREF FROM CIS MODULE AVDD OFFSET 0.1µF 00623-015 R2 2pF CML S2 S3 2pF RED Figure 14. SHA Mode Used with External DC Offset CML PROGRAMMABLE GAIN AMPLIFIERS (PGA) VING GREEN BLUE 00623-013 VINB The AD9822 uses one PGA for each channel. Each PGA has a gain range from 1× (0 dB) to 5.8× (15.5 dB), adjustable in 64 steps. Figure 15 shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately linear-in-dB, the gain in V/V varies nonlinearly with register code, following the equation Figure 12. SHA Mode Input Configuration (All Three Channels are Identical) S1, S2 CLOSED Gain = S1, S2 CLOSED S3 CLOSED S3 CLOSED S3 OPEN 00623-014 S1, S2 OPEN where G is the decimal value of the gain register contents and varies from 0 to 63. GAIN (dB) Figure 13. SHA Mode Internal Switch Timing Figure 14 shows how the OFFSET pin may be used in a CIS application for coarse offset adjustment. Many CIS signals have dc offsets ranging from several hundred millivolts to more than 1 V. By connecting the appropriate dc voltage to the OFFSET pin, the CIS signal is restored to 0. After the large dc offset is removed, the signal can be scaled using the PGA to maximize the ADC’s dynamic range. 5.7 ⎡ 63 − G ⎤ 1 + 4.7 ⎢ ⎥ ⎣ 63 ⎦ 15 5.7 12 5.0 9 4.0 6 3.0 3 2.0 1.0 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 PGA REGISTER VALUE (Decimal) Figure 15. PGA Gain Transfer Function Rev. B | Page 16 of 20 GAIN (V/V) OFFSET OPTIONAL DC OFFSET (OR CONNECT TO GND) Q3 (INTERNAL) GREEN-OFFSET DC OFFSET S1 INPUT SIGNAL CDSCLK2 SHA VING 00623-016 VINR RED-OFFSET GREEN R1 AD9822 SHA AD9822 APPLICATIONS CDSCLK2 should occur coincident with or before the rising edge of ADCCLK (see Figure 3 through Figure 6 for timing). All 0.1 µF decoupling capacitors should be located as close as possible to the AD9822 pins. When operating in single-channel mode, the unused analog inputs should be grounded. CIRCUIT AND LAYOUT RECOMMENDATIONS Figure 16 shows the recommended circuit configuration for 3-channel CDS mode operation. The recommended input coupling capacitor value is 0.1 µF (see the Circuit Operation section). A single ground plane is recommended for the AD9822. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the AD9822. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of Figure 17 shows the recommended circuit configuration for 3-channel SHA mode. All of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the AD9822 without the use of coupling capacitors. The analog input signals must already be dc-biased between 0 V and 2 V (see the Circuit Operation section). 0.1µF 5V 5V/3V 1 CDSCLK1 AVDD 28 2 CDSCLK2 AVSS 27 3 ADCCLK 4 OEB 5 DRVDD 6 DRVSS 7 D7 (MSB) 0.1µF DATA OUTPUTS RED INPUT 3 0.1µF 0.1µF GREEN INPUT 0.1µF VINR 26 BLUE INPUT OFFSET 25 VING 24 AD9822 0.1µF 0.1µF 1.0µF CML 23 0.1µF VINB 22 8 D6 CAPT 21 9 D5 CAPB 20 10 D4 AVSS 19 11 D3 AVDD 18 12 D2 SLOAD 17 13 D1 14 D0 (LSB) 0.1µF + 10µF 0.1µF 0.1µF SCLK 16 5V 00623-017 CLOCK INPUTS SDATA 15 8 3 SERIAL INTERFACE Figure 16. Recommended Circuit Configuration, 3-Channel CDS Mode 5V RED INPUT 5V/3V 0.1µF 1 CDSCLK1 AVDD 28 2 CDSCLK2 AVSS 27 3 ADCCLK 4 OEB 5 DRVDD 6 DRVSS 7 D7 (MSB) 8 D6 CAPT 21 9 D5 CAPB 20 GREEN INPUT VINR 26 BLUE INPUT OFFSET 25 AD9822 VING 24 0.1µF VINB 22 AVSS 19 11 D3 AVDD 18 12 D2 SLOAD 17 14 D0 (LSB) 0.1µF CML 23 10 D4 13 D1 DATA OUTPUTS 0.1µF 0.1µF + 10µF 0.1µF SCLK 16 5V SDATA 15 8 0.1µF 3 SERIAL INTERFACE 00623-018 CLOCK INPUTS 3 Figure 17. Recommended Circuit Configuration, 3-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground) Rev. B | Page 17 of 20 AD9822 OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 14 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) × 45° 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 8° 1.27 (0.0500) 0.51 (0.0201) SEATING 0.33 (0.0130) 0° BSC PLANE 0.31 (0.0122) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 18. 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 7.40 14 1 PIN 1 1.85 1.75 1.65 2.00 MAX COPLANARITY 0.10 0.25 0.09 0.05 MIN 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH Figure 19. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE Model AD9822JR AD9822JRRL AD9822JRS AD9822JRSRL AD9822JRSZ1 AD9822JRSZRL1 1 Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Package Description 28-Lead SOIC 28-Lead SOIC 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP Z = Pb-free part. Rev. B | Page 18 of 20 Package Options R-28 R-28 RS-28 RS-28 RS-28 RS-28 AD9822 NOTES Rev. B | Page 19 of 20 AD9822 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00623–0–2/05(B) Rev. B | Page 20 of 20